lxdream 0.9.1| filename | src/sh4/sh4x86.c |
| changeset | 732:f05753bbe723 |
| prev | 675:b97020f9af1c |
| next | 733:633ee022f52e |
| author | nkeynes |
| date | Thu Jul 10 01:46:00 2008 +0000 (13 years ago) |
| permissions | -rw-r--r-- |
| last change | Fix alignment check for 64-bit FMOVs Add missing MMU code etc to FMOV emu implementation |
| file | annotate | diff | log | raw |
1.1 --- a/src/sh4/sh4x86.c Mon May 26 11:01:42 2008 +00001.2 +++ b/src/sh4/sh4x86.c Thu Jul 10 01:46:00 2008 +00001.3 @@ -264,6 +264,14 @@1.4 TEST_imm32_r32( 0x00000003, x86reg ); \1.5 JNE_exc(EXC_DATA_ADDR_WRITE);1.7 +#define check_ralign64( x86reg ) \1.8 + TEST_imm32_r32( 0x00000007, x86reg ); \1.9 + JNE_exc(EXC_DATA_ADDR_READ)1.10 +1.11 +#define check_walign64( x86reg ) \1.12 + TEST_imm32_r32( 0x00000007, x86reg ); \1.13 + JNE_exc(EXC_DATA_ADDR_WRITE);1.14 +1.15 #define UNDEF()1.16 #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }1.17 #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)1.18 @@ -3142,17 +3150,19 @@1.19 check_fpuen();1.20 load_reg( R_EAX, Rm );1.21 ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );1.22 - check_ralign32( R_EAX );1.23 - MMU_TRANSLATE_READ( R_EAX );1.24 load_spreg( R_EDX, R_FPSCR );1.25 TEST_imm32_r32( FPSCR_SZ, R_EDX );1.26 JNE_rel8(doublesize);1.28 + check_ralign32( R_EAX );1.29 + MMU_TRANSLATE_READ( R_EAX );1.30 MEM_READ_LONG( R_EAX, R_EAX );1.31 store_fr( R_EAX, FRn );1.32 JMP_rel8(end);1.34 JMP_TARGET(doublesize);1.35 + check_ralign64( R_EAX );1.36 + MMU_TRANSLATE_READ( R_EAX );1.37 MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );1.38 store_dr0( R_ECX, FRn );1.39 store_dr1( R_EAX, FRn );1.40 @@ -3168,17 +3178,19 @@1.41 check_fpuen();1.42 load_reg( R_EAX, Rn );1.43 ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );1.44 - check_walign32( R_EAX );1.45 - MMU_TRANSLATE_WRITE( R_EAX );1.46 load_spreg( R_EDX, R_FPSCR );1.47 TEST_imm32_r32( FPSCR_SZ, R_EDX );1.48 JNE_rel8(doublesize);1.50 + check_walign32( R_EAX );1.51 + MMU_TRANSLATE_WRITE( R_EAX );1.52 load_fr( R_ECX, FRm );1.53 MEM_WRITE_LONG( R_EAX, R_ECX ); // 121.54 JMP_rel8(end);1.56 JMP_TARGET(doublesize);1.57 + check_walign64( R_EAX );1.58 + MMU_TRANSLATE_WRITE( R_EAX );1.59 load_dr0( R_ECX, FRm );1.60 load_dr1( R_EDX, FRm );1.61 MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );1.62 @@ -3193,17 +3205,19 @@1.63 COUNT_INST(I_FMOV5);1.64 check_fpuen();1.65 load_reg( R_EAX, Rm );1.66 - check_ralign32( R_EAX );1.67 - MMU_TRANSLATE_READ( R_EAX );1.68 load_spreg( R_EDX, R_FPSCR );1.69 TEST_imm32_r32( FPSCR_SZ, R_EDX );1.70 JNE_rel8(doublesize);1.72 + check_ralign32( R_EAX );1.73 + MMU_TRANSLATE_READ( R_EAX );1.74 MEM_READ_LONG( R_EAX, R_EAX );1.75 store_fr( R_EAX, FRn );1.76 JMP_rel8(end);1.78 JMP_TARGET(doublesize);1.79 + check_ralign64( R_EAX );1.80 + MMU_TRANSLATE_READ( R_EAX );1.81 MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );1.82 store_dr0( R_ECX, FRn );1.83 store_dr1( R_EAX, FRn );1.84 @@ -3217,18 +3231,20 @@1.85 COUNT_INST(I_FMOV6);1.86 check_fpuen();1.87 load_reg( R_EAX, Rm );1.88 - check_ralign32( R_EAX );1.89 - MMU_TRANSLATE_READ( R_EAX );1.90 load_spreg( R_EDX, R_FPSCR );1.91 TEST_imm32_r32( FPSCR_SZ, R_EDX );1.92 JNE_rel8(doublesize);1.94 + check_ralign32( R_EAX );1.95 + MMU_TRANSLATE_READ( R_EAX );1.96 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.97 MEM_READ_LONG( R_EAX, R_EAX );1.98 store_fr( R_EAX, FRn );1.99 JMP_rel8(end);1.101 JMP_TARGET(doublesize);1.102 + check_ralign64( R_EAX );1.103 + MMU_TRANSLATE_READ( R_EAX );1.104 ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );1.105 MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );1.106 store_dr0( R_ECX, FRn );1.107 @@ -3244,17 +3260,19 @@1.108 COUNT_INST(I_FMOV2);1.109 check_fpuen();1.110 load_reg( R_EAX, Rn );1.111 - check_walign32( R_EAX );1.112 - MMU_TRANSLATE_WRITE( R_EAX );1.113 load_spreg( R_EDX, R_FPSCR );1.114 TEST_imm32_r32( FPSCR_SZ, R_EDX );1.115 JNE_rel8(doublesize);1.117 + check_walign32( R_EAX );1.118 + MMU_TRANSLATE_WRITE( R_EAX );1.119 load_fr( R_ECX, FRm );1.120 MEM_WRITE_LONG( R_EAX, R_ECX ); // 121.121 JMP_rel8(end);1.123 JMP_TARGET(doublesize);1.124 + check_walign64( R_EAX );1.125 + MMU_TRANSLATE_WRITE( R_EAX );1.126 load_dr0( R_ECX, FRm );1.127 load_dr1( R_EDX, FRm );1.128 MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );1.129 @@ -3268,11 +3286,11 @@1.130 COUNT_INST(I_FMOV3);1.131 check_fpuen();1.132 load_reg( R_EAX, Rn );1.133 - check_walign32( R_EAX );1.134 load_spreg( R_EDX, R_FPSCR );1.135 TEST_imm32_r32( FPSCR_SZ, R_EDX );1.136 JNE_rel8(doublesize);1.138 + check_walign32( R_EAX );1.139 ADD_imm8s_r32( -4, R_EAX );1.140 MMU_TRANSLATE_WRITE( R_EAX );1.141 load_fr( R_ECX, FRm );1.142 @@ -3281,6 +3299,7 @@1.143 JMP_rel8(end);1.145 JMP_TARGET(doublesize);1.146 + check_walign64( R_EAX );1.147 ADD_imm8s_r32(-8,R_EAX);1.148 MMU_TRANSLATE_WRITE( R_EAX );1.149 load_dr0( R_ECX, FRm );
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