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lxdream.org :: lxdream/src/sh4/sh4x86.in :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 732:f05753bbe723
prev675:b97020f9af1c
next733:633ee022f52e
author nkeynes
date Thu Jul 10 01:46:00 2008 +0000 (11 years ago)
permissions -rw-r--r--
last change Fix alignment check for 64-bit FMOVs
Add missing MMU code etc to FMOV emu implementation
file annotate diff log raw
1.1 --- a/src/sh4/sh4x86.in Mon May 26 11:01:42 2008 +0000
1.2 +++ b/src/sh4/sh4x86.in Thu Jul 10 01:46:00 2008 +0000
1.3 @@ -264,6 +264,14 @@
1.4 TEST_imm32_r32( 0x00000003, x86reg ); \
1.5 JNE_exc(EXC_DATA_ADDR_WRITE);
1.6
1.7 +#define check_ralign64( x86reg ) \
1.8 + TEST_imm32_r32( 0x00000007, x86reg ); \
1.9 + JNE_exc(EXC_DATA_ADDR_READ)
1.10 +
1.11 +#define check_walign64( x86reg ) \
1.12 + TEST_imm32_r32( 0x00000007, x86reg ); \
1.13 + JNE_exc(EXC_DATA_ADDR_WRITE);
1.14 +
1.15 #define UNDEF()
1.16 #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
1.17 #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
1.18 @@ -1817,17 +1825,19 @@
1.19 COUNT_INST(I_FMOV2);
1.20 check_fpuen();
1.21 load_reg( R_EAX, Rn );
1.22 - check_walign32( R_EAX );
1.23 - MMU_TRANSLATE_WRITE( R_EAX );
1.24 load_spreg( R_EDX, R_FPSCR );
1.25 TEST_imm32_r32( FPSCR_SZ, R_EDX );
1.26 JNE_rel8(doublesize);
1.27
1.28 + check_walign32( R_EAX );
1.29 + MMU_TRANSLATE_WRITE( R_EAX );
1.30 load_fr( R_ECX, FRm );
1.31 MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
1.32 JMP_rel8(end);
1.33
1.34 JMP_TARGET(doublesize);
1.35 + check_walign64( R_EAX );
1.36 + MMU_TRANSLATE_WRITE( R_EAX );
1.37 load_dr0( R_ECX, FRm );
1.38 load_dr1( R_EDX, FRm );
1.39 MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
1.40 @@ -1838,17 +1848,19 @@
1.41 COUNT_INST(I_FMOV5);
1.42 check_fpuen();
1.43 load_reg( R_EAX, Rm );
1.44 - check_ralign32( R_EAX );
1.45 - MMU_TRANSLATE_READ( R_EAX );
1.46 load_spreg( R_EDX, R_FPSCR );
1.47 TEST_imm32_r32( FPSCR_SZ, R_EDX );
1.48 JNE_rel8(doublesize);
1.49
1.50 + check_ralign32( R_EAX );
1.51 + MMU_TRANSLATE_READ( R_EAX );
1.52 MEM_READ_LONG( R_EAX, R_EAX );
1.53 store_fr( R_EAX, FRn );
1.54 JMP_rel8(end);
1.55
1.56 JMP_TARGET(doublesize);
1.57 + check_ralign64( R_EAX );
1.58 + MMU_TRANSLATE_READ( R_EAX );
1.59 MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
1.60 store_dr0( R_ECX, FRn );
1.61 store_dr1( R_EAX, FRn );
1.62 @@ -1859,11 +1871,11 @@
1.63 COUNT_INST(I_FMOV3);
1.64 check_fpuen();
1.65 load_reg( R_EAX, Rn );
1.66 - check_walign32( R_EAX );
1.67 load_spreg( R_EDX, R_FPSCR );
1.68 TEST_imm32_r32( FPSCR_SZ, R_EDX );
1.69 JNE_rel8(doublesize);
1.70
1.71 + check_walign32( R_EAX );
1.72 ADD_imm8s_r32( -4, R_EAX );
1.73 MMU_TRANSLATE_WRITE( R_EAX );
1.74 load_fr( R_ECX, FRm );
1.75 @@ -1872,6 +1884,7 @@
1.76 JMP_rel8(end);
1.77
1.78 JMP_TARGET(doublesize);
1.79 + check_walign64( R_EAX );
1.80 ADD_imm8s_r32(-8,R_EAX);
1.81 MMU_TRANSLATE_WRITE( R_EAX );
1.82 load_dr0( R_ECX, FRm );
1.83 @@ -1886,18 +1899,20 @@
1.84 COUNT_INST(I_FMOV6);
1.85 check_fpuen();
1.86 load_reg( R_EAX, Rm );
1.87 - check_ralign32( R_EAX );
1.88 - MMU_TRANSLATE_READ( R_EAX );
1.89 load_spreg( R_EDX, R_FPSCR );
1.90 TEST_imm32_r32( FPSCR_SZ, R_EDX );
1.91 JNE_rel8(doublesize);
1.92
1.93 + check_ralign32( R_EAX );
1.94 + MMU_TRANSLATE_READ( R_EAX );
1.95 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.96 MEM_READ_LONG( R_EAX, R_EAX );
1.97 store_fr( R_EAX, FRn );
1.98 JMP_rel8(end);
1.99
1.100 JMP_TARGET(doublesize);
1.101 + check_ralign64( R_EAX );
1.102 + MMU_TRANSLATE_READ( R_EAX );
1.103 ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
1.104 MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
1.105 store_dr0( R_ECX, FRn );
1.106 @@ -1911,17 +1926,19 @@
1.107 check_fpuen();
1.108 load_reg( R_EAX, Rn );
1.109 ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
1.110 - check_walign32( R_EAX );
1.111 - MMU_TRANSLATE_WRITE( R_EAX );
1.112 load_spreg( R_EDX, R_FPSCR );
1.113 TEST_imm32_r32( FPSCR_SZ, R_EDX );
1.114 JNE_rel8(doublesize);
1.115
1.116 + check_walign32( R_EAX );
1.117 + MMU_TRANSLATE_WRITE( R_EAX );
1.118 load_fr( R_ECX, FRm );
1.119 MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
1.120 JMP_rel8(end);
1.121
1.122 JMP_TARGET(doublesize);
1.123 + check_walign64( R_EAX );
1.124 + MMU_TRANSLATE_WRITE( R_EAX );
1.125 load_dr0( R_ECX, FRm );
1.126 load_dr1( R_EDX, FRm );
1.127 MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
1.128 @@ -1934,17 +1951,19 @@
1.129 check_fpuen();
1.130 load_reg( R_EAX, Rm );
1.131 ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
1.132 - check_ralign32( R_EAX );
1.133 - MMU_TRANSLATE_READ( R_EAX );
1.134 load_spreg( R_EDX, R_FPSCR );
1.135 TEST_imm32_r32( FPSCR_SZ, R_EDX );
1.136 JNE_rel8(doublesize);
1.137
1.138 + check_ralign32( R_EAX );
1.139 + MMU_TRANSLATE_READ( R_EAX );
1.140 MEM_READ_LONG( R_EAX, R_EAX );
1.141 store_fr( R_EAX, FRn );
1.142 JMP_rel8(end);
1.143
1.144 JMP_TARGET(doublesize);
1.145 + check_ralign64( R_EAX );
1.146 + MMU_TRANSLATE_READ( R_EAX );
1.147 MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
1.148 store_dr0( R_ECX, FRn );
1.149 store_dr1( R_EAX, FRn );
.