1.1 --- a/src/aica/armdasm.c	Tue Jan 01 05:08:38 2008 +0000
     1.2 +++ b/src/aica/armdasm.c	Mon Jul 21 01:01:39 2008 +0000
     1.3 @@ -48,142 +48,142 @@
     1.4  
     1.5  
     1.6  const struct reg_desc_struct arm_reg_map[] = 
     1.7 -    { {"R0", REG_INT, &armr.r[0]}, {"R1", REG_INT, &armr.r[1]},
     1.8 -    {"R2", REG_INT, &armr.r[2]}, {"R3", REG_INT, &armr.r[3]},
     1.9 -    {"R4", REG_INT, &armr.r[4]}, {"R5", REG_INT, &armr.r[5]},
    1.10 -    {"R6", REG_INT, &armr.r[6]}, {"R7", REG_INT, &armr.r[7]},
    1.11 -    {"R8", REG_INT, &armr.r[8]}, {"R9", REG_INT, &armr.r[9]},
    1.12 -    {"R10",REG_INT, &armr.r[10]}, {"R11",REG_INT, &armr.r[11]},
    1.13 -    {"R12",REG_INT, &armr.r[12]}, {"R13",REG_INT, &armr.r[13]},
    1.14 -    {"R14",REG_INT, &armr.r[14]}, {"R15",REG_INT, &armr.r[15]},
    1.15 -    {"CPSR", REG_INT, &armr.cpsr}, {"SPSR", REG_INT, &armr.spsr},
    1.16 -    {NULL, 0, NULL} };
    1.17 +{ {"R0", REG_INT, &armr.r[0]}, {"R1", REG_INT, &armr.r[1]},
    1.18 +        {"R2", REG_INT, &armr.r[2]}, {"R3", REG_INT, &armr.r[3]},
    1.19 +        {"R4", REG_INT, &armr.r[4]}, {"R5", REG_INT, &armr.r[5]},
    1.20 +        {"R6", REG_INT, &armr.r[6]}, {"R7", REG_INT, &armr.r[7]},
    1.21 +        {"R8", REG_INT, &armr.r[8]}, {"R9", REG_INT, &armr.r[9]},
    1.22 +        {"R10",REG_INT, &armr.r[10]}, {"R11",REG_INT, &armr.r[11]},
    1.23 +        {"R12",REG_INT, &armr.r[12]}, {"R13",REG_INT, &armr.r[13]},
    1.24 +        {"R14",REG_INT, &armr.r[14]}, {"R15",REG_INT, &armr.r[15]},
    1.25 +        {"CPSR", REG_INT, &armr.cpsr}, {"SPSR", REG_INT, &armr.spsr},
    1.26 +        {NULL, 0, NULL} };
    1.27  
    1.28  
    1.29  const struct cpu_desc_struct arm_cpu_desc = 
    1.30 -    { "ARM7", arm_disasm_instruction, arm_execute_instruction, arm_has_page,
    1.31 -      arm_set_breakpoint, arm_clear_breakpoint, arm_get_breakpoint, 4,
    1.32 -      (char *)&armr, sizeof(armr), arm_reg_map,
    1.33 -      &armr.r[15] };
    1.34 +{ "ARM7", arm_disasm_instruction, arm_execute_instruction, arm_has_page,
    1.35 +        arm_set_breakpoint, arm_clear_breakpoint, arm_get_breakpoint, 4,
    1.36 +        (char *)&armr, sizeof(armr), arm_reg_map,
    1.37 +        &armr.r[15] };
    1.38  const struct cpu_desc_struct armt_cpu_desc = 
    1.39 -    { "ARM7T", armt_disasm_instruction, arm_execute_instruction, arm_has_page,
    1.40 -      arm_set_breakpoint, arm_clear_breakpoint, arm_get_breakpoint, 2,
    1.41 -      (char*)&armr, sizeof(armr), arm_reg_map,
    1.42 -      &armr.r[15] };
    1.43 +{ "ARM7T", armt_disasm_instruction, arm_execute_instruction, arm_has_page,
    1.44 +        arm_set_breakpoint, arm_clear_breakpoint, arm_get_breakpoint, 2,
    1.45 +        (char*)&armr, sizeof(armr), arm_reg_map,
    1.46 +        &armr.r[15] };
    1.47  
    1.48  
    1.49  
    1.50  
    1.51  char *conditionNames[] = { "EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", 
    1.52 -                           "HI", "LS", "GE", "LT", "GT", "LE", "  " /*AL*/, "NV" };
    1.53 -                           
    1.54 -                         /* fsxc */
    1.55 +        "HI", "LS", "GE", "LT", "GT", "LE", "  " /*AL*/, "NV" };
    1.56 +
    1.57 +/* fsxc */
    1.58  char *msrFieldMask[] = { "", "c", "x", "xc", "s", "sc", "sx", "sxc",
    1.59 -	                     "f", "fc", "fx", "fxc", "fs", "fsc", "fsx", "fsxc" };
    1.60 +        "f", "fc", "fx", "fxc", "fs", "fsc", "fsx", "fsxc" };
    1.61  char *ldmModes[] = { "DA", "IA", "DB", "IB" };
    1.62  
    1.63  #define UNIMP(ir) snprintf( buf, len, "???     " )
    1.64  
    1.65  int arm_disasm_shift_operand( uint32_t ir, char *buf, int len )
    1.66  {
    1.67 -	uint32_t operand, tmp;
    1.68 -	if( IFLAG(ir) == 0 ) {
    1.69 -		switch(SHIFT(ir)) {
    1.70 -		case 0: /* (Rm << imm) */
    1.71 -		    tmp = SHIFTIMM(ir);
    1.72 -		    if( tmp != 0 ) {
    1.73 -			return snprintf(buf, len, "R%d << %d", RM(ir), tmp );
    1.74 -		    } else {
    1.75 -			return snprintf(buf, len, "R%d", RM(ir));
    1.76 -		    }
    1.77 -		case 1: /* (Rm << Rs) */
    1.78 -			return snprintf(buf, len, "R%d << R%d", RM(ir), RS(ir) );
    1.79 -		case 2: /* (Rm >> imm) */
    1.80 -			return snprintf(buf, len, "R%d >> %d", RM(ir), SHIFTIMM(ir) );
    1.81 -		case 3: /* (Rm >> Rs) */
    1.82 -			return snprintf(buf, len, "R%d >> R%d", RM(ir), RS(ir) );
    1.83 -		case 4: /* (Rm >>> imm) */
    1.84 -			return snprintf(buf, len, "R%d >>> %d", RM(ir), SHIFTIMM(ir) );
    1.85 -		case 5: /* (Rm >>> Rs) */
    1.86 -			return snprintf(buf, len, "R%d >>> R%d", RM(ir), RS(ir) );
    1.87 -		case 6:
    1.88 -			tmp = SHIFTIMM(ir);
    1.89 -			if( tmp == 0 ) /* RRX aka rotate with carry */
    1.90 -				return snprintf(buf, len, "R%d roc 1", RM(ir) );
    1.91 -			else
    1.92 -				return snprintf(buf, len, "R%d rot %d", RM(ir), SHIFTIMM(ir) );
    1.93 -		case 7:
    1.94 -			return snprintf(buf, len, "R%d rot R%d", RM(ir), RS(ir) );
    1.95 -		}
    1.96 -	} else {
    1.97 -		operand = IMM8(ir);
    1.98 -		tmp = IMMROT(ir);
    1.99 -		operand = ROTATE_RIGHT_LONG(operand, tmp);
   1.100 -		return snprintf(buf, len, "#%08Xh", operand );
   1.101 -	}
   1.102 -	return 0;
   1.103 +    uint32_t operand, tmp;
   1.104 +    if( IFLAG(ir) == 0 ) {
   1.105 +        switch(SHIFT(ir)) {
   1.106 +        case 0: /* (Rm << imm) */
   1.107 +            tmp = SHIFTIMM(ir);
   1.108 +            if( tmp != 0 ) {
   1.109 +                return snprintf(buf, len, "R%d << %d", RM(ir), tmp );
   1.110 +            } else {
   1.111 +                return snprintf(buf, len, "R%d", RM(ir));
   1.112 +            }
   1.113 +        case 1: /* (Rm << Rs) */
   1.114 +            return snprintf(buf, len, "R%d << R%d", RM(ir), RS(ir) );
   1.115 +        case 2: /* (Rm >> imm) */
   1.116 +            return snprintf(buf, len, "R%d >> %d", RM(ir), SHIFTIMM(ir) );
   1.117 +        case 3: /* (Rm >> Rs) */
   1.118 +            return snprintf(buf, len, "R%d >> R%d", RM(ir), RS(ir) );
   1.119 +        case 4: /* (Rm >>> imm) */
   1.120 +            return snprintf(buf, len, "R%d >>> %d", RM(ir), SHIFTIMM(ir) );
   1.121 +        case 5: /* (Rm >>> Rs) */
   1.122 +            return snprintf(buf, len, "R%d >>> R%d", RM(ir), RS(ir) );
   1.123 +        case 6:
   1.124 +            tmp = SHIFTIMM(ir);
   1.125 +            if( tmp == 0 ) /* RRX aka rotate with carry */
   1.126 +                return snprintf(buf, len, "R%d roc 1", RM(ir) );
   1.127 +            else
   1.128 +                return snprintf(buf, len, "R%d rot %d", RM(ir), SHIFTIMM(ir) );
   1.129 +        case 7:
   1.130 +            return snprintf(buf, len, "R%d rot R%d", RM(ir), RS(ir) );
   1.131 +        }
   1.132 +    } else {
   1.133 +        operand = IMM8(ir);
   1.134 +        tmp = IMMROT(ir);
   1.135 +        operand = ROTATE_RIGHT_LONG(operand, tmp);
   1.136 +        return snprintf(buf, len, "#%08Xh", operand );
   1.137 +    }
   1.138 +    return 0;
   1.139  }
   1.140  
   1.141  static int arm_disasm_address_index( uint32_t ir, char *buf, int len )
   1.142  {
   1.143 -	uint32_t tmp;
   1.144 -	
   1.145 -	switch(SHIFT(ir)) {
   1.146 -	case 0: /* (Rm << imm) */
   1.147 -	    tmp = SHIFTIMM(ir);
   1.148 -	    if( tmp != 0 ) {
   1.149 -		return snprintf( buf, len, "R%d << %d", RM(ir), tmp );
   1.150 -	    } else {
   1.151 -		return snprintf( buf, len, "R%d", RM(ir) );
   1.152 -	    }
   1.153 -	case 2: /* (Rm >> imm) */
   1.154 -		return snprintf( buf, len, "R%d >> %d", RM(ir), SHIFTIMM(ir) );
   1.155 -	case 4: /* (Rm >>> imm) */
   1.156 -		return snprintf( buf, len, "R%d >>> %d", RM(ir), SHIFTIMM(ir) );
   1.157 -	case 6:
   1.158 -		tmp = SHIFTIMM(ir);
   1.159 -		if( tmp == 0 ) /* RRX aka rotate with carry */
   1.160 -			return snprintf( buf, len, "R%d roc 1", RM(ir) );
   1.161 -		else
   1.162 -			return snprintf( buf, len, "R%d rot %d", RM(ir), tmp );
   1.163 -	default: 
   1.164 -		return UNIMP(ir);
   1.165 -	}
   1.166 +    uint32_t tmp;
   1.167 +
   1.168 +    switch(SHIFT(ir)) {
   1.169 +    case 0: /* (Rm << imm) */
   1.170 +        tmp = SHIFTIMM(ir);
   1.171 +        if( tmp != 0 ) {
   1.172 +            return snprintf( buf, len, "R%d << %d", RM(ir), tmp );
   1.173 +        } else {
   1.174 +            return snprintf( buf, len, "R%d", RM(ir) );
   1.175 +        }
   1.176 +    case 2: /* (Rm >> imm) */
   1.177 +        return snprintf( buf, len, "R%d >> %d", RM(ir), SHIFTIMM(ir) );
   1.178 +    case 4: /* (Rm >>> imm) */
   1.179 +        return snprintf( buf, len, "R%d >>> %d", RM(ir), SHIFTIMM(ir) );
   1.180 +    case 6:
   1.181 +        tmp = SHIFTIMM(ir);
   1.182 +        if( tmp == 0 ) /* RRX aka rotate with carry */
   1.183 +            return snprintf( buf, len, "R%d roc 1", RM(ir) );
   1.184 +        else
   1.185 +            return snprintf( buf, len, "R%d rot %d", RM(ir), tmp );
   1.186 +    default: 
   1.187 +        return UNIMP(ir);
   1.188 +    }
   1.189  }
   1.190  
   1.191  static int arm_disasm_address_operand( uint32_t ir, char *buf, int len,  int pc )
   1.192  {
   1.193      char  shift[32];
   1.194  
   1.195 -	char sign = UFLAG(ir) ? '+' : '-';
   1.196 -	/* I P U . W */
   1.197 -	switch( (ir>>21)&0x19 ) {
   1.198 -	case 0: /* Rn -= imm offset (post-indexed) [5.2.8 A5-28] */
   1.199 -	case 1:
   1.200 -		return snprintf( buf, len, "[R%d], R%d %c= #%04Xh", RN(ir), RN(ir), sign, IMM12(ir) );
   1.201 -	case 8: /* Rn - imm offset  [5.2.2 A5-20] */
   1.202 -	    if( RN(ir) == 15 ) { /* PC relative - decode here */
   1.203 -		uint32_t addr = pc + 8 + (UFLAG(ir) ? IMM12(ir) : -IMM12(ir));
   1.204 -		return snprintf( buf, len, "[$%08Xh] <- #%08Xh", addr,
   1.205 -				 arm_read_long( addr ) );
   1.206 -	    } else {
   1.207 -		return snprintf( buf, len, "[R%d %c #%04Xh]", RN(ir), sign, IMM12(ir) );
   1.208 -	    }
   1.209 -	case 9: /* Rn -= imm offset (pre-indexed)  [5.2.5 A5-24] */
   1.210 -		return snprintf( buf, len, "[R%d %c= #%04Xh]", RN(ir), sign, IMM12(ir) );
   1.211 -	case 16: /* Rn -= Rm (post-indexed)  [5.2.10 A5-32 ] */
   1.212 -	case 17:
   1.213 -		arm_disasm_address_index( ir, shift, sizeof(shift) );
   1.214 -		return snprintf( buf, len, "[R%d], R%d %c= %s", RN(ir), RN(ir), sign, shift );
   1.215 -	case 24: /* Rn - Rm  [5.2.4 A5-23] */
   1.216 -		arm_disasm_address_index( ir, shift, sizeof(shift) );
   1.217 -		return snprintf( buf, len, "[R%d %c %s]", RN(ir), sign, shift );
   1.218 -	case 25: /* RN -= Rm (pre-indexed)  [5.2.7 A5-26] */
   1.219 -		arm_disasm_address_index( ir, shift, sizeof(shift) );
   1.220 -		return snprintf( buf, len, "[R%d %c= %s]", RN(ir), sign, shift );
   1.221 -	default:
   1.222 -		return UNIMP(ir); /* Unreachable */
   1.223 -	}
   1.224 +    char sign = UFLAG(ir) ? '+' : '-';
   1.225 +    /* I P U . W */
   1.226 +    switch( (ir>>21)&0x19 ) {
   1.227 +    case 0: /* Rn -= imm offset (post-indexed) [5.2.8 A5-28] */
   1.228 +    case 1:
   1.229 +        return snprintf( buf, len, "[R%d], R%d %c= #%04Xh", RN(ir), RN(ir), sign, IMM12(ir) );
   1.230 +    case 8: /* Rn - imm offset  [5.2.2 A5-20] */
   1.231 +        if( RN(ir) == 15 ) { /* PC relative - decode here */
   1.232 +            uint32_t addr = pc + 8 + (UFLAG(ir) ? IMM12(ir) : -IMM12(ir));
   1.233 +            return snprintf( buf, len, "[$%08Xh] <- #%08Xh", addr,
   1.234 +                    arm_read_long( addr ) );
   1.235 +        } else {
   1.236 +            return snprintf( buf, len, "[R%d %c #%04Xh]", RN(ir), sign, IMM12(ir) );
   1.237 +        }
   1.238 +    case 9: /* Rn -= imm offset (pre-indexed)  [5.2.5 A5-24] */
   1.239 +        return snprintf( buf, len, "[R%d %c= #%04Xh]", RN(ir), sign, IMM12(ir) );
   1.240 +    case 16: /* Rn -= Rm (post-indexed)  [5.2.10 A5-32 ] */
   1.241 +    case 17:
   1.242 +        arm_disasm_address_index( ir, shift, sizeof(shift) );
   1.243 +        return snprintf( buf, len, "[R%d], R%d %c= %s", RN(ir), RN(ir), sign, shift );
   1.244 +    case 24: /* Rn - Rm  [5.2.4 A5-23] */
   1.245 +        arm_disasm_address_index( ir, shift, sizeof(shift) );
   1.246 +        return snprintf( buf, len, "[R%d %c %s]", RN(ir), sign, shift );
   1.247 +    case 25: /* RN -= Rm (pre-indexed)  [5.2.7 A5-26] */
   1.248 +        arm_disasm_address_index( ir, shift, sizeof(shift) );
   1.249 +        return snprintf( buf, len, "[R%d %c= %s]", RN(ir), sign, shift );
   1.250 +    default:
   1.251 +        return UNIMP(ir); /* Unreachable */
   1.252 +    }
   1.253  }
   1.254  
   1.255  uint32_t arm_disasm_instruction( uint32_t pc, char *buf, int len, char *opcode )
   1.256 @@ -191,320 +191,320 @@
   1.257      char operand[64];
   1.258      uint32_t ir = arm_read_long(pc);
   1.259      int i,j;
   1.260 -	
   1.261 +
   1.262      sprintf( opcode, "%02X %02X %02X %02X", ir&0xFF, (ir>>8) & 0xFF,
   1.263 -	     (ir>>16)&0xFF, (ir>>24) );
   1.264 +             (ir>>16)&0xFF, (ir>>24) );
   1.265  
   1.266      if( COND(ir) == 0x0F ) {
   1.267 -    	UNIMP(ir);
   1.268 -    	return pc+4;
   1.269 +        UNIMP(ir);
   1.270 +        return pc+4;
   1.271      }
   1.272      char *cond = conditionNames[COND(ir)];
   1.273  
   1.274 -	switch( GRP(ir) ) {
   1.275 -	case 0:
   1.276 -		if( (ir & 0x0D900000) == 0x01000000 ) {
   1.277 -			/* Instructions that aren't actual data processing */
   1.278 -			switch( ir & 0x0FF000F0 ) {
   1.279 -			case 0x01200010: /* BXcc */
   1.280 -				snprintf(buf, len, "BX%s     R%d", cond, RM(ir));
   1.281 -				break;
   1.282 -			case 0x01000000: /* MRS Rd, CPSR */
   1.283 -				snprintf(buf, len, "MRS%s    R%d, CPSR", cond, RD(ir));
   1.284 -				break;
   1.285 -			case 0x01400000: /* MRS Rd, SPSR */
   1.286 -				snprintf(buf, len, "MRS%s    R%d, SPSR", cond, RD(ir));
   1.287 -				break;
   1.288 -			case 0x01200000: /* MSR CPSR, Rm */
   1.289 -				snprintf(buf, len, "MSR%s    CPSR_%s, R%d", cond, FSXC(ir), RM(ir));
   1.290 -				break;
   1.291 -			case 0x01600000: /* MSR SPSR, Rm */
   1.292 -				snprintf(buf, len, "MSR%s    SPSR_%s, R%d", cond, FSXC(ir), RM(ir));
   1.293 -				break;
   1.294 -			case 0x03200000: /* MSR CPSR, imm */
   1.295 -				snprintf(buf, len, "MSR%s    CPSR_%s, #%08X", cond, FSXC(ir), ROTIMM12(ir));
   1.296 -				break;
   1.297 -			case 0x03600000: /* MSR SPSR, imm */
   1.298 -				snprintf(buf, len, "MSR%s    SPSR_%s, #%08X", cond, FSXC(ir), ROTIMM12(ir));
   1.299 -				break;
   1.300 -			default:
   1.301 -				UNIMP();
   1.302 -			}
   1.303 -		} else if( (ir & 0x0E000090) == 0x00000090 ) {
   1.304 -			/* Neither are these */
   1.305 -			switch( (ir>>5)&0x03 ) {
   1.306 -			case 0:
   1.307 -				/* Arithmetic extension area */
   1.308 -				switch(OPCODE(ir)) {
   1.309 -				case 0: /* MUL */
   1.310 -					snprintf(buf,len, "MUL%s    R%d, R%d, R%d", cond, RN(ir), RM(ir), RS(ir) );
   1.311 -					break;
   1.312 -				case 1: /* MULS */
   1.313 -					break;
   1.314 -				case 2: /* MLA */
   1.315 -					snprintf(buf,len, "MLA%s    R%d, R%d, R%d, R%d", cond, RN(ir), RM(ir), RS(ir), RD(ir) );
   1.316 -					break;
   1.317 -				case 3: /* MLAS */
   1.318 -					break;
   1.319 -				case 8: /* UMULL */
   1.320 -					snprintf(buf,len, "UMULL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
   1.321 -					break;
   1.322 -				case 9: /* UMULLS */
   1.323 -					break;
   1.324 -				case 10: /* UMLAL */
   1.325 -					snprintf(buf,len, "UMLAL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
   1.326 -					break;
   1.327 -				case 11: /* UMLALS */
   1.328 -					break;
   1.329 -				case 12: /* SMULL */
   1.330 -					snprintf(buf,len, "SMULL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
   1.331 -					break;
   1.332 -				case 13: /* SMULLS */
   1.333 -					break;
   1.334 -				case 14: /* SMLAL */
   1.335 -					snprintf(buf,len, "SMLAL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
   1.336 -					break;
   1.337 -				case 15: /* SMLALS */
   1.338 +    switch( GRP(ir) ) {
   1.339 +    case 0:
   1.340 +        if( (ir & 0x0D900000) == 0x01000000 ) {
   1.341 +            /* Instructions that aren't actual data processing */
   1.342 +            switch( ir & 0x0FF000F0 ) {
   1.343 +            case 0x01200010: /* BXcc */
   1.344 +                snprintf(buf, len, "BX%s     R%d", cond, RM(ir));
   1.345 +                break;
   1.346 +            case 0x01000000: /* MRS Rd, CPSR */
   1.347 +                snprintf(buf, len, "MRS%s    R%d, CPSR", cond, RD(ir));
   1.348 +                break;
   1.349 +            case 0x01400000: /* MRS Rd, SPSR */
   1.350 +                snprintf(buf, len, "MRS%s    R%d, SPSR", cond, RD(ir));
   1.351 +                break;
   1.352 +            case 0x01200000: /* MSR CPSR, Rm */
   1.353 +                snprintf(buf, len, "MSR%s    CPSR_%s, R%d", cond, FSXC(ir), RM(ir));
   1.354 +                break;
   1.355 +            case 0x01600000: /* MSR SPSR, Rm */
   1.356 +                snprintf(buf, len, "MSR%s    SPSR_%s, R%d", cond, FSXC(ir), RM(ir));
   1.357 +                break;
   1.358 +            case 0x03200000: /* MSR CPSR, imm */
   1.359 +                snprintf(buf, len, "MSR%s    CPSR_%s, #%08X", cond, FSXC(ir), ROTIMM12(ir));
   1.360 +                break;
   1.361 +            case 0x03600000: /* MSR SPSR, imm */
   1.362 +                snprintf(buf, len, "MSR%s    SPSR_%s, #%08X", cond, FSXC(ir), ROTIMM12(ir));
   1.363 +                break;
   1.364 +            default:
   1.365 +                UNIMP();
   1.366 +            }
   1.367 +        } else if( (ir & 0x0E000090) == 0x00000090 ) {
   1.368 +            /* Neither are these */
   1.369 +            switch( (ir>>5)&0x03 ) {
   1.370 +            case 0:
   1.371 +                /* Arithmetic extension area */
   1.372 +                switch(OPCODE(ir)) {
   1.373 +                case 0: /* MUL */
   1.374 +                    snprintf(buf,len, "MUL%s    R%d, R%d, R%d", cond, RN(ir), RM(ir), RS(ir) );
   1.375 +                    break;
   1.376 +                case 1: /* MULS */
   1.377 +                    break;
   1.378 +                case 2: /* MLA */
   1.379 +                    snprintf(buf,len, "MLA%s    R%d, R%d, R%d, R%d", cond, RN(ir), RM(ir), RS(ir), RD(ir) );
   1.380 +                    break;
   1.381 +                case 3: /* MLAS */
   1.382 +                    break;
   1.383 +                case 8: /* UMULL */
   1.384 +                    snprintf(buf,len, "UMULL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
   1.385 +                    break;
   1.386 +                case 9: /* UMULLS */
   1.387 +                    break;
   1.388 +                case 10: /* UMLAL */
   1.389 +                    snprintf(buf,len, "UMLAL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
   1.390 +                    break;
   1.391 +                case 11: /* UMLALS */
   1.392 +                    break;
   1.393 +                case 12: /* SMULL */
   1.394 +                    snprintf(buf,len, "SMULL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
   1.395 +                    break;
   1.396 +                case 13: /* SMULLS */
   1.397 +                    break;
   1.398 +                case 14: /* SMLAL */
   1.399 +                    snprintf(buf,len, "SMLAL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
   1.400 +                    break;
   1.401 +                case 15: /* SMLALS */
   1.402  
   1.403 -					break;
   1.404 -				case 16: /* SWP */
   1.405 -					snprintf(buf,len, "SWP%s    R%d, R%d, [R%d]", cond, RD(ir), RN(ir), RM(ir) );
   1.406 -					break;
   1.407 -				case 20: /* SWPB */
   1.408 -					snprintf(buf,len, "SWPB%s   R%d, R%d, [R%d]", cond, RD(ir), RN(ir), RM(ir) );
   1.409 -					break;
   1.410 -				default:
   1.411 -					UNIMP(ir);
   1.412 -				}
   1.413 -				break;
   1.414 -			case 1:
   1.415 -				if( LFLAG(ir) ) {
   1.416 -					/* LDRH */
   1.417 -				} else {
   1.418 -					/* STRH */
   1.419 -				}
   1.420 -				UNIMP(ir);
   1.421 -				break;
   1.422 -			case 2:
   1.423 -				if( LFLAG(ir) ) {
   1.424 -					/* LDRSB */
   1.425 -				} else {
   1.426 -				}
   1.427 -				UNIMP(ir);
   1.428 -				break;
   1.429 -			case 3:
   1.430 -				if( LFLAG(ir) ) {
   1.431 -					/* LDRSH */
   1.432 -				} else {
   1.433 -				}
   1.434 -				UNIMP(ir);
   1.435 -				break;
   1.436 -			}
   1.437 -		} else {
   1.438 -			/* Data processing */
   1.439 +                    break;
   1.440 +                case 16: /* SWP */
   1.441 +                    snprintf(buf,len, "SWP%s    R%d, R%d, [R%d]", cond, RD(ir), RN(ir), RM(ir) );
   1.442 +                    break;
   1.443 +                case 20: /* SWPB */
   1.444 +                    snprintf(buf,len, "SWPB%s   R%d, R%d, [R%d]", cond, RD(ir), RN(ir), RM(ir) );
   1.445 +                    break;
   1.446 +                default:
   1.447 +                    UNIMP(ir);
   1.448 +                }
   1.449 +                break;
   1.450 +                case 1:
   1.451 +                    if( LFLAG(ir) ) {
   1.452 +                        /* LDRH */
   1.453 +                    } else {
   1.454 +                        /* STRH */
   1.455 +                    }
   1.456 +                    UNIMP(ir);
   1.457 +                    break;
   1.458 +                case 2:
   1.459 +                    if( LFLAG(ir) ) {
   1.460 +                        /* LDRSB */
   1.461 +                    } else {
   1.462 +                    }
   1.463 +                    UNIMP(ir);
   1.464 +                    break;
   1.465 +                case 3:
   1.466 +                    if( LFLAG(ir) ) {
   1.467 +                        /* LDRSH */
   1.468 +                    } else {
   1.469 +                    }
   1.470 +                    UNIMP(ir);
   1.471 +                    break;
   1.472 +            }
   1.473 +        } else {
   1.474 +            /* Data processing */
   1.475  
   1.476 -			switch(OPCODE(ir)) {
   1.477 -			case 0: /* AND Rd, Rn, operand */
   1.478 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.479 -				snprintf(buf, len, "AND%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.480 -				break;
   1.481 -			case 1: /* ANDS Rd, Rn, operand */
   1.482 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.483 -				snprintf(buf, len, "ANDS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.484 -				break;
   1.485 -			case 2: /* EOR Rd, Rn, operand */
   1.486 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.487 -				snprintf(buf, len, "EOR%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.488 -				break;
   1.489 -			case 3: /* EORS Rd, Rn, operand */
   1.490 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.491 -				snprintf(buf, len, "EORS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.492 -				break;
   1.493 -			case 4: /* SUB Rd, Rn, operand */
   1.494 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.495 -				snprintf(buf, len, "SUB%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.496 -				break;
   1.497 -			case 5: /* SUBS Rd, Rn, operand */
   1.498 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.499 -				snprintf(buf, len, "SUBS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.500 -				break;
   1.501 -			case 6: /* RSB Rd, Rn, operand */
   1.502 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.503 -				snprintf(buf, len, "RSB%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.504 -				break;
   1.505 -			case 7: /* RSBS Rd, Rn, operand */
   1.506 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.507 -				snprintf(buf, len, "RSBS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.508 -				break;
   1.509 -			case 8: /* ADD Rd, Rn, operand */
   1.510 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.511 -				snprintf(buf, len, "ADD%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.512 -				break;
   1.513 -			case 9: /* ADDS Rd, Rn, operand */
   1.514 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.515 -				snprintf(buf, len, "ADDS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.516 -				break;
   1.517 -			case 10: /* ADC Rd, Rn, operand */
   1.518 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.519 -				snprintf(buf, len, "ADC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.520 -				break;
   1.521 -			case 11: /* ADCS Rd, Rn, operand */
   1.522 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.523 -				snprintf(buf, len, "ADCS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.524 -				break;
   1.525 -			case 12: /* SBC Rd, Rn, operand */
   1.526 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.527 -				snprintf(buf, len, "SBC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.528 -				break;
   1.529 -			case 13: /* SBCS Rd, Rn, operand */
   1.530 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.531 -				snprintf(buf, len, "SBCS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.532 -				break;
   1.533 -			case 14: /* RSC Rd, Rn, operand */
   1.534 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.535 -				snprintf(buf, len, "RSC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.536 -				break;
   1.537 -			case 15: /* RSCS Rd, Rn, operand */
   1.538 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.539 -				snprintf(buf, len, "RSCS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.540 -				break;
   1.541 -			case 17: /* TST Rd, Rn, operand */
   1.542 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.543 -				snprintf(buf, len, "TST%s    R%d, %s", cond, RN(ir), operand);
   1.544 -				break;
   1.545 -			case 19: /* TEQ Rd, Rn, operand */
   1.546 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.547 -				snprintf(buf, len, "TEQ%s    R%d, %s", cond, RN(ir), operand);
   1.548 -				break;
   1.549 -			case 21: /* CMP Rd, Rn, operand */
   1.550 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.551 -				snprintf(buf, len, "CMP%s    R%d, %s", cond, RN(ir), operand);
   1.552 -				break;
   1.553 -			case 23: /* CMN Rd, Rn, operand */
   1.554 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.555 -				snprintf(buf, len, "CMN%s    R%d, %s", cond, RN(ir), operand);
   1.556 -				break;
   1.557 -			case 24: /* ORR Rd, Rn, operand */
   1.558 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.559 -				snprintf(buf, len, "ORR%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.560 -				break;
   1.561 -			case 25: /* ORRS Rd, Rn, operand */
   1.562 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.563 -				snprintf(buf, len, "ORRS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.564 -				break;
   1.565 -			case 26: /* MOV Rd, operand */
   1.566 -			    if( ir == 0xE1A00000 ) {
   1.567 -				/* Not technically a different instruction,
   1.568 -				 * but this one is commonly used as a NOP,
   1.569 -				 * so... 
   1.570 -				 */
   1.571 -				snprintf(buf, len, "NOP");
   1.572 -			    } else {
   1.573 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.574 -				snprintf(buf, len, "MOV%s    R%d, %s", cond, RD(ir), operand);
   1.575 -			    }
   1.576 -			    break;
   1.577 -			case 27: /* MOVS Rd, operand */
   1.578 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.579 -				snprintf(buf, len, "MOVS%s   R%d, %s", cond, RD(ir), operand);
   1.580 -				break;
   1.581 -			case 28: /* BIC Rd, Rn, operand */
   1.582 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.583 -				snprintf(buf, len, "BIC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.584 -				break;
   1.585 -			case 29: /* BICS Rd, Rn, operand */
   1.586 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.587 -				snprintf(buf, len, "BICS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.588 -				break;
   1.589 -			case 30: /* MVN Rd, Rn, operand */
   1.590 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.591 -				snprintf(buf, len, "MVN%s    R%d, %s", cond, RD(ir), operand);
   1.592 -				break;
   1.593 -			case 31: /* MVNS Rd, Rn, operand */
   1.594 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.595 -				snprintf(buf, len, "MVNS%s   R%d, %s", cond, RD(ir), operand);
   1.596 -				break;
   1.597 -			default:
   1.598 -				UNIMP(ir);
   1.599 -			}
   1.600 -		}
   1.601 -		break;
   1.602 -	case 1: /* Load/store */
   1.603 -	    arm_disasm_address_operand( ir, operand, sizeof(operand), pc );
   1.604 -		switch( (ir>>20)&0x17 ) {
   1.605 -			case 0:
   1.606 -			case 16:
   1.607 -			case 18:
   1.608 -				snprintf(buf, len, "STR%s    R%d, %s", cond, RD(ir), operand );
   1.609 -				break;
   1.610 -			case 1:
   1.611 -			case 17:
   1.612 -			case 19:
   1.613 -				snprintf(buf, len, "LDR%s    R%d, %s", cond, RD(ir), operand );
   1.614 -				break;
   1.615 -			case 2:
   1.616 -				snprintf(buf, len, "STRT%s   R%d, %s", cond, RD(ir), operand );
   1.617 -				break;
   1.618 -			case 3:
   1.619 -				snprintf(buf, len, "LDRT%s   R%d, %s", cond, RD(ir), operand );
   1.620 -				break;
   1.621 -			case 4:
   1.622 -			case 20:
   1.623 -			case 22:
   1.624 -				snprintf(buf, len, "STRB%s   R%d, %s", cond, RD(ir), operand );
   1.625 -				break;
   1.626 -			case 5:
   1.627 -			case 21:
   1.628 -			case 23:
   1.629 -				snprintf(buf, len, "LDRB%s   R%d, %s", cond, RD(ir), operand );
   1.630 -				break;
   1.631 -			case 6:
   1.632 -				snprintf(buf, len, "STRBT%s  R%d, %s", cond, RD(ir), operand );
   1.633 -				break;
   1.634 -			case 7: 
   1.635 -				snprintf(buf, len, "LDRBT%s  R%d, %s", cond, RD(ir), operand );
   1.636 -				break;
   1.637 -		}
   1.638 -		break;
   1.639 -	case 2: 
   1.640 -	    if( (ir & 0x02000000) == 0x02000000 ) {
   1.641 -		int32_t offset = SIGNEXT24(ir&0x00FFFFFF) << 2;
   1.642 -		if( (ir & 0x01000000) == 0x01000000 ) { 
   1.643 -		    snprintf( buf, len, "BL%s     $%08Xh", cond, pc + offset + 8 );
   1.644 -		} else {
   1.645 -		    snprintf( buf, len, "B%s      $%08Xh", cond, pc + offset + 8 );
   1.646 -		}
   1.647 -	    } else {
   1.648 -		/* Load/store multiple */
   1.649 -		j = snprintf( buf, len, LFLAG(ir) ? "LDM%s%s  R%d%c,":"STM%s%s  R%d%c,", 
   1.650 -			      ldmModes[(ir>>23)&0x03], cond, RN(ir), WFLAG(ir)?'!':' ' );
   1.651 -		buf += j;
   1.652 -		len -= j;
   1.653 -		for( i = 0; i<16 && len > 2; i++ ) {
   1.654 -		    if( ir & (1<<i) ) {
   1.655 -			j = snprintf( buf, len, "R%d", i );
   1.656 -			buf+=j;
   1.657 -			len-=j;
   1.658 -		    }
   1.659 -		}
   1.660 -		if( BFLAG(ir) && len > 0 ) {
   1.661 -			buf[0] = '^';
   1.662 -			buf[1] = '\0';
   1.663 -		}
   1.664 -	    }
   1.665 -	    break;
   1.666 -	case 3: /* Copro */
   1.667 -	    if( (ir & 0x0F000000) == 0x0F000000 ) {
   1.668 -		snprintf( buf, len, "SWI%s    #%08Xh", cond, SIGNEXT24(ir) );
   1.669 -	    } else {
   1.670 -		UNIMP(ir);
   1.671 -	    }
   1.672 -	    break;
   1.673 -	}
   1.674 -	
   1.675 -	
   1.676 -	
   1.677 -	return pc+4;
   1.678 +            switch(OPCODE(ir)) {
   1.679 +            case 0: /* AND Rd, Rn, operand */
   1.680 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.681 +                snprintf(buf, len, "AND%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.682 +                break;
   1.683 +            case 1: /* ANDS Rd, Rn, operand */
   1.684 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.685 +                snprintf(buf, len, "ANDS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.686 +                break;
   1.687 +            case 2: /* EOR Rd, Rn, operand */
   1.688 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.689 +                snprintf(buf, len, "EOR%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.690 +                break;
   1.691 +            case 3: /* EORS Rd, Rn, operand */
   1.692 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.693 +                snprintf(buf, len, "EORS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.694 +                break;
   1.695 +            case 4: /* SUB Rd, Rn, operand */
   1.696 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.697 +                snprintf(buf, len, "SUB%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.698 +                break;
   1.699 +            case 5: /* SUBS Rd, Rn, operand */
   1.700 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.701 +                snprintf(buf, len, "SUBS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.702 +                break;
   1.703 +            case 6: /* RSB Rd, Rn, operand */
   1.704 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.705 +                snprintf(buf, len, "RSB%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.706 +                break;
   1.707 +            case 7: /* RSBS Rd, Rn, operand */
   1.708 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.709 +                snprintf(buf, len, "RSBS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.710 +                break;
   1.711 +            case 8: /* ADD Rd, Rn, operand */
   1.712 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.713 +                snprintf(buf, len, "ADD%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.714 +                break;
   1.715 +            case 9: /* ADDS Rd, Rn, operand */
   1.716 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.717 +                snprintf(buf, len, "ADDS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.718 +                break;
   1.719 +            case 10: /* ADC Rd, Rn, operand */
   1.720 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.721 +                snprintf(buf, len, "ADC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.722 +                break;
   1.723 +            case 11: /* ADCS Rd, Rn, operand */
   1.724 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.725 +                snprintf(buf, len, "ADCS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.726 +                break;
   1.727 +            case 12: /* SBC Rd, Rn, operand */
   1.728 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.729 +                snprintf(buf, len, "SBC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.730 +                break;
   1.731 +            case 13: /* SBCS Rd, Rn, operand */
   1.732 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.733 +                snprintf(buf, len, "SBCS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.734 +                break;
   1.735 +            case 14: /* RSC Rd, Rn, operand */
   1.736 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.737 +                snprintf(buf, len, "RSC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.738 +                break;
   1.739 +            case 15: /* RSCS Rd, Rn, operand */
   1.740 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.741 +                snprintf(buf, len, "RSCS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.742 +                break;
   1.743 +            case 17: /* TST Rd, Rn, operand */
   1.744 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.745 +                snprintf(buf, len, "TST%s    R%d, %s", cond, RN(ir), operand);
   1.746 +                break;
   1.747 +            case 19: /* TEQ Rd, Rn, operand */
   1.748 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.749 +                snprintf(buf, len, "TEQ%s    R%d, %s", cond, RN(ir), operand);
   1.750 +                break;
   1.751 +            case 21: /* CMP Rd, Rn, operand */
   1.752 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.753 +                snprintf(buf, len, "CMP%s    R%d, %s", cond, RN(ir), operand);
   1.754 +                break;
   1.755 +            case 23: /* CMN Rd, Rn, operand */
   1.756 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.757 +                snprintf(buf, len, "CMN%s    R%d, %s", cond, RN(ir), operand);
   1.758 +                break;
   1.759 +            case 24: /* ORR Rd, Rn, operand */
   1.760 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.761 +                snprintf(buf, len, "ORR%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.762 +                break;
   1.763 +            case 25: /* ORRS Rd, Rn, operand */
   1.764 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.765 +                snprintf(buf, len, "ORRS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.766 +                break;
   1.767 +            case 26: /* MOV Rd, operand */
   1.768 +                if( ir == 0xE1A00000 ) {
   1.769 +                    /* Not technically a different instruction,
   1.770 +                     * but this one is commonly used as a NOP,
   1.771 +                     * so... 
   1.772 +                     */
   1.773 +                    snprintf(buf, len, "NOP");
   1.774 +                } else {
   1.775 +                    arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.776 +                    snprintf(buf, len, "MOV%s    R%d, %s", cond, RD(ir), operand);
   1.777 +                }
   1.778 +                break;
   1.779 +            case 27: /* MOVS Rd, operand */
   1.780 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.781 +                snprintf(buf, len, "MOVS%s   R%d, %s", cond, RD(ir), operand);
   1.782 +                break;
   1.783 +            case 28: /* BIC Rd, Rn, operand */
   1.784 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.785 +                snprintf(buf, len, "BIC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.786 +                break;
   1.787 +            case 29: /* BICS Rd, Rn, operand */
   1.788 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.789 +                snprintf(buf, len, "BICS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   1.790 +                break;
   1.791 +            case 30: /* MVN Rd, Rn, operand */
   1.792 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.793 +                snprintf(buf, len, "MVN%s    R%d, %s", cond, RD(ir), operand);
   1.794 +                break;
   1.795 +            case 31: /* MVNS Rd, Rn, operand */
   1.796 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   1.797 +                snprintf(buf, len, "MVNS%s   R%d, %s", cond, RD(ir), operand);
   1.798 +                break;
   1.799 +            default:
   1.800 +                UNIMP(ir);
   1.801 +            }
   1.802 +        }
   1.803 +        break;
   1.804 +    case 1: /* Load/store */
   1.805 +        arm_disasm_address_operand( ir, operand, sizeof(operand), pc );
   1.806 +        switch( (ir>>20)&0x17 ) {
   1.807 +        case 0:
   1.808 +        case 16:
   1.809 +        case 18:
   1.810 +            snprintf(buf, len, "STR%s    R%d, %s", cond, RD(ir), operand );
   1.811 +            break;
   1.812 +        case 1:
   1.813 +        case 17:
   1.814 +        case 19:
   1.815 +            snprintf(buf, len, "LDR%s    R%d, %s", cond, RD(ir), operand );
   1.816 +            break;
   1.817 +        case 2:
   1.818 +            snprintf(buf, len, "STRT%s   R%d, %s", cond, RD(ir), operand );
   1.819 +            break;
   1.820 +        case 3:
   1.821 +            snprintf(buf, len, "LDRT%s   R%d, %s", cond, RD(ir), operand );
   1.822 +            break;
   1.823 +        case 4:
   1.824 +        case 20:
   1.825 +        case 22:
   1.826 +            snprintf(buf, len, "STRB%s   R%d, %s", cond, RD(ir), operand );
   1.827 +            break;
   1.828 +        case 5:
   1.829 +        case 21:
   1.830 +        case 23:
   1.831 +            snprintf(buf, len, "LDRB%s   R%d, %s", cond, RD(ir), operand );
   1.832 +            break;
   1.833 +        case 6:
   1.834 +            snprintf(buf, len, "STRBT%s  R%d, %s", cond, RD(ir), operand );
   1.835 +            break;
   1.836 +        case 7: 
   1.837 +            snprintf(buf, len, "LDRBT%s  R%d, %s", cond, RD(ir), operand );
   1.838 +            break;
   1.839 +        }
   1.840 +        break;
   1.841 +        case 2: 
   1.842 +            if( (ir & 0x02000000) == 0x02000000 ) {
   1.843 +                int32_t offset = SIGNEXT24(ir&0x00FFFFFF) << 2;
   1.844 +                if( (ir & 0x01000000) == 0x01000000 ) { 
   1.845 +                    snprintf( buf, len, "BL%s     $%08Xh", cond, pc + offset + 8 );
   1.846 +                } else {
   1.847 +                    snprintf( buf, len, "B%s      $%08Xh", cond, pc + offset + 8 );
   1.848 +                }
   1.849 +            } else {
   1.850 +                /* Load/store multiple */
   1.851 +                j = snprintf( buf, len, LFLAG(ir) ? "LDM%s%s  R%d%c,":"STM%s%s  R%d%c,", 
   1.852 +                        ldmModes[(ir>>23)&0x03], cond, RN(ir), WFLAG(ir)?'!':' ' );
   1.853 +                buf += j;
   1.854 +                len -= j;
   1.855 +                for( i = 0; i<16 && len > 2; i++ ) {
   1.856 +                    if( ir & (1<<i) ) {
   1.857 +                        j = snprintf( buf, len, "R%d", i );
   1.858 +                        buf+=j;
   1.859 +                        len-=j;
   1.860 +                    }
   1.861 +                }
   1.862 +                if( BFLAG(ir) && len > 0 ) {
   1.863 +                    buf[0] = '^';
   1.864 +                    buf[1] = '\0';
   1.865 +                }
   1.866 +            }
   1.867 +            break;
   1.868 +        case 3: /* Copro */
   1.869 +            if( (ir & 0x0F000000) == 0x0F000000 ) {
   1.870 +                snprintf( buf, len, "SWI%s    #%08Xh", cond, SIGNEXT24(ir) );
   1.871 +            } else {
   1.872 +                UNIMP(ir);
   1.873 +            }
   1.874 +            break;
   1.875 +    }
   1.876 +
   1.877 +
   1.878 +
   1.879 +    return pc+4;
   1.880  }
   1.881  
   1.882