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lxdream.org :: lxdream/src/sh4/sh4core.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.c
changeset 229:f27eb26ccdd2
prev227:1b98af7fc601
next232:9c8ef78376ed
author nkeynes
date Mon Sep 25 11:19:42 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Fix SPC assignment for exceptions (the only one it was _correct_ for was
TRAPA)
file annotate diff log raw
1.1 --- a/src/sh4/sh4core.c Sat Sep 23 11:38:41 2006 +0000
1.2 +++ b/src/sh4/sh4core.c Mon Sep 25 11:19:42 2006 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: sh4core.c,v 1.31 2006-09-23 11:38:41 nkeynes Exp $
1.6 + * $Id: sh4core.c,v 1.32 2006-09-25 11:19:42 nkeynes Exp $
1.7 *
1.8 * SH4 emulation core, and parent module for all the SH4 peripheral
1.9 * modules.
1.10 @@ -254,12 +254,12 @@
1.11 #define TRACE_RETURN( source, dest )
1.12 #endif
1.13
1.14 -#define RAISE( x, v ) do{ \
1.15 +#define RAISE( x, v, pcadj ) do{ \
1.16 if( sh4r.vbr == 0 ) { \
1.17 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
1.18 dreamcast_stop(); return FALSE; \
1.19 } else { \
1.20 - sh4r.spc = sh4r.pc + 2; \
1.21 + sh4r.spc = sh4r.pc + pcadj; \
1.22 sh4r.ssr = sh4_read_sr(); \
1.23 sh4r.sgr = sh4r.r[15]; \
1.24 MMIO_WRITE(MMU,EXPEVT,x); \
1.25 @@ -269,6 +269,7 @@
1.26 } \
1.27 return TRUE; } while(0)
1.28
1.29 +
1.30 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
1.31 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
1.32 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
1.33 @@ -282,16 +283,16 @@
1.34
1.35 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
1.36
1.37 -#define CHECK( x, c, v ) if( !x ) RAISE( c, v )
1.38 +#define CHECK( x, c, v ) if( !x ) RAISE( c, v, 0 )
1.39 #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
1.40 -#define CHECKRALIGN16(addr) if( (addr)&0x01 ) RAISE( EXC_READ_ADDR_ERR, EXV_TRAP )
1.41 -#define CHECKRALIGN32(addr) if( (addr)&0x03 ) RAISE( EXC_READ_ADDR_ERR, EXV_TRAP )
1.42 -#define CHECKWALIGN16(addr) if( (addr)&0x01 ) RAISE( EXC_WRITE_ADDR_ERR, EXV_TRAP )
1.43 -#define CHECKWALIGN32(addr) if( (addr)&0x03 ) RAISE( EXC_WRITE_ADDR_ERR, EXV_TRAP )
1.44 +#define CHECKRALIGN16(addr) if( (addr)&0x01 ) RAISE( EXC_READ_ADDR_ERR, EXV_TRAP, 0 )
1.45 +#define CHECKRALIGN32(addr) if( (addr)&0x03 ) RAISE( EXC_READ_ADDR_ERR, EXV_TRAP, 0 )
1.46 +#define CHECKWALIGN16(addr) if( (addr)&0x01 ) RAISE( EXC_WRITE_ADDR_ERR, EXV_TRAP, 0 )
1.47 +#define CHECKWALIGN32(addr) if( (addr)&0x03 ) RAISE( EXC_WRITE_ADDR_ERR, EXV_TRAP, 0 )
1.48
1.49 #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
1.50 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
1.51 -#define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }
1.52 +#define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL, -2); }
1.53
1.54 static void sh4_switch_banks( )
1.55 {
1.56 @@ -357,7 +358,7 @@
1.57 /* function for external use */
1.58 void sh4_raise_exception( int code, int vector )
1.59 {
1.60 - RAISE(code, vector);
1.61 + RAISE(code, vector, 0);
1.62 }
1.63
1.64 static void sh4_accept_interrupt( void )
1.65 @@ -1265,7 +1266,7 @@
1.66 CHECKSLOTILLEGAL()
1.67 sh4r.in_delay_slot = 1;
1.68 MMIO_WRITE( MMU, TRA, UIMM8(ir)<<2 );
1.69 - RAISE( EXC_TRAP, EXV_TRAP );
1.70 + RAISE( EXC_TRAP, EXV_TRAP, 2 );
1.71 break;
1.72 case 4: /* MOV.B [GBR + disp8], R0 */
1.73 R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
.