1.1 --- a/src/pvr2/pvr2.c	Thu Dec 11 21:33:08 2008 +0000
     1.2 +++ b/src/pvr2/pvr2.c	Tue Jan 13 11:56:28 2009 +0000
     1.3 @@ -31,8 +31,6 @@
     1.4  #define MMIO_IMPL
     1.5  #include "pvr2/pvr2mmio.h"
     1.6  
     1.7 -unsigned char *video_base;
     1.8 -
     1.9  #define MAX_RENDER_BUFFERS 4
    1.10  
    1.11  #define HPOS_PER_FRAME 0
    1.12 @@ -142,12 +140,10 @@
    1.13      int i;
    1.14      register_io_region( &mmio_region_PVR2 );
    1.15      register_io_region( &mmio_region_PVR2PAL );
    1.16 -    register_io_region( &mmio_region_PVR2TA );
    1.17      register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
    1.18      register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
    1.19      register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
    1.20      register_event_callback( EVENT_GUNPOS, pvr2_gunpos_callback );
    1.21 -    video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
    1.22      texcache_init();
    1.23      pvr2_reset();
    1.24      pvr2_ta_reset();
    1.25 @@ -445,7 +441,7 @@
    1.26          }
    1.27          fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
    1.28          fbuf.inverted = FALSE;
    1.29 -        fbuf.data = video_base + (fbuf.address&0x00FFFFFF);
    1.30 +        fbuf.data = pvr2_main_ram + (fbuf.address&0x00FFFFFF);
    1.31  
    1.32          render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
    1.33          if( rbuf == NULL ) {
    1.34 @@ -462,8 +458,9 @@
    1.35   * This has to handle every single register individually as they all get masked 
    1.36   * off differently (and its easier to do it at write time)
    1.37   */
    1.38 -void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
    1.39 +MMIO_REGION_WRITE_FN( PVR2, reg, val )
    1.40  {
    1.41 +    reg &= 0xFFF;
    1.42      if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
    1.43          MMIO_WRITE( PVR2, reg, val );
    1.44          return;
    1.45 @@ -826,6 +823,7 @@
    1.46  
    1.47  MMIO_REGION_READ_FN( PVR2, reg )
    1.48  {
    1.49 +    reg &= 0xFFF;
    1.50      switch( reg ) {
    1.51      case DISP_SYNCSTAT:
    1.52          return pvr2_get_sync_status();
    1.53 @@ -836,6 +834,7 @@
    1.54  
    1.55  MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
    1.56  {
    1.57 +    reg &= 0xFFF;
    1.58      MMIO_WRITE( PVR2PAL, reg, val );
    1.59      pvr2_state.palette_changed = TRUE;
    1.60  }
    1.61 @@ -855,19 +854,6 @@
    1.62      mmio_region_PVR2_write( DISP_ADDR1, base );
    1.63  }
    1.64  
    1.65 -
    1.66 -
    1.67 -
    1.68 -int32_t mmio_region_PVR2TA_read( uint32_t reg )
    1.69 -{
    1.70 -    return 0xFFFFFFFF;
    1.71 -}
    1.72 -
    1.73 -void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
    1.74 -{
    1.75 -    pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );
    1.76 -}
    1.77 -
    1.78  render_buffer_t pvr2_create_render_buffer( sh4addr_t addr, int width, int height, GLuint tex_id )
    1.79  {
    1.80      if( display_driver != NULL && display_driver->create_render_buffer != NULL ) {