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lxdream.org :: lxdream/src/pvr2/pvr2.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 197:f65ff8c8320d
prev193:31151fcc3cb7
next214:7a6501b74fbc
author nkeynes
date Sun Aug 06 02:47:08 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Add masks on all PVR2 registers
Add missing registers and rename display registers for consistency
file annotate diff log raw
1.1 --- a/src/pvr2/pvr2.c Fri Aug 04 01:38:30 2006 +0000
1.2 +++ b/src/pvr2/pvr2.c Sun Aug 06 02:47:08 2006 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: pvr2.c,v 1.30 2006-08-04 01:38:27 nkeynes Exp $
1.6 + * $Id: pvr2.c,v 1.31 2006-08-06 02:47:08 nkeynes Exp $
1.7 *
1.8 * PVR2 (Video) Core module implementation and MMIO registers.
1.9 *
1.10 @@ -148,11 +148,11 @@
1.11 */
1.12 void pvr2_display_frame( void )
1.13 {
1.14 - uint32_t display_addr = MMIO_READ( PVR2, DISPADDR1 );
1.15 + uint32_t display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
1.16
1.17 - int dispsize = MMIO_READ( PVR2, DISPSIZE );
1.18 - int dispmode = MMIO_READ( PVR2, DISPMODE );
1.19 - int vidcfg = MMIO_READ( PVR2, DISPCFG );
1.20 + int dispsize = MMIO_READ( PVR2, DISP_SIZE );
1.21 + int dispmode = MMIO_READ( PVR2, DISP_MODE );
1.22 + int vidcfg = MMIO_READ( PVR2, DISP_CFG );
1.23 int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
1.24 int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
1.25 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
1.26 @@ -162,7 +162,7 @@
1.27 video_buffer_idx = !video_buffer_idx;
1.28 video_buffer_t last = &video_buffer[video_buffer_idx];
1.29 buffer->rowstride = (vid_ppl + vid_stride) << 2;
1.30 - buffer->data = video_base + MMIO_READ( PVR2, DISPADDR1 );
1.31 + buffer->data = video_base + MMIO_READ( PVR2, DISP_ADDR1 );
1.32 buffer->vres = vid_lpf;
1.33 if( interlaced ) buffer->vres <<= 1;
1.34 switch( (dispmode & DISPMODE_COL) >> 2 ) {
1.35 @@ -197,8 +197,8 @@
1.36 }
1.37 if( !bEnabled ) {
1.38 display_driver->display_blank_frame( 0 );
1.39 - } else if( MMIO_READ( PVR2, DISPCFG2 ) & 0x08 ) { /* Blanked */
1.40 - uint32_t colour = MMIO_READ( PVR2, DISPBORDER );
1.41 + } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { /* Blanked */
1.42 + uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
1.43 display_driver->display_blank_frame( colour );
1.44 } else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
1.45 display_driver->display_frame( buffer );
1.46 @@ -207,11 +207,14 @@
1.47 pvr2_state.frame_count++;
1.48 }
1.49
1.50 +/**
1.51 + * This has to handle every single register individually as they all get masked
1.52 + * off differently (and its easier to do it at write time)
1.53 + */
1.54 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
1.55 {
1.56 if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
1.57 MMIO_WRITE( PVR2, reg, val );
1.58 - /* I don't want to hear about these */
1.59 return;
1.60 }
1.61
1.62 @@ -223,6 +226,10 @@
1.63 case TA_LISTPOS:
1.64 /* Readonly registers */
1.65 break;
1.66 + case PVRRESET:
1.67 + val &= 0x00000007; /* Do stuff? */
1.68 + MMIO_WRITE( PVR2, reg, val );
1.69 + break;
1.70 case RENDER_START:
1.71 if( val == 0xFFFFFFFF )
1.72 pvr2_render_scene();
1.73 @@ -236,10 +243,10 @@
1.74 case RENDER_TSPCFG:
1.75 MMIO_WRITE( PVR2, reg, val&0x00010101 );
1.76 break;
1.77 - case DISPBORDER:
1.78 + case DISP_BORDER:
1.79 MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
1.80 break;
1.81 - case DISPMODE:
1.82 + case DISP_MODE:
1.83 MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
1.84 break;
1.85 case RENDER_MODE:
1.86 @@ -248,7 +255,7 @@
1.87 case RENDER_SIZE:
1.88 MMIO_WRITE( PVR2, reg, val&0x000001FF );
1.89 break;
1.90 - case DISPADDR1:
1.91 + case DISP_ADDR1:
1.92 val &= 0x00FFFFFC;
1.93 MMIO_WRITE( PVR2, reg, val );
1.94 if( pvr2_state.retrace ) {
1.95 @@ -256,10 +263,10 @@
1.96 pvr2_state.retrace = FALSE;
1.97 }
1.98 break;
1.99 - case DISPADDR2:
1.100 + case DISP_ADDR2:
1.101 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
1.102 break;
1.103 - case DISPSIZE:
1.104 + case DISP_SIZE:
1.105 MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
1.106 break;
1.107 case RENDER_ADDR1:
1.108 @@ -272,30 +279,97 @@
1.109 case RENDER_VCLIP:
1.110 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
1.111 break;
1.112 - case HPOS_IRQ:
1.113 + case DISP_HPOSIRQ:
1.114 MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
1.115 break;
1.116 - case VPOS_IRQ:
1.117 + case DISP_VPOSIRQ:
1.118 val = val & 0x03FF03FF;
1.119 pvr2_state.irq_vpos1 = (val >> 16);
1.120 pvr2_state.irq_vpos2 = val & 0x03FF;
1.121 MMIO_WRITE( PVR2, reg, val );
1.122 break;
1.123 + case RENDER_NEARCLIP:
1.124 + MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
1.125 + break;
1.126 case RENDER_SHADOW:
1.127 MMIO_WRITE( PVR2, reg, val&0x000001FF );
1.128 break;
1.129 case RENDER_OBJCFG:
1.130 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
1.131 break;
1.132 + case PVRUNK2:
1.133 + MMIO_WRITE( PVR2, reg, val&0x00000007 );
1.134 + break;
1.135 case RENDER_TSPCLIP:
1.136 MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
1.137 break;
1.138 + case RENDER_FARCLIP:
1.139 + MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
1.140 + break;
1.141 case RENDER_BGPLANE:
1.142 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
1.143 break;
1.144 case RENDER_ISPCFG:
1.145 MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
1.146 break;
1.147 + case VRAM_CFG1:
1.148 + MMIO_WRITE( PVR2, reg, val&0x000000FF );
1.149 + break;
1.150 + case VRAM_CFG2:
1.151 + MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
1.152 + break;
1.153 + case VRAM_CFG3:
1.154 + MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
1.155 + break;
1.156 + case RENDER_FOGTBLCOL:
1.157 + case RENDER_FOGVRTCOL:
1.158 + MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
1.159 + break;
1.160 + case RENDER_FOGCOEFF:
1.161 + MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
1.162 + break;
1.163 + case RENDER_CLAMPHI:
1.164 + case RENDER_CLAMPLO:
1.165 + MMIO_WRITE( PVR2, reg, val );
1.166 + break;
1.167 + case DISP_CFG:
1.168 + MMIO_WRITE( PVR2, reg, val&0x000003FF );
1.169 + break;
1.170 + case DISP_HBORDER:
1.171 + case DISP_SYNC:
1.172 + case DISP_VBORDER:
1.173 + MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
1.174 + break;
1.175 + case DISP_SYNC2:
1.176 + MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
1.177 + break;
1.178 + case RENDER_TEXSIZE:
1.179 + MMIO_WRITE( PVR2, reg, val&0x00031F1F );
1.180 + break;
1.181 + case DISP_CFG2:
1.182 + MMIO_WRITE( PVR2, reg, val&0x003F01FF );
1.183 + break;
1.184 + case DISP_HPOS:
1.185 + MMIO_WRITE( PVR2, reg, val&0x000003FF );
1.186 + break;
1.187 + case DISP_VPOS:
1.188 + MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
1.189 + break;
1.190 + case SCALERCFG:
1.191 + MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
1.192 + break;
1.193 + case RENDER_PALETTE:
1.194 + MMIO_WRITE( PVR2, reg, val&0x00000003 );
1.195 + break;
1.196 + case PVRUNK3:
1.197 + MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
1.198 + break;
1.199 + case PVRUNK5:
1.200 + MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
1.201 + break;
1.202 + case PVRUNK6:
1.203 + MMIO_WRITE( PVR2, reg, val&0x000000FF );
1.204 + break;
1.205 case TA_TILEBASE:
1.206 case TA_LISTEND:
1.207 case TA_LISTBASE:
1.208 @@ -312,26 +386,28 @@
1.209 case TA_TILECFG:
1.210 MMIO_WRITE( PVR2, reg, val&0x00133333 );
1.211 break;
1.212 + case YUV_ADDR:
1.213 + MMIO_WRITE( PVR2, reg, val&0x00FFFFF8 );
1.214 + break;
1.215 + case YUV_CFG:
1.216 + MMIO_WRITE( PVR2, reg, val&0x01013F3F );
1.217 + break;
1.218 case TA_INIT:
1.219 if( val & 0x80000000 )
1.220 pvr2_ta_init();
1.221 break;
1.222 -
1.223 - /* Nonexistent registers (as far as we know, anyway) */
1.224 - case 0x01C:
1.225 - case 0x024:
1.226 - case 0x028:
1.227 - case 0x058:
1.228 - break;
1.229 - default:
1.230 - MMIO_WRITE( PVR2, reg, val );
1.231 + case TA_REINIT:
1.232 + break;
1.233 + case PVRUNK7:
1.234 + MMIO_WRITE( PVR2, reg, val&0x00000001 );
1.235 + break;
1.236 }
1.237 }
1.238
1.239 MMIO_REGION_READ_FN( PVR2, reg )
1.240 {
1.241 switch( reg ) {
1.242 - case BEAMPOS:
1.243 + case DISP_BEAMPOS:
1.244 return sh4r.icount&0x20 ? 0x2000 : 1;
1.245 default:
1.246 return MMIO_READ( PVR2, reg );
1.247 @@ -342,7 +418,7 @@
1.248
1.249 void pvr2_set_base_address( uint32_t base )
1.250 {
1.251 - mmio_region_PVR2_write( DISPADDR1, base );
1.252 + mmio_region_PVR2_write( DISP_ADDR1, base );
1.253 }
1.254
1.255
.