1.1 --- a/src/sh4/sh4core.in	Tue Sep 18 09:14:20 2007 +0000
     1.2 +++ b/src/sh4/sh4core.in	Thu Sep 20 08:37:19 2007 +0000
     1.3 @@ -1,5 +1,5 @@
     1.4  /**
     1.5 - * $Id: sh4core.in,v 1.7 2007-09-18 09:14:20 nkeynes Exp $
     1.6 + * $Id: sh4core.in,v 1.8 2007-09-20 08:37:19 nkeynes Exp $
     1.7   * 
     1.8   * SH4 emulation core, and parent module for all the SH4 peripheral
     1.9   * modules.
    1.10 @@ -34,14 +34,8 @@
    1.11  #define MAX_INTF 2147483647.0
    1.12  #define MIN_INTF -2147483648.0
    1.13  
    1.14 -#define EXV_EXCEPTION    0x100  /* General exception vector */
    1.15 -#define EXV_TLBMISS      0x400  /* TLB-miss exception vector */
    1.16 -#define EXV_INTERRUPT    0x600  /* External interrupt vector */
    1.17 -
    1.18  /********************** SH4 Module Definition ****************************/
    1.19  
    1.20 -uint32_t sh4_run_slice( uint32_t );
    1.21 -
    1.22  uint16_t *sh4_icache = NULL;
    1.23  uint32_t sh4_icache_addr = 0;
    1.24  
    1.25 @@ -68,7 +62,6 @@
    1.26  		    sh4_accept_interrupt();
    1.27  		}
    1.28  	    }
    1.29 -	    //	    sh4_stats_add( sh4r.pc );
    1.30  	    if( !sh4_execute_instruction() ) {
    1.31  		break;
    1.32  	    }
    1.33 @@ -119,12 +112,6 @@
    1.34  
    1.35  /********************** SH4 emulation core  ****************************/
    1.36  
    1.37 -void sh4_set_pc( int pc )
    1.38 -{
    1.39 -    sh4r.pc = pc;
    1.40 -    sh4r.new_pc = pc+2;
    1.41 -}
    1.42 -
    1.43  #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
    1.44  #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
    1.45  
    1.46 @@ -175,25 +162,6 @@
    1.47  #define TRACE_RETURN( source, dest )
    1.48  #endif
    1.49  
    1.50 -#define RAISE( x, v ) do{			\
    1.51 -    if( sh4r.vbr == 0 ) { \
    1.52 -        ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
    1.53 -        dreamcast_stop(); return FALSE;	\
    1.54 -    } else { \
    1.55 -        sh4r.spc = sh4r.pc;	\
    1.56 -        sh4r.ssr = sh4_read_sr(); \
    1.57 -        sh4r.sgr = sh4r.r[15]; \
    1.58 -        MMIO_WRITE(MMU,EXPEVT,x); \
    1.59 -        sh4r.pc = sh4r.vbr + v; \
    1.60 -        sh4r.new_pc = sh4r.pc + 2; \
    1.61 -        sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
    1.62 -	if( sh4r.in_delay_slot ) { \
    1.63 -	    sh4r.in_delay_slot = 0; \
    1.64 -	    sh4r.spc -= 2; \
    1.65 -	} \
    1.66 -    } \
    1.67 -    return TRUE; } while(0)
    1.68 -
    1.69  #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
    1.70  #define MEM_READ_WORD( addr ) sh4_read_word(addr)
    1.71  #define MEM_READ_LONG( addr ) sh4_read_long(addr)
    1.72 @@ -216,27 +184,6 @@
    1.73  #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
    1.74  #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
    1.75  
    1.76 -static void sh4_switch_banks( )
    1.77 -{
    1.78 -    uint32_t tmp[8];
    1.79 -
    1.80 -    memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
    1.81 -    memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
    1.82 -    memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
    1.83 -}
    1.84 -
    1.85 -void sh4_write_sr( uint32_t newval )
    1.86 -{
    1.87 -    if( (newval ^ sh4r.sr) & SR_RB )
    1.88 -        sh4_switch_banks();
    1.89 -    sh4r.sr = newval;
    1.90 -    sh4r.t = (newval&SR_T) ? 1 : 0;
    1.91 -    sh4r.s = (newval&SR_S) ? 1 : 0;
    1.92 -    sh4r.m = (newval&SR_M) ? 1 : 0;
    1.93 -    sh4r.q = (newval&SR_Q) ? 1 : 0;
    1.94 -    intc_mask_changed();
    1.95 -}
    1.96 -
    1.97  static void sh4_write_float( uint32_t addr, int reg )
    1.98  {
    1.99      if( IS_FPU_DOUBLESIZE() ) {
   1.100 @@ -267,58 +214,6 @@
   1.101      }
   1.102  }
   1.103  
   1.104 -uint32_t sh4_read_sr( void )
   1.105 -{
   1.106 -    /* synchronize sh4r.sr with the various bitflags */
   1.107 -    sh4r.sr &= SR_MQSTMASK;
   1.108 -    if( sh4r.t ) sh4r.sr |= SR_T;
   1.109 -    if( sh4r.s ) sh4r.sr |= SR_S;
   1.110 -    if( sh4r.m ) sh4r.sr |= SR_M;
   1.111 -    if( sh4r.q ) sh4r.sr |= SR_Q;
   1.112 -    return sh4r.sr;
   1.113 -}
   1.114 -
   1.115 -/**
   1.116 - * Raise a general CPU exception for the specified exception code.
   1.117 - * (NOT for TRAPA or TLB exceptions)
   1.118 - */
   1.119 -gboolean sh4_raise_exception( int code )
   1.120 -{
   1.121 -    RAISE( code, EXV_EXCEPTION );
   1.122 -}
   1.123 -
   1.124 -gboolean sh4_raise_trap( int trap )
   1.125 -{
   1.126 -    MMIO_WRITE( MMU, TRA, trap<<2 );
   1.127 -    return sh4_raise_exception( EXC_TRAP );
   1.128 -}
   1.129 -
   1.130 -gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
   1.131 -    if( sh4r.in_delay_slot ) {
   1.132 -	return sh4_raise_exception(slot_code);
   1.133 -    } else {
   1.134 -	return sh4_raise_exception(normal_code);
   1.135 -    }
   1.136 -}
   1.137 -
   1.138 -gboolean sh4_raise_tlb_exception( int code )
   1.139 -{
   1.140 -    RAISE( code, EXV_TLBMISS );
   1.141 -}
   1.142 -
   1.143 -void sh4_accept_interrupt( void )
   1.144 -{
   1.145 -    uint32_t code = intc_accept_interrupt();
   1.146 -    sh4r.ssr = sh4_read_sr();
   1.147 -    sh4r.spc = sh4r.pc;
   1.148 -    sh4r.sgr = sh4r.r[15];
   1.149 -    sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   1.150 -    MMIO_WRITE( MMU, INTEVT, code );
   1.151 -    sh4r.pc = sh4r.vbr + 0x600;
   1.152 -    sh4r.new_pc = sh4r.pc + 2;
   1.153 -    //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   1.154 -}
   1.155 -
   1.156  gboolean sh4_execute_instruction( void )
   1.157  {
   1.158      uint32_t pc;