1.1 --- a/src/sh4/sh4x86.in Tue Sep 11 21:23:48 2007 +0000
1.2 +++ b/src/sh4/sh4x86.in Wed Sep 12 09:17:52 2007 +0000
1.5 - * $Id: sh4x86.in,v 1.5 2007-09-11 21:23:48 nkeynes Exp $
1.6 + * $Id: sh4x86.in,v 1.6 2007-09-12 09:17:24 nkeynes Exp $
1.8 * SH4 => x86 translation. This version does no real optimization, it just
1.9 * outputs straight-line x86 code - it mainly exists to provide a baseline
1.10 @@ -180,6 +180,22 @@
1.14 + * Push FPUL (as a 32-bit float) onto the FPU stack
1.16 +static inline void push_fpul( )
1.18 + OP(0xD9); OP(0x45); OP(R_FPUL);
1.22 + * Pop FPUL (as a 32-bit float) from the FPU stack
1.24 +static inline void pop_fpul( )
1.26 + OP(0xD9); OP(0x5D); OP(R_FPUL);
1.30 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
1.31 * with the location of the current fp bank.
1.37 - ADD_imm8s_r32( -4, R_ESP );
1.38 + ADD_imm8s_r32( 4, R_ESP );
1.41 static inline void call_func2( void *ptr, int arg1, int arg2 )
1.46 - ADD_imm8s_r32( -8, R_ESP );
1.47 + ADD_imm8s_r32( 8, R_ESP );
1.54 call_func0(sh4_write_long);
1.55 - ADD_imm8s_r32( -8, R_ESP );
1.56 + ADD_imm8s_r32( 8, R_ESP );
1.57 call_func0(sh4_write_long);
1.58 - ADD_imm8s_r32( -8, R_ESP );
1.59 + ADD_imm8s_r32( 8, R_ESP );
1.64 ADD_imm8s_r32( 4, addr );
1.66 call_func0(sh4_read_long);
1.67 - ADD_imm8s_r32( -4, R_ESP );
1.68 + ADD_imm8s_r32( 4, R_ESP );
1.69 MOV_r32_r32( R_EAX, arg2b );
1.72 @@ -1235,6 +1251,8 @@
1.73 load_spreg( R_EAX, R_SSR );
1.74 call_func1( sh4_write_sr, R_EAX );
1.75 sh4_x86.in_delay_slot = TRUE;
1.76 + sh4_x86.priv_checked = FALSE;
1.77 + sh4_x86.fpuen_checked = FALSE;
1.81 @@ -1297,8 +1315,9 @@
1.82 * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
1.83 * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
1.86 load_spreg( R_ECX, R_FPSCR );
1.87 - load_spreg( R_EDX, REG_OFFSET(fr_bank) );
1.88 + load_fr_bank( R_EDX );
1.89 TEST_imm32_r32( FPSCR_SZ, R_ECX );
1.91 load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
1.92 @@ -1334,12 +1353,13 @@
1.97 load_reg( R_EDX, Rn );
1.98 check_walign32( R_EDX );
1.99 load_spreg( R_ECX, R_FPSCR );
1.100 TEST_imm32_r32( FPSCR_SZ, R_ECX );
1.102 - load_spreg( R_ECX, REG_OFFSET(fr_bank) );
1.103 + load_fr_bank( R_ECX );
1.104 load_fr( R_ECX, R_EAX, FRm );
1.105 MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
1.107 @@ -1347,20 +1367,21 @@
1.108 load_xf_bank( R_ECX );
1.111 - load_spreg( R_ECX, REG_OFFSET(fr_bank) );
1.112 + load_fr_bank( R_ECX );
1.114 load_fr( R_ECX, R_EAX, FRm&0x0E );
1.115 load_fr( R_ECX, R_ECX, FRm|0x01 );
1.116 MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
1.120 load_reg( R_EDX, Rm );
1.121 check_ralign32( R_EDX );
1.122 load_spreg( R_ECX, R_FPSCR );
1.123 TEST_imm32_r32( FPSCR_SZ, R_ECX );
1.125 MEM_READ_LONG( R_EDX, R_EAX );
1.126 - load_spreg( R_ECX, REG_OFFSET(fr_bank) );
1.127 + load_fr_bank( R_ECX );
1.128 store_fr( R_ECX, R_EAX, FRn );
1.131 @@ -1370,20 +1391,183 @@
1.134 MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
1.135 - load_spreg( R_ECX, REG_OFFSET(fr_bank) );
1.136 + load_fr_bank( R_ECX );
1.138 store_fr( R_ECX, R_EAX, FRn&0x0E );
1.139 store_fr( R_ECX, R_EDX, FRn|0x01 );
1.141 -FMOV FRm, @-Rn {: :}
1.142 -FMOV FRm, @(R0, Rn) {: :}
1.143 -FMOV @Rm+, FRn {: :}
1.144 -FMOV @(R0, Rm), FRn {: :}
1.147 + load_reg( R_EDX, Rn );
1.148 + check_walign32( R_EDX );
1.149 + load_spreg( R_ECX, R_FPSCR );
1.150 + TEST_imm32_r32( FPSCR_SZ, R_ECX );
1.152 + load_fr_bank( R_ECX );
1.153 + load_fr( R_ECX, R_EAX, FRm );
1.154 + ADD_imm8s_r32(-4,R_EDX);
1.155 + store_reg( R_EDX, Rn );
1.156 + MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
1.159 + load_xf_bank( R_ECX );
1.162 + load_fr_bank( R_ECX );
1.164 + load_fr( R_ECX, R_EAX, FRm&0x0E );
1.165 + load_fr( R_ECX, R_ECX, FRm|0x01 );
1.166 + ADD_imm8s_r32(-8,R_EDX);
1.167 + store_reg( R_EDX, Rn );
1.168 + MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
1.172 + load_reg( R_EDX, Rm );
1.173 + check_ralign32( R_EDX );
1.174 + MOV_r32_r32( R_EDX, R_EAX );
1.175 + load_spreg( R_ECX, R_FPSCR );
1.176 + TEST_imm32_r32( FPSCR_SZ, R_ECX );
1.178 + ADD_imm8s_r32( 4, R_EAX );
1.179 + store_reg( R_EAX, Rm );
1.180 + MEM_READ_LONG( R_EDX, R_EAX );
1.181 + load_fr_bank( R_ECX );
1.182 + store_fr( R_ECX, R_EAX, FRn );
1.185 + ADD_imm8s_r32( 8, R_EAX );
1.186 + store_reg(R_EAX, Rm);
1.187 + MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
1.188 + load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
1.189 + load_xf_bank( R_ECX );
1.192 + ADD_imm8s_r32( 8, R_EAX );
1.193 + store_reg(R_EAX, Rm);
1.194 + MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
1.195 + load_fr_bank( R_ECX );
1.197 + store_fr( R_ECX, R_EAX, FRn&0x0E );
1.198 + store_fr( R_ECX, R_EDX, FRn|0x01 );
1.200 +FMOV FRm, @(R0, Rn) {:
1.202 + load_reg( R_EDX, Rn );
1.203 + ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
1.204 + check_walign32( R_EDX );
1.205 + load_spreg( R_ECX, R_FPSCR );
1.206 + TEST_imm32_r32( FPSCR_SZ, R_ECX );
1.208 + load_fr_bank( R_ECX );
1.209 + load_fr( R_ECX, R_EAX, FRm );
1.210 + MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
1.213 + load_xf_bank( R_ECX );
1.216 + load_fr_bank( R_ECX );
1.218 + load_fr( R_ECX, R_EAX, FRm&0x0E );
1.219 + load_fr( R_ECX, R_ECX, FRm|0x01 );
1.220 + MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
1.222 +FMOV @(R0, Rm), FRn {:
1.224 + load_reg( R_EDX, Rm );
1.225 + ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
1.226 + check_ralign32( R_EDX );
1.227 + load_spreg( R_ECX, R_FPSCR );
1.228 + TEST_imm32_r32( FPSCR_SZ, R_ECX );
1.230 + MEM_READ_LONG( R_EDX, R_EAX );
1.231 + load_fr_bank( R_ECX );
1.232 + store_fr( R_ECX, R_EAX, FRn );
1.235 + MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
1.236 + load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
1.237 + load_xf_bank( R_ECX );
1.240 + MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
1.241 + load_fr_bank( R_ECX );
1.243 + store_fr( R_ECX, R_EAX, FRn&0x0E );
1.244 + store_fr( R_ECX, R_EDX, FRn|0x01 );
1.246 +FLDI0 FRn {: /* IFF PR=0 */
1.248 + load_spreg( R_ECX, R_FPSCR );
1.249 + TEST_imm32_r32( FPSCR_PR, R_ECX );
1.251 + XOR_r32_r32( R_EAX, R_EAX );
1.252 + load_spreg( R_ECX, REG_OFFSET(fr_bank) );
1.253 + store_fr( R_ECX, R_EAX, FRn );
1.255 +FLDI1 FRn {: /* IFF PR=0 */
1.257 + load_spreg( R_ECX, R_FPSCR );
1.258 + TEST_imm32_r32( FPSCR_PR, R_ECX );
1.260 + load_imm32(R_EAX, 0x3F800000);
1.261 + load_spreg( R_ECX, REG_OFFSET(fr_bank) );
1.262 + store_fr( R_ECX, R_EAX, FRn );
1.265 +FLOAT FPUL, FRn {:
1.267 + load_spreg( R_ECX, R_FPSCR );
1.268 + load_spreg(R_EDX, REG_OFFSET(fr_bank));
1.269 + FILD_sh4r(R_FPUL);
1.270 + TEST_imm32_r32( FPSCR_PR, R_ECX );
1.272 + pop_fr( R_EDX, FRn );
1.274 + pop_dr( R_EDX, FRn );
1.282 + load_fr_bank( R_ECX );
1.283 + load_fr( R_ECX, R_EAX, FRm );
1.284 + store_spreg( R_EAX, R_FPUL );
1.288 + load_fr_bank( R_ECX );
1.289 + load_spreg( R_EAX, R_FPUL );
1.290 + store_fr( R_ECX, R_EAX, FRn );
1.292 +FCNVDS FRm, FPUL {:
1.294 + load_spreg( R_ECX, R_FPSCR );
1.295 + TEST_imm32_r32( FPSCR_PR, R_ECX );
1.296 + JE_rel8(9); // only when PR=1
1.297 + load_fr_bank( R_ECX );
1.298 + push_dr( R_ECX, FRm );
1.301 +FCNVSD FPUL, FRn {:
1.304 + load_spreg( R_ECX, R_FPSCR );
1.305 + TEST_imm32_r32( FPSCR_PR, R_ECX );
1.306 + JE_rel8(9); // only when PR=1
1.307 + load_fr_bank( R_ECX );
1.309 + pop_dr( R_ECX, FRn );
1.312 /* Floating point instructions */
1.315 load_spreg( R_ECX, R_FPSCR );
1.316 - load_spreg( R_EDX, REG_OFFSET(fr_bank) );
1.317 + load_fr_bank( R_EDX );
1.318 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.320 push_fr(R_EDX, FRn); // 3
1.321 @@ -1394,41 +1578,40 @@
1.323 pop_dr(R_EDX, FRn);
1.325 -FADD FRm, FRn {: :}
1.326 -FCMP/EQ FRm, FRn {: :}
1.327 -FCMP/GT FRm, FRn {: :}
1.328 -FCNVDS FRm, FPUL {: :}
1.329 -FCNVSD FPUL, FRn {: :}
1.330 -FDIV FRm, FRn {: :}
1.331 -FIPR FVm, FVn {: :}
1.332 -FLDS FRm, FPUL {: :}
1.333 -FLDI0 FRn {: /* IFF PR=0 */
1.336 load_spreg( R_ECX, R_FPSCR );
1.337 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.339 - xor_r32_r32( R_EAX, R_EAX );
1.340 - load_spreg( R_ECX, REG_OFFSET(fr_bank) );
1.341 - store_fr( R_ECX, R_EAX, FRn );
1.342 + load_fr_bank( R_EDX );
1.344 + push_fr(R_EDX, FRm);
1.345 + push_fr(R_EDX, FRn);
1.347 + pop_fr(R_EDX, FRn);
1.349 + push_dr(R_EDX, FRm);
1.350 + push_dr(R_EDX, FRn);
1.352 + pop_dr(R_EDX, FRn);
1.354 -FLDI1 FRn {: /* IFF PR=0 */
1.357 load_spreg( R_ECX, R_FPSCR );
1.358 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.360 - load_imm32(R_EAX, 0x3F800000);
1.361 - load_spreg( R_ECX, REG_OFFSET(fr_bank) );
1.362 - store_fr( R_ECX, R_EAX, FRn );
1.364 -FLOAT FPUL, FRn {:
1.365 - load_spreg( R_ECX, R_FPSCR );
1.366 - load_spreg(R_EDX, REG_OFFSET(fr_bank));
1.367 - FILD_sh4r(R_FPUL);
1.368 - TEST_imm32_r32( FPSCR_PR, R_ECX );
1.370 - pop_fr( R_EDX, FRn );
1.372 - pop_dr( R_EDX, FRn );
1.373 + load_fr_bank( R_EDX );
1.375 + push_fr(R_EDX, FRn);
1.376 + push_fr(R_EDX, FRm);
1.378 + pop_fr(R_EDX, FRn);
1.380 + push_dr(R_EDX, FRn);
1.381 + push_dr(R_EDX, FRm);
1.383 + pop_dr(R_EDX, FRn);
1.385 FMAC FR0, FRm, FRn {:
1.387 load_spreg( R_ECX, R_FPSCR );
1.388 load_spreg( R_EDX, REG_OFFSET(fr_bank));
1.389 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.390 @@ -1448,22 +1631,140 @@
1.391 pop_dr( R_EDX, FRn );
1.394 -FMUL FRm, FRn {: :}
1.397 -FSCA FPUL, FRn {: :}
1.401 -FSTS FPUL, FRn {: :}
1.402 -FSUB FRm, FRn {: :}
1.403 -FTRC FRm, FPUL {: :}
1.404 -FTRV XMTRX, FVn {: :}
1.407 + load_spreg( R_ECX, R_FPSCR );
1.408 + TEST_imm32_r32( FPSCR_PR, R_ECX );
1.409 + load_fr_bank( R_EDX );
1.411 + push_fr(R_EDX, FRm);
1.412 + push_fr(R_EDX, FRn);
1.414 + pop_fr(R_EDX, FRn);
1.416 + push_dr(R_EDX, FRm);
1.417 + push_dr(R_EDX, FRn);
1.419 + pop_dr(R_EDX, FRn);
1.423 + load_spreg( R_ECX, R_FPSCR );
1.424 + TEST_imm32_r32( FPSCR_PR, R_ECX );
1.425 + load_fr_bank( R_EDX );
1.427 + push_fr(R_EDX, FRn);
1.429 + pop_fr(R_EDX, FRn);
1.431 + push_dr(R_EDX, FRn);
1.433 + pop_dr(R_EDX, FRn);
1.437 + load_spreg( R_ECX, R_FPSCR );
1.438 + TEST_imm32_r32( FPSCR_PR, R_ECX );
1.439 + load_fr_bank( R_EDX );
1.440 + JNE_rel8(12); // PR=0 only
1.442 + push_fr(R_EDX, FRn);
1.445 + pop_fr(R_EDX, FRn);
1.449 + load_spreg( R_ECX, R_FPSCR );
1.450 + TEST_imm32_r32( FPSCR_PR, R_ECX );
1.451 + load_fr_bank( R_EDX );
1.453 + push_fr(R_EDX, FRn);
1.455 + pop_fr(R_EDX, FRn);
1.457 + push_dr(R_EDX, FRn);
1.459 + pop_dr(R_EDX, FRn);
1.463 + load_spreg( R_ECX, R_FPSCR );
1.464 + TEST_imm32_r32( FPSCR_PR, R_ECX );
1.465 + load_fr_bank( R_EDX );
1.467 + push_fr(R_EDX, FRn);
1.468 + push_fr(R_EDX, FRm);
1.470 + pop_fr(R_EDX, FRn);
1.472 + push_dr(R_EDX, FRn);
1.473 + push_dr(R_EDX, FRm);
1.475 + pop_dr(R_EDX, FRn);
1.478 +FCMP/EQ FRm, FRn {:
1.480 + load_spreg( R_ECX, R_FPSCR );
1.481 + TEST_imm32_r32( FPSCR_PR, R_ECX );
1.482 + load_fr_bank( R_EDX );
1.484 + push_fr(R_EDX, FRm);
1.485 + push_fr(R_EDX, FRn);
1.487 + push_dr(R_EDX, FRm);
1.488 + push_dr(R_EDX, FRn);
1.493 +FCMP/GT FRm, FRn {:
1.495 + load_spreg( R_ECX, R_FPSCR );
1.496 + TEST_imm32_r32( FPSCR_PR, R_ECX );
1.497 + load_fr_bank( R_EDX );
1.499 + push_fr(R_EDX, FRm);
1.500 + push_fr(R_EDX, FRn);
1.502 + push_dr(R_EDX, FRm);
1.503 + push_dr(R_EDX, FRn);
1.515 +FTRV XMTRX, FVn {:
1.521 + load_spreg( R_ECX, R_FPSCR );
1.522 + XOR_imm32_r32( FPSCR_FR, R_ECX );
1.523 + store_spreg( R_ECX, R_FPSCR );
1.528 + load_spreg( R_ECX, R_FPSCR );
1.529 + XOR_imm32_r32( FPSCR_SZ, R_ECX );
1.530 + store_spreg( R_ECX, R_FPSCR );
1.533 /* Processor control instructions */
1.535 load_reg( R_EAX, Rm );
1.536 call_func1( sh4_write_sr, R_EAX );
1.537 + sh4_x86.priv_checked = FALSE;
1.538 + sh4_x86.fpuen_checked = FALSE;
1.541 load_reg( R_EAX, Rm );
1.542 @@ -1508,6 +1809,8 @@
1.543 store_reg( R_EAX, Rm );
1.544 MEM_READ_LONG( R_ECX, R_EAX );
1.545 call_func1( sh4_write_sr, R_EAX );
1.546 + sh4_x86.priv_checked = FALSE;
1.547 + sh4_x86.fpuen_checked = FALSE;
1.550 load_reg( R_EAX, Rm );
1.551 @@ -1628,7 +1931,7 @@
1.552 CMP_imm32_r32( 0xE0000000, R_EAX );
1.554 call_func0( sh4_flush_store_queue );
1.555 - ADD_imm8s_r32( -4, R_ESP );
1.556 + ADD_imm8s_r32( 4, R_ESP );
1.558 SLEEP {: /* TODO */ :}