Search
lxdream.org :: lxdream/src/pvr2/pvr2.c :: diff
lxdream 0.9.1
released Jun 29
Download Now
filename src/pvr2/pvr2.c
changeset 335:fb890e1814c0
prev304:2855cf8709a5
next337:cdd757aa8e8c
author nkeynes
date Sat Jan 27 12:03:53 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Start working towards more thorough interlaced support
file annotate diff log raw
1.1 --- a/src/pvr2/pvr2.c Thu Jan 18 11:13:12 2007 +0000
1.2 +++ b/src/pvr2/pvr2.c Sat Jan 27 12:03:53 2007 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: pvr2.c,v 1.41 2007-01-18 11:13:12 nkeynes Exp $
1.6 + * $Id: pvr2.c,v 1.42 2007-01-27 12:03:53 nkeynes Exp $
1.7 *
1.8 * PVR2 (Video) Core module implementation and MMIO registers.
1.9 *
1.10 @@ -238,24 +238,38 @@
1.11 */
1.12 void pvr2_display_frame( void )
1.13 {
1.14 - uint32_t display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
1.15 -
1.16 + uint32_t display_addr;
1.17 int dispsize = MMIO_READ( PVR2, DISP_SIZE );
1.18 int dispmode = MMIO_READ( PVR2, DISP_MODE );
1.19 int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
1.20 - int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
1.21 + int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
1.22 int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
1.23 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
1.24 - gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
1.25 + gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
1.26 gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
1.27 video_buffer_t buffer = &video_buffer[video_buffer_idx];
1.28 video_buffer_idx = !video_buffer_idx;
1.29 video_buffer_t last = &video_buffer[video_buffer_idx];
1.30 buffer->rowstride = (vid_ppl + vid_stride) << 2;
1.31 buffer->data = video_base + MMIO_READ( PVR2, DISP_ADDR1 );
1.32 + buffer->line_double = (dispmode & DISPMODE_LINEDOUBLE) ? TRUE : FALSE;
1.33 buffer->vres = vid_lpf;
1.34 - if( interlaced ) buffer->vres <<= 1;
1.35 - switch( (dispmode & DISPMODE_COL) >> 2 ) {
1.36 + if( interlaced ) {
1.37 + if( vid_ppl == vid_stride ) { /* Magic deinterlace */
1.38 + buffer->vres <<= 1;
1.39 + buffer->rowstride = vid_ppl << 2;
1.40 + display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
1.41 + } else { /* Just display the field as is, folks */
1.42 + if( pvr2_state.odd_even_field ) {
1.43 + display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
1.44 + } else {
1.45 + display_addr = MMIO_READ( PVR2, DISP_ADDR2 );
1.46 + }
1.47 + }
1.48 + } else {
1.49 + display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
1.50 + }
1.51 + switch( (dispmode & DISPMODE_COLFMT) >> 2 ) {
1.52 case 0:
1.53 buffer->colour_format = COLFMT_ARGB1555;
1.54 buffer->hres = vid_ppl << 1;
1.55 @@ -520,12 +534,7 @@
1.56 case TA_REINIT:
1.57 break;
1.58 /**************** Scaler registers? ****************/
1.59 - case SCALERCFG:
1.60 - /* KOS suggests bits as follows:
1.61 - * 0: enable vertical scaling
1.62 - * 10: ???
1.63 - * 16: enable FSAA
1.64 - */
1.65 + case RENDER_SCALER:
1.66 MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
1.67 break;
1.68
.