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lxdream.org :: lxdream/src/sh4/sh4x86.in :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 382:fce3f4da92ab
prev381:aade6c9aca4d
next386:6fb10951326a
author nkeynes
date Thu Sep 13 08:28:01 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Fix exception handling
Fix various instruction bugs
file annotate diff log raw
1.1 --- a/src/sh4/sh4x86.in Wed Sep 12 11:41:43 2007 +0000
1.2 +++ b/src/sh4/sh4x86.in Thu Sep 13 08:28:01 2007 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: sh4x86.in,v 1.8 2007-09-12 11:41:43 nkeynes Exp $
1.6 + * $Id: sh4x86.in,v 1.9 2007-09-13 08:28:01 nkeynes Exp $
1.7 *
1.8 * SH4 => x86 translation. This version does no real optimization, it just
1.9 * outputs straight-line x86 code - it mainly exists to provide a baseline
1.10 @@ -335,7 +335,7 @@
1.11 #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
1.12
1.13 #define RAISE_EXCEPTION( exc ) call_func1(sh4_raise_exception, exc);
1.14 -#define SLOTILLEGAL() RAISE_EXCEPTION(EXC_SLOT_ILLEGAL); return 1
1.15 +#define SLOTILLEGAL() RAISE_EXCEPTION(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1
1.16
1.17
1.18
1.19 @@ -415,6 +415,9 @@
1.20
1.21 load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
1.22 CALL_r32( R_EAX ); // 2
1.23 + ADD_imm8s_r32( 4, R_ESP );
1.24 + POP_r32(R_ESI);
1.25 + POP_r32(R_EDI);
1.26 POP_r32(R_EBP);
1.27 RET();
1.28
1.29 @@ -589,7 +592,7 @@
1.30 :}
1.31 DT Rn {:
1.32 load_reg( R_EAX, Rn );
1.33 - ADD_imm8s_r32( -1, Rn );
1.34 + ADD_imm8s_r32( -1, R_EAX );
1.35 store_reg( R_EAX, Rn );
1.36 SETE_t();
1.37 :}
1.38 @@ -705,12 +708,13 @@
1.39 load_reg( R_EAX, Rn );
1.40 load_reg( R_ECX, Rm );
1.41 CMP_imm32_r32( 0, R_ECX );
1.42 - JAE_rel8(9, doshl);
1.43 + JGE_rel8(9, doshl);
1.44
1.45 NEG_r32( R_ECX ); // 2
1.46 AND_imm8_r8( 0x1F, R_CL ); // 3
1.47 SAR_r32_CL( R_EAX ); // 2
1.48 JMP_rel8(5, end); // 2
1.49 +
1.50 JMP_TARGET(doshl);
1.51 AND_imm8_r8( 0x1F, R_CL ); // 3
1.52 SHL_r32_CL( R_EAX ); // 2
1.53 @@ -720,13 +724,18 @@
1.54 SHLD Rm, Rn {:
1.55 load_reg( R_EAX, Rn );
1.56 load_reg( R_ECX, Rm );
1.57 + CMP_imm32_r32( 0, R_ECX );
1.58 + JGE_rel8(9, doshl);
1.59
1.60 - MOV_r32_r32( R_EAX, R_EDX );
1.61 - SHL_r32_CL( R_EAX );
1.62 - NEG_r32( R_ECX );
1.63 - SHR_r32_CL( R_EDX );
1.64 - CMP_imm8s_r32( 0, R_ECX );
1.65 - CMOVAE_r32_r32( R_EDX, R_EAX );
1.66 + NEG_r32( R_ECX ); // 2
1.67 + AND_imm8_r8( 0x1F, R_CL ); // 3
1.68 + SHR_r32_CL( R_EAX ); // 2
1.69 + JMP_rel8(5, end); // 2
1.70 +
1.71 + JMP_TARGET(doshl);
1.72 + AND_imm8_r8( 0x1F, R_CL ); // 3
1.73 + SHL_r32_CL( R_EAX ); // 2
1.74 + JMP_TARGET(end);
1.75 store_reg( R_EAX, Rn );
1.76 :}
1.77 SHAL Rn {:
1.78 @@ -884,7 +893,7 @@
1.79 MOV.B Rm, @-Rn {:
1.80 load_reg( R_EAX, Rm );
1.81 load_reg( R_ECX, Rn );
1.82 - ADD_imm8s_r32( -1, Rn );
1.83 + ADD_imm8s_r32( -1, R_ECX );
1.84 store_reg( R_ECX, Rn );
1.85 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.86 :}
1.87 @@ -983,7 +992,7 @@
1.88 :}
1.89 MOV.L @Rm+, Rn {:
1.90 load_reg( R_EAX, Rm );
1.91 - check_ralign32( R_ECX );
1.92 + check_ralign32( R_EAX );
1.93 MOV_r32_r32( R_EAX, R_ECX );
1.94 ADD_imm8s_r32( 4, R_EAX );
1.95 store_reg( R_EAX, Rm );
1.96 @@ -1011,7 +1020,7 @@
1.97 } else {
1.98 load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
1.99 MEM_READ_LONG( R_ECX, R_EAX );
1.100 - store_reg( R_EAX, 0 );
1.101 + store_reg( R_EAX, Rn );
1.102 }
1.103 :}
1.104 MOV.L @(disp, Rm), Rn {:
1.105 @@ -1024,14 +1033,15 @@
1.106 MOV.W Rm, @Rn {:
1.107 load_reg( R_ECX, Rn );
1.108 check_walign16( R_ECX );
1.109 - MEM_READ_WORD( R_ECX, R_EAX );
1.110 - store_reg( R_EAX, Rn );
1.111 + load_reg( R_EAX, Rm );
1.112 + MEM_WRITE_WORD( R_ECX, R_EAX );
1.113 :}
1.114 MOV.W Rm, @-Rn {:
1.115 load_reg( R_ECX, Rn );
1.116 check_walign16( R_ECX );
1.117 load_reg( R_EAX, Rm );
1.118 ADD_imm8s_r32( -2, R_ECX );
1.119 + store_reg( R_ECX, Rn );
1.120 MEM_WRITE_WORD( R_ECX, R_EAX );
1.121 :}
1.122 MOV.W Rm, @(R0, Rn) {:
1.123 @@ -1160,6 +1170,7 @@
1.124 SLOTILLEGAL();
1.125 } else {
1.126 load_reg( R_EDI, Rn );
1.127 + ADD_imm32_r32( pc + 4, R_EDI );
1.128 sh4_x86.in_delay_slot = TRUE;
1.129 INC_r32(R_ESI);
1.130 return 0;
1.131 @@ -1274,11 +1285,11 @@
1.132 :}
1.133 UNDEF {:
1.134 if( sh4_x86.in_delay_slot ) {
1.135 - RAISE_EXCEPTION(EXC_SLOT_ILLEGAL);
1.136 + SLOTILLEGAL();
1.137 } else {
1.138 RAISE_EXCEPTION(EXC_ILLEGAL);
1.139 + return 1;
1.140 }
1.141 - return 1;
1.142 :}
1.143
1.144 CLRMAC {:
1.145 @@ -1416,14 +1427,14 @@
1.146 check_walign32( R_EDX );
1.147 load_spreg( R_ECX, R_FPSCR );
1.148 TEST_imm32_r32( FPSCR_SZ, R_ECX );
1.149 - JNE_rel8(20, doublesize);
1.150 + JNE_rel8(26, doublesize);
1.151 load_fr_bank( R_ECX );
1.152 load_fr( R_ECX, R_EAX, FRm );
1.153 ADD_imm8s_r32(-4,R_EDX);
1.154 store_reg( R_EDX, Rn );
1.155 MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
1.156 if( FRm&1 ) {
1.157 - JMP_rel8( 46, end );
1.158 + JMP_rel8( 52, end );
1.159 JMP_TARGET(doublesize);
1.160 load_xf_bank( R_ECX );
1.161 load_fr( R_ECX, R_EAX, FRm&0x0E );
1.162 @@ -1433,7 +1444,7 @@
1.163 MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
1.164 JMP_TARGET(end);
1.165 } else {
1.166 - JMP_rel8( 39, end );
1.167 + JMP_rel8( 45, end );
1.168 JMP_TARGET(doublesize);
1.169 load_fr_bank( R_ECX );
1.170 load_fr( R_ECX, R_EAX, FRm&0x0E );
1.171 @@ -1780,10 +1791,10 @@
1.172 JMP_TARGET(doubleprec);
1.173 push_dr(R_EDX, FRm);
1.174 push_dr(R_EDX, FRn);
1.175 + JMP_TARGET(end);
1.176 FCOMIP_st(1);
1.177 SETE_t();
1.178 FPOP_st();
1.179 - JMP_TARGET(end);
1.180 :}
1.181 FCMP/GT FRm, FRn {:
1.182 check_fpuen();
1.183 @@ -2037,56 +2048,56 @@
1.184 :}
1.185 STC.L SR, @-Rn {:
1.186 load_reg( R_ECX, Rn );
1.187 - ADD_imm8s_r32( -4, Rn );
1.188 + ADD_imm8s_r32( -4, R_ECX );
1.189 store_reg( R_ECX, Rn );
1.190 call_func0( sh4_read_sr );
1.191 MEM_WRITE_LONG( R_ECX, R_EAX );
1.192 :}
1.193 STC.L VBR, @-Rn {:
1.194 load_reg( R_ECX, Rn );
1.195 - ADD_imm8s_r32( -4, Rn );
1.196 + ADD_imm8s_r32( -4, R_ECX );
1.197 store_reg( R_ECX, Rn );
1.198 load_spreg( R_EAX, R_VBR );
1.199 MEM_WRITE_LONG( R_ECX, R_EAX );
1.200 :}
1.201 STC.L SSR, @-Rn {:
1.202 load_reg( R_ECX, Rn );
1.203 - ADD_imm8s_r32( -4, Rn );
1.204 + ADD_imm8s_r32( -4, R_ECX );
1.205 store_reg( R_ECX, Rn );
1.206 load_spreg( R_EAX, R_SSR );
1.207 MEM_WRITE_LONG( R_ECX, R_EAX );
1.208 :}
1.209 STC.L SPC, @-Rn {:
1.210 load_reg( R_ECX, Rn );
1.211 - ADD_imm8s_r32( -4, Rn );
1.212 + ADD_imm8s_r32( -4, R_ECX );
1.213 store_reg( R_ECX, Rn );
1.214 load_spreg( R_EAX, R_SPC );
1.215 MEM_WRITE_LONG( R_ECX, R_EAX );
1.216 :}
1.217 STC.L SGR, @-Rn {:
1.218 load_reg( R_ECX, Rn );
1.219 - ADD_imm8s_r32( -4, Rn );
1.220 + ADD_imm8s_r32( -4, R_ECX );
1.221 store_reg( R_ECX, Rn );
1.222 load_spreg( R_EAX, R_SGR );
1.223 MEM_WRITE_LONG( R_ECX, R_EAX );
1.224 :}
1.225 STC.L DBR, @-Rn {:
1.226 load_reg( R_ECX, Rn );
1.227 - ADD_imm8s_r32( -4, Rn );
1.228 + ADD_imm8s_r32( -4, R_ECX );
1.229 store_reg( R_ECX, Rn );
1.230 load_spreg( R_EAX, R_DBR );
1.231 MEM_WRITE_LONG( R_ECX, R_EAX );
1.232 :}
1.233 STC.L Rm_BANK, @-Rn {:
1.234 load_reg( R_ECX, Rn );
1.235 - ADD_imm8s_r32( -4, Rn );
1.236 + ADD_imm8s_r32( -4, R_ECX );
1.237 store_reg( R_ECX, Rn );
1.238 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
1.239 MEM_WRITE_LONG( R_ECX, R_EAX );
1.240 :}
1.241 STC.L GBR, @-Rn {:
1.242 load_reg( R_ECX, Rn );
1.243 - ADD_imm8s_r32( -4, Rn );
1.244 + ADD_imm8s_r32( -4, R_ECX );
1.245 store_reg( R_ECX, Rn );
1.246 load_spreg( R_EAX, R_GBR );
1.247 MEM_WRITE_LONG( R_ECX, R_EAX );
1.248 @@ -2097,7 +2108,7 @@
1.249 :}
1.250 STS.L FPSCR, @-Rn {:
1.251 load_reg( R_ECX, Rn );
1.252 - ADD_imm8s_r32( -4, Rn );
1.253 + ADD_imm8s_r32( -4, R_ECX );
1.254 store_reg( R_ECX, Rn );
1.255 load_spreg( R_EAX, R_FPSCR );
1.256 MEM_WRITE_LONG( R_ECX, R_EAX );
1.257 @@ -2108,7 +2119,7 @@
1.258 :}
1.259 STS.L FPUL, @-Rn {:
1.260 load_reg( R_ECX, Rn );
1.261 - ADD_imm8s_r32( -4, Rn );
1.262 + ADD_imm8s_r32( -4, R_ECX );
1.263 store_reg( R_ECX, Rn );
1.264 load_spreg( R_EAX, R_FPUL );
1.265 MEM_WRITE_LONG( R_ECX, R_EAX );
1.266 @@ -2119,7 +2130,7 @@
1.267 :}
1.268 STS.L MACH, @-Rn {:
1.269 load_reg( R_ECX, Rn );
1.270 - ADD_imm8s_r32( -4, Rn );
1.271 + ADD_imm8s_r32( -4, R_ECX );
1.272 store_reg( R_ECX, Rn );
1.273 load_spreg( R_EAX, R_MACH );
1.274 MEM_WRITE_LONG( R_ECX, R_EAX );
1.275 @@ -2130,7 +2141,7 @@
1.276 :}
1.277 STS.L MACL, @-Rn {:
1.278 load_reg( R_ECX, Rn );
1.279 - ADD_imm8s_r32( -4, Rn );
1.280 + ADD_imm8s_r32( -4, R_ECX );
1.281 store_reg( R_ECX, Rn );
1.282 load_spreg( R_EAX, R_MACL );
1.283 MEM_WRITE_LONG( R_ECX, R_EAX );
1.284 @@ -2141,7 +2152,7 @@
1.285 :}
1.286 STS.L PR, @-Rn {:
1.287 load_reg( R_ECX, Rn );
1.288 - ADD_imm8s_r32( -4, Rn );
1.289 + ADD_imm8s_r32( -4, R_ECX );
1.290 store_reg( R_ECX, Rn );
1.291 load_spreg( R_EAX, R_PR );
1.292 MEM_WRITE_LONG( R_ECX, R_EAX );
.