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lxdream.org :: lxdream/src/asic.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/asic.c
changeset 929:fd8cb0c82f5f
prev855:b937948d79d9
next975:007bf7eb944f
author nkeynes
date Sat Dec 20 03:01:40 2008 +0000 (11 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change First pass experiment using cached decoding.
file annotate diff log raw
1.1 --- a/src/asic.c Wed Sep 10 02:03:20 2008 +0000
1.2 +++ b/src/asic.c Sat Dec 20 03:01:40 2008 +0000
1.3 @@ -416,8 +416,38 @@
1.4 MMIO_WRITE( ASIC, SORTDMACTL, 0 );
1.5 }
1.6
1.7 -void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
1.8 +MMIO_REGION_READ_FN( ASIC, reg )
1.9 {
1.10 + int32_t val;
1.11 + reg &= 0xFFF;
1.12 + switch( reg ) {
1.13 + case PIRQ0:
1.14 + case PIRQ1:
1.15 + case PIRQ2:
1.16 + case IRQA0:
1.17 + case IRQA1:
1.18 + case IRQA2:
1.19 + case IRQB0:
1.20 + case IRQB1:
1.21 + case IRQB2:
1.22 + case IRQC0:
1.23 + case IRQC1:
1.24 + case IRQC2:
1.25 + case MAPLE_STATE:
1.26 + val = MMIO_READ(ASIC, reg);
1.27 + return val;
1.28 + case G2STATUS:
1.29 + return g2_read_status();
1.30 + default:
1.31 + val = MMIO_READ(ASIC, reg);
1.32 + return val;
1.33 + }
1.34 +
1.35 +}
1.36 +
1.37 +MMIO_REGION_WRITE_FN( ASIC, reg, val )
1.38 +{
1.39 + reg &= 0xFFF;
1.40 switch( reg ) {
1.41 case PIRQ1:
1.42 break; /* Treat this as read-only for the moment */
1.43 @@ -496,36 +526,37 @@
1.44 }
1.45 }
1.46
1.47 -int32_t mmio_region_ASIC_read( uint32_t reg )
1.48 +MMIO_REGION_READ_FN( EXTDMA, reg )
1.49 {
1.50 - int32_t val;
1.51 + uint32_t val;
1.52 + reg &= 0xFFF;
1.53 + if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
1.54 + return 0xFFFFFFFF; /* disabled */
1.55 + }
1.56 +
1.57 switch( reg ) {
1.58 - case PIRQ0:
1.59 - case PIRQ1:
1.60 - case PIRQ2:
1.61 - case IRQA0:
1.62 - case IRQA1:
1.63 - case IRQA2:
1.64 - case IRQB0:
1.65 - case IRQB1:
1.66 - case IRQB2:
1.67 - case IRQC0:
1.68 - case IRQC1:
1.69 - case IRQC2:
1.70 - case MAPLE_STATE:
1.71 - val = MMIO_READ(ASIC, reg);
1.72 - return val;
1.73 - case G2STATUS:
1.74 - return g2_read_status();
1.75 + case IDEALTSTATUS:
1.76 + val = idereg.status;
1.77 + return val;
1.78 + case IDEDATA: return ide_read_data_pio( );
1.79 + case IDEFEAT: return idereg.error;
1.80 + case IDECOUNT:return idereg.count;
1.81 + case IDELBA0: return ide_get_drive_status();
1.82 + case IDELBA1: return idereg.lba1;
1.83 + case IDELBA2: return idereg.lba2;
1.84 + case IDEDEV: return idereg.device;
1.85 + case IDECMD:
1.86 + val = ide_read_status();
1.87 + return val;
1.88 default:
1.89 - val = MMIO_READ(ASIC, reg);
1.90 + val = MMIO_READ( EXTDMA, reg );
1.91 return val;
1.92 }
1.93 -
1.94 }
1.95
1.96 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
1.97 {
1.98 + reg &= 0xFFF;
1.99 if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
1.100 return; /* disabled */
1.101 }
1.102 @@ -645,30 +676,3 @@
1.103 }
1.104 }
1.105
1.106 -MMIO_REGION_READ_FN( EXTDMA, reg )
1.107 -{
1.108 - uint32_t val;
1.109 - if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
1.110 - return 0xFFFFFFFF; /* disabled */
1.111 - }
1.112 -
1.113 - switch( reg ) {
1.114 - case IDEALTSTATUS:
1.115 - val = idereg.status;
1.116 - return val;
1.117 - case IDEDATA: return ide_read_data_pio( );
1.118 - case IDEFEAT: return idereg.error;
1.119 - case IDECOUNT:return idereg.count;
1.120 - case IDELBA0: return ide_get_drive_status();
1.121 - case IDELBA1: return idereg.lba1;
1.122 - case IDELBA2: return idereg.lba2;
1.123 - case IDEDEV: return idereg.device;
1.124 - case IDECMD:
1.125 - val = ide_read_status();
1.126 - return val;
1.127 - default:
1.128 - val = MMIO_READ( EXTDMA, reg );
1.129 - return val;
1.130 - }
1.131 -}
1.132 -
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