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lxdream.org :: lxdream/src/sh4/mmu.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/mmu.c
changeset 929:fd8cb0c82f5f
prev927:17b6b9e245d8
next931:430048ea8b71
author nkeynes
date Sat Dec 20 03:01:40 2008 +0000 (12 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change First pass experiment using cached decoding.
file annotate diff log raw
1.1 --- a/src/sh4/mmu.c Mon Dec 15 10:44:56 2008 +0000
1.2 +++ b/src/sh4/mmu.c Sat Dec 20 03:01:40 2008 +0000
1.3 @@ -143,8 +143,9 @@
1.4 }
1.5 }
1.6
1.7 -int32_t mmio_region_MMU_read( uint32_t reg )
1.8 +MMIO_REGION_READ_FN( MMU, reg )
1.9 {
1.10 + reg &= 0xFFF;
1.11 switch( reg ) {
1.12 case MMUCR:
1.13 return MMIO_READ( MMU, MMUCR) | (mmu_urc<<10) | (mmu_urb<<18) | (mmu_lrui<<26);
1.14 @@ -153,9 +154,10 @@
1.15 }
1.16 }
1.17
1.18 -void mmio_region_MMU_write( uint32_t reg, uint32_t val )
1.19 +MMIO_REGION_WRITE_FN( MMU, reg, val )
1.20 {
1.21 uint32_t tmp;
1.22 + reg &= 0xFFF;
1.23 switch(reg) {
1.24 case SH4VER:
1.25 return;
1.26 @@ -448,18 +450,18 @@
1.27
1.28 #define ITLB_ENTRY(addr) ((addr>>7)&0x03)
1.29
1.30 -int32_t mmu_itlb_addr_read( sh4addr_t addr )
1.31 +int32_t FASTCALL mmu_itlb_addr_read( sh4addr_t addr )
1.32 {
1.33 struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
1.34 return ent->vpn | ent->asid | (ent->flags & TLB_VALID);
1.35 }
1.36 -int32_t mmu_itlb_data_read( sh4addr_t addr )
1.37 +int32_t FASTCALL mmu_itlb_data_read( sh4addr_t addr )
1.38 {
1.39 struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
1.40 return (ent->ppn & 0x1FFFFC00) | ent->flags;
1.41 }
1.42
1.43 -void mmu_itlb_addr_write( sh4addr_t addr, uint32_t val )
1.44 +void FASTCALL mmu_itlb_addr_write( sh4addr_t addr, uint32_t val )
1.45 {
1.46 struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
1.47 ent->vpn = val & 0xFFFFFC00;
1.48 @@ -467,7 +469,7 @@
1.49 ent->flags = (ent->flags & ~(TLB_VALID)) | (val&TLB_VALID);
1.50 }
1.51
1.52 -void mmu_itlb_data_write( sh4addr_t addr, uint32_t val )
1.53 +void FASTCALL mmu_itlb_data_write( sh4addr_t addr, uint32_t val )
1.54 {
1.55 struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
1.56 ent->ppn = val & 0x1FFFFC00;
1.57 @@ -481,13 +483,13 @@
1.58 #define UTLB_ASSOC(addr) (addr&0x80)
1.59 #define UTLB_DATA2(addr) (addr&0x00800000)
1.60
1.61 -int32_t mmu_utlb_addr_read( sh4addr_t addr )
1.62 +int32_t FASTCALL mmu_utlb_addr_read( sh4addr_t addr )
1.63 {
1.64 struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
1.65 return ent->vpn | ent->asid | (ent->flags & TLB_VALID) |
1.66 ((ent->flags & TLB_DIRTY)<<7);
1.67 }
1.68 -int32_t mmu_utlb_data_read( sh4addr_t addr )
1.69 +int32_t FASTCALL mmu_utlb_data_read( sh4addr_t addr )
1.70 {
1.71 struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
1.72 if( UTLB_DATA2(addr) ) {
1.73 @@ -540,7 +542,7 @@
1.74 return result;
1.75 }
1.76
1.77 -void mmu_utlb_addr_write( sh4addr_t addr, uint32_t val )
1.78 +void FASTCALL mmu_utlb_addr_write( sh4addr_t addr, uint32_t val )
1.79 {
1.80 if( UTLB_ASSOC(addr) ) {
1.81 int utlb = mmu_utlb_lookup_assoc( val, mmu_asid );
1.82 @@ -581,7 +583,7 @@
1.83 }
1.84 }
1.85
1.86 -void mmu_utlb_data_write( sh4addr_t addr, uint32_t val )
1.87 +void FASTCALL mmu_utlb_data_write( sh4addr_t addr, uint32_t val )
1.88 {
1.89 struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
1.90 if( UTLB_DATA2(addr) ) {
1.91 @@ -601,36 +603,36 @@
1.92
1.93 /* Cache access - not implemented */
1.94
1.95 -int32_t mmu_icache_addr_read( sh4addr_t addr )
1.96 +int32_t FASTCALL mmu_icache_addr_read( sh4addr_t addr )
1.97 {
1.98 return 0; // not implemented
1.99 }
1.100 -int32_t mmu_icache_data_read( sh4addr_t addr )
1.101 +int32_t FASTCALL mmu_icache_data_read( sh4addr_t addr )
1.102 {
1.103 return 0; // not implemented
1.104 }
1.105 -int32_t mmu_ocache_addr_read( sh4addr_t addr )
1.106 +int32_t FASTCALL mmu_ocache_addr_read( sh4addr_t addr )
1.107 {
1.108 return 0; // not implemented
1.109 }
1.110 -int32_t mmu_ocache_data_read( sh4addr_t addr )
1.111 +int32_t FASTCALL mmu_ocache_data_read( sh4addr_t addr )
1.112 {
1.113 return 0; // not implemented
1.114 }
1.115
1.116 -void mmu_icache_addr_write( sh4addr_t addr, uint32_t val )
1.117 +void FASTCALL mmu_icache_addr_write( sh4addr_t addr, uint32_t val )
1.118 {
1.119 }
1.120
1.121 -void mmu_icache_data_write( sh4addr_t addr, uint32_t val )
1.122 +void FASTCALL mmu_icache_data_write( sh4addr_t addr, uint32_t val )
1.123 {
1.124 }
1.125
1.126 -void mmu_ocache_addr_write( sh4addr_t addr, uint32_t val )
1.127 +void FASTCALL mmu_ocache_addr_write( sh4addr_t addr, uint32_t val )
1.128 {
1.129 }
1.130
1.131 -void mmu_ocache_data_write( sh4addr_t addr, uint32_t val )
1.132 +void FASTCALL mmu_ocache_data_write( sh4addr_t addr, uint32_t val )
1.133 {
1.134 }
1.135
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