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lxdream.org :: lxdream/src/sh4/sh4x86.in :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 929:fd8cb0c82f5f
prev927:17b6b9e245d8
next930:07e5b11419db
author nkeynes
date Sat Dec 20 03:01:40 2008 +0000 (12 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change First pass experiment using cached decoding.
file annotate diff log raw
1.1 --- a/src/sh4/sh4x86.in Mon Dec 15 10:44:56 2008 +0000
1.2 +++ b/src/sh4/sh4x86.in Sat Dec 20 03:01:40 2008 +0000
1.3 @@ -20,6 +20,7 @@
1.4
1.5 #include <assert.h>
1.6 #include <math.h>
1.7 +#include <stddef.h>
1.8
1.9 #ifndef NDEBUG
1.10 #define DEBUG_JUMPS 1
1.11 @@ -322,6 +323,111 @@
1.12 #include "sh4/ia32abi.h"
1.13 #endif
1.14
1.15 +#define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )
1.16 +
1.17 +/**
1.18 + * Given an address in addr_reg and a cache entry, test if the cache is valid
1.19 + * and decode otherwise.
1.20 + * At conclusion of this:
1.21 + * R_EBX will contain the address
1.22 + * R_ECX will contain the memory region vtable
1.23 + * R_EAX, R_EDX (and any other volatiles) are clobbered
1.24 + */
1.25 +static inline void MEM_DECODE_ADDRESS( int addr_reg, int rm )
1.26 +{
1.27 + MOV_r32_r32( addr_reg, R_EBX );
1.28 + AND_sh4r_r32( REG_OFFSET(pointer_cache[rm].page_mask), addr_reg );
1.29 + CMP_sh4r_r32( REG_OFFSET(pointer_cache[rm].page_vma), addr_reg );
1.30 + EXPJE_rel8(uptodate);
1.31 + store_spreg( addr_reg, REG_OFFSET(pointer_cache[rm].page_vma) );
1.32 + call_func1( sh7750_decode_address, addr_reg );
1.33 + store_spreg( R_EAX, REG_OFFSET(pointer_cache[rm].page_fn) );
1.34 + JMP_TARGET(uptodate);
1.35 + load_spreg( R_ECX, REG_OFFSET(pointer_cache[rm].page_fn) );
1.36 +}
1.37 +
1.38 +static inline void MEM_READ_LONG_CACHED( int addr_reg, int value_reg, int rm )
1.39 +{
1.40 + MEM_DECODE_ADDRESS( addr_reg, rm );
1.41 + call_func1_r32ind( R_ECX, MEM_REGION_PTR(read_long), R_EBX );
1.42 + MEM_RESULT(value_reg);
1.43 +}
1.44 +
1.45 +static inline void MEM_READ_WORD_CACHED( int addr_reg, int value_reg, int rm )
1.46 +{
1.47 + MEM_DECODE_ADDRESS( addr_reg, rm );
1.48 + call_func1_r32ind( R_ECX, MEM_REGION_PTR(read_word), R_EBX );
1.49 + MEM_RESULT(value_reg);
1.50 +}
1.51 +
1.52 +static inline void MEM_READ_BYTE_CACHED( int addr_reg, int value_reg, int rm )
1.53 +{
1.54 + MEM_DECODE_ADDRESS( addr_reg, rm );
1.55 + call_func1_r32ind( R_ECX, MEM_REGION_PTR(read_byte), R_EBX );
1.56 + MEM_RESULT(value_reg);
1.57 +}
1.58 +
1.59 +static inline void MEM_WRITE_LONG_CACHED_SP( int addr_reg, int ebpdisp, int rn )
1.60 +{
1.61 + MEM_DECODE_ADDRESS( addr_reg, rn );
1.62 + MOV_sh4r_r32( ebpdisp, R_EDX );
1.63 + call_func2_r32ind( R_ECX, MEM_REGION_PTR(write_long), R_EBX, R_EDX );
1.64 +}
1.65 +
1.66 +#define MEM_WRITE_LONG_CACHED( addr_reg, value_rm, rn ) MEM_WRITE_LONG_CACHED_SP( addr_reg, REG_OFFSET(r[value_rm]), rn )
1.67 +
1.68 +static inline void MEM_WRITE_WORD_CACHED( int addr_reg, int value_rm, int rn )
1.69 +{
1.70 + MEM_DECODE_ADDRESS( addr_reg, rn );
1.71 + MOVZX_sh4r16_r32( REG_OFFSET(r[value_rm]), R_EDX );
1.72 + call_func2_r32ind( R_ECX, MEM_REGION_PTR(write_word), R_EBX, R_EDX );
1.73 +}
1.74 +
1.75 +static inline void MEM_WRITE_BYTE_CACHED( int addr_reg, int value_rm, int rn )
1.76 +{
1.77 + MEM_DECODE_ADDRESS( addr_reg, rn );
1.78 + MOVZX_sh4r8_r32( REG_OFFSET(r[value_rm]), R_EDX );
1.79 + call_func2_r32ind( R_ECX, MEM_REGION_PTR(write_byte), R_EBX, R_EDX );
1.80 +}
1.81 +
1.82 +static inline void MEM_WRITE_BYTE_UNCHECKED( int addr_reg, int value_reg, int rn )
1.83 +{
1.84 + load_spreg( R_ECX, REG_OFFSET(pointer_cache[rn].page_fn) );
1.85 + call_func2_r32ind( R_ECX, MEM_REGION_PTR(write_byte), addr_reg, R_EDX );
1.86 +}
1.87 +
1.88 +static inline void MEM_WRITE_FLOAT_CACHED( int addr_reg, int value_frm, int rn )
1.89 +{
1.90 + MEM_DECODE_ADDRESS( addr_reg, rn );
1.91 + load_fr( R_EDX, value_frm );
1.92 + call_func2_r32ind( R_ECX, MEM_REGION_PTR(write_long), R_EBX, R_EDX );
1.93 +}
1.94 +
1.95 +static inline void MEM_READ_DOUBLE_CACHED( int addr_reg, int value_reg1, int value_reg2, int rm )
1.96 +{
1.97 + MEM_DECODE_ADDRESS( addr_reg, rm );
1.98 + call_func1_r32ind( R_ECX, MEM_REGION_PTR(read_long), R_EBX );
1.99 + MOV_r32_esp8( R_EAX, 0 );
1.100 + load_spreg( R_ECX, REG_OFFSET(pointer_cache[rm].page_fn) );
1.101 + LEA_r32disp8_r32( R_EBX, 4, R_EBX );
1.102 + call_func1_r32ind( R_ECX, MEM_REGION_PTR(read_long), R_EBX );
1.103 + MEM_RESULT(value_reg2);
1.104 + MOV_esp8_r32( 0, value_reg1 );
1.105 +}
1.106 +
1.107 +static inline void MEM_WRITE_DOUBLE_CACHED( int addr_reg, int value_frm, int rn )
1.108 +{
1.109 + MEM_DECODE_ADDRESS( addr_reg, rn );
1.110 + load_dr0( R_EDX, value_frm );
1.111 + call_func2_r32ind( R_ECX, MEM_REGION_PTR(write_long), R_EBX, R_EDX );
1.112 + LEA_r32disp8_r32( R_EBX, 4, R_EBX );
1.113 + load_spreg( R_ECX, REG_OFFSET(pointer_cache[rn].page_fn) );
1.114 + load_dr1( R_EDX, value_frm );
1.115 + call_func2_r32ind( R_ECX, MEM_REGION_PTR(write_long), R_EBX, R_EDX );
1.116 +}
1.117 +
1.118 +
1.119 +
1.120 void sh4_translate_begin_block( sh4addr_t pc )
1.121 {
1.122 enter_block();
1.123 @@ -471,11 +577,9 @@
1.124 load_spreg( R_ECX, R_GBR );
1.125 ADD_r32_r32( R_ECX, R_EAX );
1.126 MMU_TRANSLATE_WRITE( R_EAX );
1.127 - MOV_r32_esp8(R_EAX, 0);
1.128 - MEM_READ_BYTE( R_EAX, R_EDX );
1.129 - MOV_esp8_r32(0, R_EAX);
1.130 + MEM_READ_BYTE_CACHED( R_EAX, R_EDX, 16 );
1.131 AND_imm32_r32(imm, R_EDX );
1.132 - MEM_WRITE_BYTE( R_EAX, R_EDX );
1.133 + MEM_WRITE_BYTE_UNCHECKED( R_EBX, R_EDX, 16 );
1.134 sh4_x86.tstate = TSTATE_NONE;
1.135 :}
1.136 CMP/EQ Rm, Rn {:
1.137 @@ -679,10 +783,10 @@
1.138 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.139 }
1.140 MEM_READ_LONG( R_EAX, R_EAX );
1.141 - MOV_r32_esp8( R_EAX, 4 );
1.142 + MOV_r32_r32( R_EAX, R_EBX );
1.143 MOV_esp8_r32( 0, R_EAX );
1.144 MEM_READ_LONG( R_EAX, R_EAX );
1.145 - MOV_esp8_r32( 4, R_ECX );
1.146 + MOV_r32_r32( R_EBX, R_ECX );
1.147
1.148 IMUL_r32( R_ECX );
1.149 ADD_r32_sh4r( R_EAX, R_MACL );
1.150 @@ -720,10 +824,10 @@
1.151 ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
1.152 }
1.153 MEM_READ_WORD( R_EAX, R_EAX );
1.154 - MOV_r32_esp8( R_EAX, 4 );
1.155 + MOV_r32_r32( R_EAX, R_EBX );
1.156 MOV_esp8_r32( 0, R_EAX );
1.157 MEM_READ_WORD( R_EAX, R_EAX );
1.158 - MOV_esp8_r32( 4, R_ECX );
1.159 + MOV_r32_r32( R_EBX, R_ECX );
1.160
1.161 IMUL_r32( R_ECX );
1.162 load_spreg( R_ECX, R_S );
1.163 @@ -826,11 +930,9 @@
1.164 load_spreg( R_ECX, R_GBR );
1.165 ADD_r32_r32( R_ECX, R_EAX );
1.166 MMU_TRANSLATE_WRITE( R_EAX );
1.167 - MOV_r32_esp8( R_EAX, 0 );
1.168 - MEM_READ_BYTE( R_EAX, R_EDX );
1.169 - MOV_esp8_r32( 0, R_EAX );
1.170 + MEM_READ_BYTE_CACHED( R_EAX, R_EDX, 16 );
1.171 OR_imm32_r32(imm, R_EDX );
1.172 - MEM_WRITE_BYTE( R_EAX, R_EDX );
1.173 + MEM_WRITE_BYTE_UNCHECKED( R_EBX, R_EDX, 16 );
1.174 sh4_x86.tstate = TSTATE_NONE;
1.175 :}
1.176 ROTCL Rn {:
1.177 @@ -1045,13 +1147,11 @@
1.178 COUNT_INST(I_TASB);
1.179 load_reg( R_EAX, Rn );
1.180 MMU_TRANSLATE_WRITE( R_EAX );
1.181 - MOV_r32_esp8( R_EAX, 0 );
1.182 - MEM_READ_BYTE( R_EAX, R_EDX );
1.183 + MEM_READ_BYTE_CACHED( R_EAX, R_EDX, 16 );
1.184 TEST_r8_r8( R_DL, R_DL );
1.185 SETE_t();
1.186 OR_imm8_r8( 0x80, R_DL );
1.187 - MOV_esp8_r32( 0, R_EAX );
1.188 - MEM_WRITE_BYTE( R_EAX, R_EDX );
1.189 + MEM_WRITE_BYTE_UNCHECKED( R_EBX, R_EDX, 16 );
1.190 sh4_x86.tstate = TSTATE_NONE;
1.191 :}
1.192 TST Rm, Rn {:
1.193 @@ -1075,7 +1175,7 @@
1.194 load_reg( R_ECX, R_GBR);
1.195 ADD_r32_r32( R_ECX, R_EAX );
1.196 MMU_TRANSLATE_READ( R_EAX );
1.197 - MEM_READ_BYTE( R_EAX, R_EAX );
1.198 + MEM_READ_BYTE_CACHED( R_EAX, R_EAX, 16 );
1.199 TEST_imm8_r8( imm, R_AL );
1.200 SETE_t();
1.201 sh4_x86.tstate = TSTATE_E;
1.202 @@ -1101,11 +1201,9 @@
1.203 load_spreg( R_ECX, R_GBR );
1.204 ADD_r32_r32( R_ECX, R_EAX );
1.205 MMU_TRANSLATE_WRITE( R_EAX );
1.206 - MOV_r32_esp8( R_EAX, 0 );
1.207 - MEM_READ_BYTE(R_EAX, R_EDX);
1.208 - MOV_esp8_r32( 0, R_EAX );
1.209 + MEM_READ_BYTE_CACHED(R_EAX, R_EDX, 16);
1.210 XOR_imm32_r32( imm, R_EDX );
1.211 - MEM_WRITE_BYTE( R_EAX, R_EDX );
1.212 + MEM_WRITE_BYTE_UNCHECKED( R_EBX, R_EDX, 16 );
1.213 sh4_x86.tstate = TSTATE_NONE;
1.214 :}
1.215 XTRCT Rm, Rn {:
1.216 @@ -1134,8 +1232,7 @@
1.217 COUNT_INST(I_MOVB);
1.218 load_reg( R_EAX, Rn );
1.219 MMU_TRANSLATE_WRITE( R_EAX );
1.220 - load_reg( R_EDX, Rm );
1.221 - MEM_WRITE_BYTE( R_EAX, R_EDX );
1.222 + MEM_WRITE_BYTE_CACHED( R_EAX, Rm, Rn );
1.223 sh4_x86.tstate = TSTATE_NONE;
1.224 :}
1.225 MOV.B Rm, @-Rn {:
1.226 @@ -1143,9 +1240,8 @@
1.227 load_reg( R_EAX, Rn );
1.228 ADD_imm8s_r32( -1, R_EAX );
1.229 MMU_TRANSLATE_WRITE( R_EAX );
1.230 - load_reg( R_EDX, Rm );
1.231 ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
1.232 - MEM_WRITE_BYTE( R_EAX, R_EDX );
1.233 + MEM_WRITE_BYTE_CACHED( R_EAX, Rm, Rn );
1.234 sh4_x86.tstate = TSTATE_NONE;
1.235 :}
1.236 MOV.B Rm, @(R0, Rn) {:
1.237 @@ -1154,8 +1250,7 @@
1.238 load_reg( R_ECX, Rn );
1.239 ADD_r32_r32( R_ECX, R_EAX );
1.240 MMU_TRANSLATE_WRITE( R_EAX );
1.241 - load_reg( R_EDX, Rm );
1.242 - MEM_WRITE_BYTE( R_EAX, R_EDX );
1.243 + MEM_WRITE_BYTE_CACHED( R_EAX, Rm, 0 );
1.244 sh4_x86.tstate = TSTATE_NONE;
1.245 :}
1.246 MOV.B R0, @(disp, GBR) {:
1.247 @@ -1163,8 +1258,7 @@
1.248 load_spreg( R_EAX, R_GBR );
1.249 ADD_imm32_r32( disp, R_EAX );
1.250 MMU_TRANSLATE_WRITE( R_EAX );
1.251 - load_reg( R_EDX, 0 );
1.252 - MEM_WRITE_BYTE( R_EAX, R_EDX );
1.253 + MEM_WRITE_BYTE_CACHED( R_EAX, 0, 16 );
1.254 sh4_x86.tstate = TSTATE_NONE;
1.255 :}
1.256 MOV.B R0, @(disp, Rn) {:
1.257 @@ -1172,15 +1266,14 @@
1.258 load_reg( R_EAX, Rn );
1.259 ADD_imm32_r32( disp, R_EAX );
1.260 MMU_TRANSLATE_WRITE( R_EAX );
1.261 - load_reg( R_EDX, 0 );
1.262 - MEM_WRITE_BYTE( R_EAX, R_EDX );
1.263 + MEM_WRITE_BYTE_CACHED( R_EAX, 0, Rn );
1.264 sh4_x86.tstate = TSTATE_NONE;
1.265 :}
1.266 MOV.B @Rm, Rn {:
1.267 COUNT_INST(I_MOVB);
1.268 load_reg( R_EAX, Rm );
1.269 MMU_TRANSLATE_READ( R_EAX );
1.270 - MEM_READ_BYTE( R_EAX, R_EAX );
1.271 + MEM_READ_BYTE_CACHED( R_EAX, R_EAX, Rm );
1.272 store_reg( R_EAX, Rn );
1.273 sh4_x86.tstate = TSTATE_NONE;
1.274 :}
1.275 @@ -1189,7 +1282,7 @@
1.276 load_reg( R_EAX, Rm );
1.277 MMU_TRANSLATE_READ( R_EAX );
1.278 ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
1.279 - MEM_READ_BYTE( R_EAX, R_EAX );
1.280 + MEM_READ_BYTE_CACHED( R_EAX, R_EAX, Rm );
1.281 store_reg( R_EAX, Rn );
1.282 sh4_x86.tstate = TSTATE_NONE;
1.283 :}
1.284 @@ -1199,7 +1292,7 @@
1.285 load_reg( R_ECX, Rm );
1.286 ADD_r32_r32( R_ECX, R_EAX );
1.287 MMU_TRANSLATE_READ( R_EAX )
1.288 - MEM_READ_BYTE( R_EAX, R_EAX );
1.289 + MEM_READ_BYTE_CACHED( R_EAX, R_EAX, 0 );
1.290 store_reg( R_EAX, Rn );
1.291 sh4_x86.tstate = TSTATE_NONE;
1.292 :}
1.293 @@ -1208,7 +1301,7 @@
1.294 load_spreg( R_EAX, R_GBR );
1.295 ADD_imm32_r32( disp, R_EAX );
1.296 MMU_TRANSLATE_READ( R_EAX );
1.297 - MEM_READ_BYTE( R_EAX, R_EAX );
1.298 + MEM_READ_BYTE_CACHED( R_EAX, R_EAX, 16 );
1.299 store_reg( R_EAX, 0 );
1.300 sh4_x86.tstate = TSTATE_NONE;
1.301 :}
1.302 @@ -1217,7 +1310,7 @@
1.303 load_reg( R_EAX, Rm );
1.304 ADD_imm32_r32( disp, R_EAX );
1.305 MMU_TRANSLATE_READ( R_EAX );
1.306 - MEM_READ_BYTE( R_EAX, R_EAX );
1.307 + MEM_READ_BYTE_CACHED( R_EAX, R_EAX, Rm );
1.308 store_reg( R_EAX, 0 );
1.309 sh4_x86.tstate = TSTATE_NONE;
1.310 :}
1.311 @@ -1226,8 +1319,7 @@
1.312 load_reg( R_EAX, Rn );
1.313 check_walign32(R_EAX);
1.314 MMU_TRANSLATE_WRITE( R_EAX );
1.315 - load_reg( R_EDX, Rm );
1.316 - MEM_WRITE_LONG( R_EAX, R_EDX );
1.317 + MEM_WRITE_LONG_CACHED( R_EAX, Rm, Rn );
1.318 sh4_x86.tstate = TSTATE_NONE;
1.319 :}
1.320 MOV.L Rm, @-Rn {:
1.321 @@ -1236,9 +1328,8 @@
1.322 ADD_imm8s_r32( -4, R_EAX );
1.323 check_walign32( R_EAX );
1.324 MMU_TRANSLATE_WRITE( R_EAX );
1.325 - load_reg( R_EDX, Rm );
1.326 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.327 - MEM_WRITE_LONG( R_EAX, R_EDX );
1.328 + MEM_WRITE_LONG_CACHED( R_EAX, Rm, Rn );
1.329 sh4_x86.tstate = TSTATE_NONE;
1.330 :}
1.331 MOV.L Rm, @(R0, Rn) {:
1.332 @@ -1248,8 +1339,7 @@
1.333 ADD_r32_r32( R_ECX, R_EAX );
1.334 check_walign32( R_EAX );
1.335 MMU_TRANSLATE_WRITE( R_EAX );
1.336 - load_reg( R_EDX, Rm );
1.337 - MEM_WRITE_LONG( R_EAX, R_EDX );
1.338 + MEM_WRITE_LONG_CACHED( R_EAX, Rm, 0 );
1.339 sh4_x86.tstate = TSTATE_NONE;
1.340 :}
1.341 MOV.L R0, @(disp, GBR) {:
1.342 @@ -1258,8 +1348,7 @@
1.343 ADD_imm32_r32( disp, R_EAX );
1.344 check_walign32( R_EAX );
1.345 MMU_TRANSLATE_WRITE( R_EAX );
1.346 - load_reg( R_EDX, 0 );
1.347 - MEM_WRITE_LONG( R_EAX, R_EDX );
1.348 + MEM_WRITE_LONG_CACHED( R_EAX, 0, 16 );
1.349 sh4_x86.tstate = TSTATE_NONE;
1.350 :}
1.351 MOV.L Rm, @(disp, Rn) {:
1.352 @@ -1268,8 +1357,7 @@
1.353 ADD_imm32_r32( disp, R_EAX );
1.354 check_walign32( R_EAX );
1.355 MMU_TRANSLATE_WRITE( R_EAX );
1.356 - load_reg( R_EDX, Rm );
1.357 - MEM_WRITE_LONG( R_EAX, R_EDX );
1.358 + MEM_WRITE_LONG_CACHED( R_EAX, Rm, Rn );
1.359 sh4_x86.tstate = TSTATE_NONE;
1.360 :}
1.361 MOV.L @Rm, Rn {:
1.362 @@ -1277,7 +1365,7 @@
1.363 load_reg( R_EAX, Rm );
1.364 check_ralign32( R_EAX );
1.365 MMU_TRANSLATE_READ( R_EAX );
1.366 - MEM_READ_LONG( R_EAX, R_EAX );
1.367 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.368 store_reg( R_EAX, Rn );
1.369 sh4_x86.tstate = TSTATE_NONE;
1.370 :}
1.371 @@ -1287,7 +1375,7 @@
1.372 check_ralign32( R_EAX );
1.373 MMU_TRANSLATE_READ( R_EAX );
1.374 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.375 - MEM_READ_LONG( R_EAX, R_EAX );
1.376 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.377 store_reg( R_EAX, Rn );
1.378 sh4_x86.tstate = TSTATE_NONE;
1.379 :}
1.380 @@ -1298,7 +1386,7 @@
1.381 ADD_r32_r32( R_ECX, R_EAX );
1.382 check_ralign32( R_EAX );
1.383 MMU_TRANSLATE_READ( R_EAX );
1.384 - MEM_READ_LONG( R_EAX, R_EAX );
1.385 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, 0 );
1.386 store_reg( R_EAX, Rn );
1.387 sh4_x86.tstate = TSTATE_NONE;
1.388 :}
1.389 @@ -1308,7 +1396,7 @@
1.390 ADD_imm32_r32( disp, R_EAX );
1.391 check_ralign32( R_EAX );
1.392 MMU_TRANSLATE_READ( R_EAX );
1.393 - MEM_READ_LONG( R_EAX, R_EAX );
1.394 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, 16 );
1.395 store_reg( R_EAX, 0 );
1.396 sh4_x86.tstate = TSTATE_NONE;
1.397 :}
1.398 @@ -1337,7 +1425,7 @@
1.399 load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
1.400 ADD_sh4r_r32( R_PC, R_EAX );
1.401 MMU_TRANSLATE_READ( R_EAX );
1.402 - MEM_READ_LONG( R_EAX, R_EAX );
1.403 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, 16 );
1.404 sh4_x86.tstate = TSTATE_NONE;
1.405 }
1.406 store_reg( R_EAX, Rn );
1.407 @@ -1349,7 +1437,7 @@
1.408 ADD_imm8s_r32( disp, R_EAX );
1.409 check_ralign32( R_EAX );
1.410 MMU_TRANSLATE_READ( R_EAX );
1.411 - MEM_READ_LONG( R_EAX, R_EAX );
1.412 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.413 store_reg( R_EAX, Rn );
1.414 sh4_x86.tstate = TSTATE_NONE;
1.415 :}
1.416 @@ -1358,8 +1446,7 @@
1.417 load_reg( R_EAX, Rn );
1.418 check_walign16( R_EAX );
1.419 MMU_TRANSLATE_WRITE( R_EAX )
1.420 - load_reg( R_EDX, Rm );
1.421 - MEM_WRITE_WORD( R_EAX, R_EDX );
1.422 + MEM_WRITE_WORD_CACHED( R_EAX, Rm, Rn );
1.423 sh4_x86.tstate = TSTATE_NONE;
1.424 :}
1.425 MOV.W Rm, @-Rn {:
1.426 @@ -1368,9 +1455,8 @@
1.427 ADD_imm8s_r32( -2, R_EAX );
1.428 check_walign16( R_EAX );
1.429 MMU_TRANSLATE_WRITE( R_EAX );
1.430 - load_reg( R_EDX, Rm );
1.431 ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
1.432 - MEM_WRITE_WORD( R_EAX, R_EDX );
1.433 + MEM_WRITE_WORD_CACHED( R_EAX, Rm, Rn );
1.434 sh4_x86.tstate = TSTATE_NONE;
1.435 :}
1.436 MOV.W Rm, @(R0, Rn) {:
1.437 @@ -1380,8 +1466,7 @@
1.438 ADD_r32_r32( R_ECX, R_EAX );
1.439 check_walign16( R_EAX );
1.440 MMU_TRANSLATE_WRITE( R_EAX );
1.441 - load_reg( R_EDX, Rm );
1.442 - MEM_WRITE_WORD( R_EAX, R_EDX );
1.443 + MEM_WRITE_WORD_CACHED( R_EAX, Rm, 0 );
1.444 sh4_x86.tstate = TSTATE_NONE;
1.445 :}
1.446 MOV.W R0, @(disp, GBR) {:
1.447 @@ -1390,8 +1475,7 @@
1.448 ADD_imm32_r32( disp, R_EAX );
1.449 check_walign16( R_EAX );
1.450 MMU_TRANSLATE_WRITE( R_EAX );
1.451 - load_reg( R_EDX, 0 );
1.452 - MEM_WRITE_WORD( R_EAX, R_EDX );
1.453 + MEM_WRITE_WORD_CACHED( R_EAX, 0, 16 );
1.454 sh4_x86.tstate = TSTATE_NONE;
1.455 :}
1.456 MOV.W R0, @(disp, Rn) {:
1.457 @@ -1400,8 +1484,7 @@
1.458 ADD_imm32_r32( disp, R_EAX );
1.459 check_walign16( R_EAX );
1.460 MMU_TRANSLATE_WRITE( R_EAX );
1.461 - load_reg( R_EDX, 0 );
1.462 - MEM_WRITE_WORD( R_EAX, R_EDX );
1.463 + MEM_WRITE_WORD_CACHED( R_EAX, 0, Rn );
1.464 sh4_x86.tstate = TSTATE_NONE;
1.465 :}
1.466 MOV.W @Rm, Rn {:
1.467 @@ -1409,7 +1492,7 @@
1.468 load_reg( R_EAX, Rm );
1.469 check_ralign16( R_EAX );
1.470 MMU_TRANSLATE_READ( R_EAX );
1.471 - MEM_READ_WORD( R_EAX, R_EAX );
1.472 + MEM_READ_WORD_CACHED( R_EAX, R_EAX, Rm );
1.473 store_reg( R_EAX, Rn );
1.474 sh4_x86.tstate = TSTATE_NONE;
1.475 :}
1.476 @@ -1419,7 +1502,7 @@
1.477 check_ralign16( R_EAX );
1.478 MMU_TRANSLATE_READ( R_EAX );
1.479 ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
1.480 - MEM_READ_WORD( R_EAX, R_EAX );
1.481 + MEM_READ_WORD_CACHED( R_EAX, R_EAX, Rm );
1.482 store_reg( R_EAX, Rn );
1.483 sh4_x86.tstate = TSTATE_NONE;
1.484 :}
1.485 @@ -1430,7 +1513,7 @@
1.486 ADD_r32_r32( R_ECX, R_EAX );
1.487 check_ralign16( R_EAX );
1.488 MMU_TRANSLATE_READ( R_EAX );
1.489 - MEM_READ_WORD( R_EAX, R_EAX );
1.490 + MEM_READ_WORD_CACHED( R_EAX, R_EAX, 0 );
1.491 store_reg( R_EAX, Rn );
1.492 sh4_x86.tstate = TSTATE_NONE;
1.493 :}
1.494 @@ -1440,7 +1523,7 @@
1.495 ADD_imm32_r32( disp, R_EAX );
1.496 check_ralign16( R_EAX );
1.497 MMU_TRANSLATE_READ( R_EAX );
1.498 - MEM_READ_WORD( R_EAX, R_EAX );
1.499 + MEM_READ_WORD_CACHED( R_EAX, R_EAX, 16 );
1.500 store_reg( R_EAX, 0 );
1.501 sh4_x86.tstate = TSTATE_NONE;
1.502 :}
1.503 @@ -1471,7 +1554,7 @@
1.504 ADD_imm32_r32( disp, R_EAX );
1.505 check_ralign16( R_EAX );
1.506 MMU_TRANSLATE_READ( R_EAX );
1.507 - MEM_READ_WORD( R_EAX, R_EAX );
1.508 + MEM_READ_WORD_CACHED( R_EAX, R_EAX, Rm );
1.509 store_reg( R_EAX, 0 );
1.510 sh4_x86.tstate = TSTATE_NONE;
1.511 :}
1.512 @@ -1491,8 +1574,7 @@
1.513 load_reg( R_EAX, Rn );
1.514 check_walign32( R_EAX );
1.515 MMU_TRANSLATE_WRITE( R_EAX );
1.516 - load_reg( R_EDX, 0 );
1.517 - MEM_WRITE_LONG( R_EAX, R_EDX );
1.518 + MEM_WRITE_LONG_CACHED( R_EAX, 0, Rn );
1.519 sh4_x86.tstate = TSTATE_NONE;
1.520 :}
1.521
1.522 @@ -1842,14 +1924,11 @@
1.523 if( sh4_x86.double_size ) {
1.524 check_walign64( R_EAX );
1.525 MMU_TRANSLATE_WRITE( R_EAX );
1.526 - load_dr0( R_EDX, FRm );
1.527 - load_dr1( R_ECX, FRm );
1.528 - MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );
1.529 + MEM_WRITE_DOUBLE_CACHED( R_EAX, FRm, Rn );
1.530 } else {
1.531 check_walign32( R_EAX );
1.532 MMU_TRANSLATE_WRITE( R_EAX );
1.533 - load_fr( R_EDX, FRm );
1.534 - MEM_WRITE_LONG( R_EAX, R_EDX );
1.535 + MEM_WRITE_FLOAT_CACHED( R_EAX, FRm, Rn );
1.536 }
1.537 sh4_x86.tstate = TSTATE_NONE;
1.538 :}
1.539 @@ -1860,13 +1939,13 @@
1.540 if( sh4_x86.double_size ) {
1.541 check_ralign64( R_EAX );
1.542 MMU_TRANSLATE_READ( R_EAX );
1.543 - MEM_READ_DOUBLE( R_EAX, R_EDX, R_EAX );
1.544 + MEM_READ_DOUBLE_CACHED( R_EAX, R_EDX, R_EAX, Rm );
1.545 store_dr0( R_EDX, FRn );
1.546 store_dr1( R_EAX, FRn );
1.547 } else {
1.548 check_ralign32( R_EAX );
1.549 MMU_TRANSLATE_READ( R_EAX );
1.550 - MEM_READ_LONG( R_EAX, R_EAX );
1.551 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.552 store_fr( R_EAX, FRn );
1.553 }
1.554 sh4_x86.tstate = TSTATE_NONE;
1.555 @@ -1877,19 +1956,16 @@
1.556 load_reg( R_EAX, Rn );
1.557 if( sh4_x86.double_size ) {
1.558 check_walign64( R_EAX );
1.559 - ADD_imm8s_r32(-8,R_EAX);
1.560 + LEA_r32disp8_r32( R_EAX, -8, R_EAX );
1.561 MMU_TRANSLATE_WRITE( R_EAX );
1.562 - load_dr0( R_EDX, FRm );
1.563 - load_dr1( R_ECX, FRm );
1.564 ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
1.565 - MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );
1.566 + MEM_WRITE_DOUBLE_CACHED( R_EAX, FRm, Rn );
1.567 } else {
1.568 check_walign32( R_EAX );
1.569 - ADD_imm8s_r32( -4, R_EAX );
1.570 + LEA_r32disp8_r32( R_EAX, -4, R_EAX );
1.571 MMU_TRANSLATE_WRITE( R_EAX );
1.572 - load_fr( R_EDX, FRm );
1.573 ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
1.574 - MEM_WRITE_LONG( R_EAX, R_EDX );
1.575 + MEM_WRITE_FLOAT_CACHED( R_EAX, FRm, Rn );
1.576 }
1.577 sh4_x86.tstate = TSTATE_NONE;
1.578 :}
1.579 @@ -1901,14 +1977,14 @@
1.580 check_ralign64( R_EAX );
1.581 MMU_TRANSLATE_READ( R_EAX );
1.582 ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
1.583 - MEM_READ_DOUBLE( R_EAX, R_EDX, R_EAX );
1.584 + MEM_READ_DOUBLE_CACHED( R_EAX, R_EDX, R_EAX, Rm );
1.585 store_dr0( R_EDX, FRn );
1.586 store_dr1( R_EAX, FRn );
1.587 } else {
1.588 check_ralign32( R_EAX );
1.589 MMU_TRANSLATE_READ( R_EAX );
1.590 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.591 - MEM_READ_LONG( R_EAX, R_EAX );
1.592 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.593 store_fr( R_EAX, FRn );
1.594 }
1.595 sh4_x86.tstate = TSTATE_NONE;
1.596 @@ -1921,14 +1997,11 @@
1.597 if( sh4_x86.double_size ) {
1.598 check_walign64( R_EAX );
1.599 MMU_TRANSLATE_WRITE( R_EAX );
1.600 - load_dr0( R_EDX, FRm );
1.601 - load_dr1( R_ECX, FRm );
1.602 - MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );
1.603 + MEM_WRITE_DOUBLE_CACHED( R_EAX, FRm, 0 );
1.604 } else {
1.605 check_walign32( R_EAX );
1.606 MMU_TRANSLATE_WRITE( R_EAX );
1.607 - load_fr( R_EDX, FRm );
1.608 - MEM_WRITE_LONG( R_EAX, R_EDX ); // 12
1.609 + MEM_WRITE_FLOAT_CACHED( R_EAX, FRm, 0 );
1.610 }
1.611 sh4_x86.tstate = TSTATE_NONE;
1.612 :}
1.613 @@ -1940,13 +2013,13 @@
1.614 if( sh4_x86.double_size ) {
1.615 check_ralign64( R_EAX );
1.616 MMU_TRANSLATE_READ( R_EAX );
1.617 - MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
1.618 + MEM_READ_DOUBLE_CACHED( R_EAX, R_ECX, R_EAX, 0 );
1.619 store_dr0( R_ECX, FRn );
1.620 store_dr1( R_EAX, FRn );
1.621 } else {
1.622 check_ralign32( R_EAX );
1.623 MMU_TRANSLATE_READ( R_EAX );
1.624 - MEM_READ_LONG( R_EAX, R_EAX );
1.625 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, 0 );
1.626 store_fr( R_EAX, FRn );
1.627 }
1.628 sh4_x86.tstate = TSTATE_NONE;
1.629 @@ -2363,7 +2436,7 @@
1.630 check_ralign32( R_EAX );
1.631 MMU_TRANSLATE_READ( R_EAX );
1.632 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.633 - MEM_READ_LONG( R_EAX, R_EAX );
1.634 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.635 store_spreg( R_EAX, R_GBR );
1.636 sh4_x86.tstate = TSTATE_NONE;
1.637 :}
1.638 @@ -2377,7 +2450,7 @@
1.639 check_ralign32( R_EAX );
1.640 MMU_TRANSLATE_READ( R_EAX );
1.641 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.642 - MEM_READ_LONG( R_EAX, R_EAX );
1.643 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.644 call_func1( sh4_write_sr, R_EAX );
1.645 sh4_x86.priv_checked = FALSE;
1.646 sh4_x86.fpuen_checked = FALSE;
1.647 @@ -2391,7 +2464,7 @@
1.648 check_ralign32( R_EAX );
1.649 MMU_TRANSLATE_READ( R_EAX );
1.650 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.651 - MEM_READ_LONG( R_EAX, R_EAX );
1.652 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.653 store_spreg( R_EAX, R_VBR );
1.654 sh4_x86.tstate = TSTATE_NONE;
1.655 :}
1.656 @@ -2402,7 +2475,7 @@
1.657 check_ralign32( R_EAX );
1.658 MMU_TRANSLATE_READ( R_EAX );
1.659 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.660 - MEM_READ_LONG( R_EAX, R_EAX );
1.661 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.662 store_spreg( R_EAX, R_SSR );
1.663 sh4_x86.tstate = TSTATE_NONE;
1.664 :}
1.665 @@ -2413,7 +2486,7 @@
1.666 check_ralign32( R_EAX );
1.667 MMU_TRANSLATE_READ( R_EAX );
1.668 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.669 - MEM_READ_LONG( R_EAX, R_EAX );
1.670 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.671 store_spreg( R_EAX, R_SGR );
1.672 sh4_x86.tstate = TSTATE_NONE;
1.673 :}
1.674 @@ -2424,7 +2497,7 @@
1.675 check_ralign32( R_EAX );
1.676 MMU_TRANSLATE_READ( R_EAX );
1.677 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.678 - MEM_READ_LONG( R_EAX, R_EAX );
1.679 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.680 store_spreg( R_EAX, R_SPC );
1.681 sh4_x86.tstate = TSTATE_NONE;
1.682 :}
1.683 @@ -2435,7 +2508,7 @@
1.684 check_ralign32( R_EAX );
1.685 MMU_TRANSLATE_READ( R_EAX );
1.686 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.687 - MEM_READ_LONG( R_EAX, R_EAX );
1.688 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.689 store_spreg( R_EAX, R_DBR );
1.690 sh4_x86.tstate = TSTATE_NONE;
1.691 :}
1.692 @@ -2446,7 +2519,7 @@
1.693 check_ralign32( R_EAX );
1.694 MMU_TRANSLATE_READ( R_EAX );
1.695 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.696 - MEM_READ_LONG( R_EAX, R_EAX );
1.697 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.698 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
1.699 sh4_x86.tstate = TSTATE_NONE;
1.700 :}
1.701 @@ -2465,7 +2538,7 @@
1.702 check_ralign32( R_EAX );
1.703 MMU_TRANSLATE_READ( R_EAX );
1.704 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.705 - MEM_READ_LONG( R_EAX, R_EAX );
1.706 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.707 call_func1( sh4_write_fpscr, R_EAX );
1.708 sh4_x86.tstate = TSTATE_NONE;
1.709 return 2;
1.710 @@ -2483,7 +2556,7 @@
1.711 check_ralign32( R_EAX );
1.712 MMU_TRANSLATE_READ( R_EAX );
1.713 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.714 - MEM_READ_LONG( R_EAX, R_EAX );
1.715 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.716 store_spreg( R_EAX, R_FPUL );
1.717 sh4_x86.tstate = TSTATE_NONE;
1.718 :}
1.719 @@ -2498,7 +2571,7 @@
1.720 check_ralign32( R_EAX );
1.721 MMU_TRANSLATE_READ( R_EAX );
1.722 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.723 - MEM_READ_LONG( R_EAX, R_EAX );
1.724 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.725 store_spreg( R_EAX, R_MACH );
1.726 sh4_x86.tstate = TSTATE_NONE;
1.727 :}
1.728 @@ -2513,7 +2586,7 @@
1.729 check_ralign32( R_EAX );
1.730 MMU_TRANSLATE_READ( R_EAX );
1.731 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.732 - MEM_READ_LONG( R_EAX, R_EAX );
1.733 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.734 store_spreg( R_EAX, R_MACL );
1.735 sh4_x86.tstate = TSTATE_NONE;
1.736 :}
1.737 @@ -2528,7 +2601,7 @@
1.738 check_ralign32( R_EAX );
1.739 MMU_TRANSLATE_READ( R_EAX );
1.740 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.741 - MEM_READ_LONG( R_EAX, R_EAX );
1.742 + MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.743 store_spreg( R_EAX, R_PR );
1.744 sh4_x86.tstate = TSTATE_NONE;
1.745 :}
1.746 @@ -2632,12 +2705,11 @@
1.747 check_walign32( R_EAX );
1.748 ADD_imm8s_r32( -4, R_EAX );
1.749 MMU_TRANSLATE_WRITE( R_EAX );
1.750 - MOV_r32_esp8( R_EAX, 0 );
1.751 + MOV_r32_r32( R_EAX, R_EBX );
1.752 call_func0( sh4_read_sr );
1.753 MOV_r32_r32( R_EAX, R_EDX );
1.754 - MOV_esp8_r32( 0, R_EAX );
1.755 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.756 - MEM_WRITE_LONG( R_EAX, R_EDX );
1.757 + MEM_WRITE_LONG( R_EBX, R_EDX );
1.758 sh4_x86.tstate = TSTATE_NONE;
1.759 :}
1.760 STC.L VBR, @-Rn {:
1.761 @@ -2647,9 +2719,8 @@
1.762 check_walign32( R_EAX );
1.763 ADD_imm8s_r32( -4, R_EAX );
1.764 MMU_TRANSLATE_WRITE( R_EAX );
1.765 - load_spreg( R_EDX, R_VBR );
1.766 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.767 - MEM_WRITE_LONG( R_EAX, R_EDX );
1.768 + MEM_WRITE_LONG_CACHED_SP( R_EAX, R_VBR, Rn );
1.769 sh4_x86.tstate = TSTATE_NONE;
1.770 :}
1.771 STC.L SSR, @-Rn {:
1.772 @@ -2659,9 +2730,8 @@
1.773 check_walign32( R_EAX );
1.774 ADD_imm8s_r32( -4, R_EAX );
1.775 MMU_TRANSLATE_WRITE( R_EAX );
1.776 - load_spreg( R_EDX, R_SSR );
1.777 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.778 - MEM_WRITE_LONG( R_EAX, R_EDX );
1.779 + MEM_WRITE_LONG_CACHED_SP( R_EAX, R_SSR, Rn );
1.780 sh4_x86.tstate = TSTATE_NONE;
1.781 :}
1.782 STC.L SPC, @-Rn {:
1.783 @@ -2671,9 +2741,8 @@
1.784 check_walign32( R_EAX );
1.785 ADD_imm8s_r32( -4, R_EAX );
1.786 MMU_TRANSLATE_WRITE( R_EAX );
1.787 - load_spreg( R_EDX, R_SPC );
1.788 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.789 - MEM_WRITE_LONG( R_EAX, R_EDX );
1.790 + MEM_WRITE_LONG_CACHED_SP( R_EAX, R_SPC, Rn );
1.791 sh4_x86.tstate = TSTATE_NONE;
1.792 :}
1.793 STC.L SGR, @-Rn {:
1.794 @@ -2683,9 +2752,8 @@
1.795 check_walign32( R_EAX );
1.796 ADD_imm8s_r32( -4, R_EAX );
1.797 MMU_TRANSLATE_WRITE( R_EAX );
1.798 - load_spreg( R_EDX, R_SGR );
1.799 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.800 - MEM_WRITE_LONG( R_EAX, R_EDX );
1.801 + MEM_WRITE_LONG_CACHED_SP( R_EAX, R_SGR, Rn );
1.802 sh4_x86.tstate = TSTATE_NONE;
1.803 :}
1.804 STC.L DBR, @-Rn {:
1.805 @@ -2695,9 +2763,8 @@
1.806 check_walign32( R_EAX );
1.807 ADD_imm8s_r32( -4, R_EAX );
1.808 MMU_TRANSLATE_WRITE( R_EAX );
1.809 - load_spreg( R_EDX, R_DBR );
1.810 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.811 - MEM_WRITE_LONG( R_EAX, R_EDX );
1.812 + MEM_WRITE_LONG_CACHED_SP( R_EAX, R_DBR, Rn );
1.813 sh4_x86.tstate = TSTATE_NONE;
1.814 :}
1.815 STC.L Rm_BANK, @-Rn {:
1.816 @@ -2707,9 +2774,8 @@
1.817 check_walign32( R_EAX );
1.818 ADD_imm8s_r32( -4, R_EAX );
1.819 MMU_TRANSLATE_WRITE( R_EAX );
1.820 - load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
1.821 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.822 - MEM_WRITE_LONG( R_EAX, R_EDX );
1.823 + MEM_WRITE_LONG_CACHED_SP( R_EAX, REG_OFFSET(r_bank[Rm_BANK]), Rn );
1.824 sh4_x86.tstate = TSTATE_NONE;
1.825 :}
1.826 STC.L GBR, @-Rn {:
1.827 @@ -2718,9 +2784,8 @@
1.828 check_walign32( R_EAX );
1.829 ADD_imm8s_r32( -4, R_EAX );
1.830 MMU_TRANSLATE_WRITE( R_EAX );
1.831 - load_spreg( R_EDX, R_GBR );
1.832 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.833 - MEM_WRITE_LONG( R_EAX, R_EDX );
1.834 + MEM_WRITE_LONG_CACHED_SP( R_EAX, R_GBR, Rn );
1.835 sh4_x86.tstate = TSTATE_NONE;
1.836 :}
1.837 STS FPSCR, Rn {:
1.838 @@ -2736,9 +2801,8 @@
1.839 check_walign32( R_EAX );
1.840 ADD_imm8s_r32( -4, R_EAX );
1.841 MMU_TRANSLATE_WRITE( R_EAX );
1.842 - load_spreg( R_EDX, R_FPSCR );
1.843 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.844 - MEM_WRITE_LONG( R_EAX, R_EDX );
1.845 + MEM_WRITE_LONG_CACHED_SP( R_EAX, R_FPSCR, Rn );
1.846 sh4_x86.tstate = TSTATE_NONE;
1.847 :}
1.848 STS FPUL, Rn {:
1.849 @@ -2754,9 +2818,8 @@
1.850 check_walign32( R_EAX );
1.851 ADD_imm8s_r32( -4, R_EAX );
1.852 MMU_TRANSLATE_WRITE( R_EAX );
1.853 - load_spreg( R_EDX, R_FPUL );
1.854 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.855 - MEM_WRITE_LONG( R_EAX, R_EDX );
1.856 + MEM_WRITE_LONG_CACHED_SP( R_EAX, R_FPUL, Rn );
1.857 sh4_x86.tstate = TSTATE_NONE;
1.858 :}
1.859 STS MACH, Rn {:
1.860 @@ -2770,9 +2833,8 @@
1.861 check_walign32( R_EAX );
1.862 ADD_imm8s_r32( -4, R_EAX );
1.863 MMU_TRANSLATE_WRITE( R_EAX );
1.864 - load_spreg( R_EDX, R_MACH );
1.865 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.866 - MEM_WRITE_LONG( R_EAX, R_EDX );
1.867 + MEM_WRITE_LONG_CACHED_SP( R_EAX, R_MACH, Rn );
1.868 sh4_x86.tstate = TSTATE_NONE;
1.869 :}
1.870 STS MACL, Rn {:
1.871 @@ -2786,9 +2848,8 @@
1.872 check_walign32( R_EAX );
1.873 ADD_imm8s_r32( -4, R_EAX );
1.874 MMU_TRANSLATE_WRITE( R_EAX );
1.875 - load_spreg( R_EDX, R_MACL );
1.876 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.877 - MEM_WRITE_LONG( R_EAX, R_EDX );
1.878 + MEM_WRITE_LONG_CACHED_SP( R_EAX, R_MACL, Rn );
1.879 sh4_x86.tstate = TSTATE_NONE;
1.880 :}
1.881 STS PR, Rn {:
1.882 @@ -2802,9 +2863,8 @@
1.883 check_walign32( R_EAX );
1.884 ADD_imm8s_r32( -4, R_EAX );
1.885 MMU_TRANSLATE_WRITE( R_EAX );
1.886 - load_spreg( R_EDX, R_PR );
1.887 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.888 - MEM_WRITE_LONG( R_EAX, R_EDX );
1.889 + MEM_WRITE_LONG_CACHED_SP( R_EAX, R_PR, Rn );
1.890 sh4_x86.tstate = TSTATE_NONE;
1.891 :}
1.892
.