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lxdream.org :: lxdream/src/sh4/timer.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/timer.c
changeset 929:fd8cb0c82f5f
prev859:b941c703ccd6
next975:007bf7eb944f
author nkeynes
date Sat Dec 20 03:01:40 2008 +0000 (12 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change First pass experiment using cached decoding.
file annotate diff log raw
1.1 --- a/src/sh4/timer.c Fri Sep 26 10:29:10 2008 +0000
1.2 +++ b/src/sh4/timer.c Sat Dec 20 03:01:40 2008 +0000
1.3 @@ -44,9 +44,9 @@
1.4 uint32_t sh4_bus_period = 2* 1000 / SH4_BASE_RATE;
1.5 uint32_t sh4_peripheral_period = 4 * 2000 / SH4_BASE_RATE;
1.6
1.7 -int32_t mmio_region_CPG_read( uint32_t reg )
1.8 +MMIO_REGION_READ_FN( CPG, reg )
1.9 {
1.10 - return MMIO_READ( CPG, reg );
1.11 + return MMIO_READ( CPG, reg&0xFFF );
1.12 }
1.13
1.14 /* CPU + bus dividers (note officially only the first 6 values are valid) */
1.15 @@ -54,11 +54,11 @@
1.16 /* Peripheral clock dividers (only first 5 are officially valid) */
1.17 int pfc_divider[8] = { 2, 3, 4, 6, 8, 8, 8, 8 };
1.18
1.19 -void mmio_region_CPG_write( uint32_t reg, uint32_t val )
1.20 +MMIO_REGION_WRITE_FN( CPG, reg, val )
1.21 {
1.22 uint32_t div;
1.23 uint32_t primary_clock = sh4_input_freq;
1.24 -
1.25 + reg &= 0xFFF;
1.26 switch( reg ) {
1.27 case FRQCR: /* Frequency control */
1.28 if( (val & FRQCR_PLL1EN) == 0 )
1.29 @@ -98,14 +98,14 @@
1.30
1.31 uint32_t rtc_output_period;
1.32
1.33 -int32_t mmio_region_RTC_read( uint32_t reg )
1.34 +MMIO_REGION_READ_FN( RTC, reg )
1.35 {
1.36 - return MMIO_READ( RTC, reg );
1.37 + return MMIO_READ( RTC, reg &0xFFF );
1.38 }
1.39
1.40 -void mmio_region_RTC_write( uint32_t reg, uint32_t val )
1.41 +MMIO_REGION_WRITE_FN( RTC, reg, val )
1.42 {
1.43 - MMIO_WRITE( RTC, reg, val );
1.44 + MMIO_WRITE( RTC, reg &0xFFF, val );
1.45 }
1.46
1.47 /********************************** TMU *************************************/
1.48 @@ -140,22 +140,6 @@
1.49
1.50 static struct TMU_timer TMU_timers[3];
1.51
1.52 -int32_t mmio_region_TMU_read( uint32_t reg )
1.53 -{
1.54 - switch( reg ) {
1.55 - case TCNT0:
1.56 - TMU_count( 0, sh4r.slice_cycle );
1.57 - break;
1.58 - case TCNT1:
1.59 - TMU_count( 1, sh4r.slice_cycle );
1.60 - break;
1.61 - case TCNT2:
1.62 - TMU_count( 2, sh4r.slice_cycle );
1.63 - break;
1.64 - }
1.65 - return MMIO_READ( TMU, reg );
1.66 -}
1.67 -
1.68 void TMU_set_timer_control( int timer, int tcr )
1.69 {
1.70 uint32_t period = 1;
1.71 @@ -261,10 +245,28 @@
1.72 return value;
1.73 }
1.74
1.75 -void mmio_region_TMU_write( uint32_t reg, uint32_t val )
1.76 +MMIO_REGION_READ_FN( TMU, reg )
1.77 +{
1.78 + reg &= 0xFFF;
1.79 + switch( reg ) {
1.80 + case TCNT0:
1.81 + TMU_count( 0, sh4r.slice_cycle );
1.82 + break;
1.83 + case TCNT1:
1.84 + TMU_count( 1, sh4r.slice_cycle );
1.85 + break;
1.86 + case TCNT2:
1.87 + TMU_count( 2, sh4r.slice_cycle );
1.88 + break;
1.89 + }
1.90 + return MMIO_READ( TMU, reg );
1.91 +}
1.92 +
1.93 +MMIO_REGION_WRITE_FN( TMU, reg, val )
1.94 {
1.95 uint32_t oldval;
1.96 int i;
1.97 + reg &= 0xFFF;
1.98 switch( reg ) {
1.99 case TSTR:
1.100 oldval = MMIO_READ( TMU, TSTR );
.