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lxdream.org :: lxdream/src/sh4/sh4xir.in :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4xir.in
changeset 1011:fdd58619b760
prev1006:3a169c224c12
next1012:0b8cc74ac83a
author nkeynes
date Sun Apr 12 07:24:45 2009 +0000 (13 years ago)
branchxlat-refactor
permissions -rw-r--r--
last change Restructure operand types -
rename to forms to avoid conflict for actual data types
temporary operands are now a first class form
remove explicit types for immediates - now implied by opcode
Initial work on promote-source-reg pass
file annotate diff log raw
1.1 --- a/src/sh4/sh4xir.in Tue Apr 07 10:55:03 2009 +0000
1.2 +++ b/src/sh4/sh4xir.in Sun Apr 12 07:24:45 2009 +0000
1.3 @@ -37,11 +37,11 @@
1.4 #define R_Q REG_OFFSET(q)
1.5 #define R_S REG_OFFSET(s)
1.6 #define R_FR(frn) REG_OFFSET(fr[0][(frn)^1])
1.7 -#define R_DR(frn) REG_OFFSET(fr[0][frn])
1.8 +#define R_DR(frn) REG_OFFSET(fr[0][(frn)&0x0E])
1.9 #define R_DRL(f) REG_OFFSET(fr[(f)&1][(f)|0x01])
1.10 #define R_DRH(f) REG_OFFSET(fr[(f)&1][(f)&0x0E])
1.11 #define R_XF(frn) REG_OFFSET(fr[1][(frn)^1])
1.12 -#define R_XD(frn) REG_OFFSET(fr[1][frn^1])
1.13 +#define R_XD(frn) REG_OFFSET(fr[1][(frn)&0x0E])
1.14 #define R_FV(fvn) REG_OFFSET(fr[0][fvn<<2])
1.15 #define R_XMTRX R_XD(0)
1.16 #define R_FPSCR REG_OFFSET(fpscr)
1.17 @@ -72,8 +72,46 @@
1.18 "store_queue", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1.19 "new_pc", "event_pending", "event_type", "delay_slot", "slice_cycle", "bus_cycle", "state", "xlat_mode" };
1.20
1.21 -struct xlat_source_machine sh4_source_machine = { "sH4", &sh4r,
1.22 - sh4_register_names, R_PC, R_NEW_PC, R_T, R_M, R_Q, R_S,
1.23 +static const char *sh4_quad_register_names[] = /* From FR1 to MACH */
1.24 + {"dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
1.25 + "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14",
1.26 + NULL, "mac" };
1.27 +static const char *sh4_vec4_register_names[] = /* From FR1 to XF14 */
1.28 + {"fv0", "fv4", "fv8", "fv12", "xfv0", "xfv4", "xfv8", "xfv12" };
1.29 +
1.30 +static const char *sh4_get_register_name( uint32_t reg, xir_type_t ty )
1.31 +{
1.32 + switch( ty ) {
1.33 + case XTY_LONG:
1.34 + case XTY_FLOAT:
1.35 + if( reg <= R_SH4_MODE ) {
1.36 + return sh4_register_names[reg>>2];
1.37 + }
1.38 + break;
1.39 + case XTY_QUAD:
1.40 + case XTY_DOUBLE:
1.41 + if( reg >= R_DR(0) && reg <= R_MACH ) {
1.42 + return sh4_quad_register_names[(reg-R_DR(0))>>3];
1.43 + }
1.44 + break;
1.45 + case XTY_VEC4F:
1.46 + if( reg >= R_DR(0) && reg <= R_XD(14) ) {
1.47 + return sh4_vec4_register_names[(reg-R_DR(0))>>4];
1.48 + }
1.49 + break;
1.50 + case XTY_MAT16F:
1.51 + if( reg = R_XMTRX ) {
1.52 + return "xmtrx";
1.53 + } else if( reg == R_DR(0) ) {
1.54 + return "mtrx";
1.55 + }
1.56 + }
1.57 + return NULL;
1.58 +}
1.59 +
1.60 +struct xlat_source_machine sh4_source_machine = { "SH4", &sh4r,
1.61 + R_PC, R_NEW_PC, R_T, R_M, R_Q, R_S,
1.62 + sh4_get_register_name,
1.63 sh4_decode_basic_block };
1.64
1.65 /**
1.66 @@ -89,21 +127,55 @@
1.67
1.68 static struct sh4_xir_state sh4_xir;
1.69
1.70 -#define XOP1E( op, arg0 ) do{ \
1.71 - xir_op_t ins = xir_append_op2(xbb, op, SOURCE_REGISTER_OPERAND, arg0, NO_OPERAND, 0); \
1.72 - ins->exc = write_postexc(xbb, (in_delay_slot ? pc-2 : pc) ); \
1.73 - ins->next = xbb->ir_ptr; \
1.74 - xbb->ir_ptr->prev = ins; \
1.75 - } while(0)
1.76 -#define XOP2E( op, arg0, arg1 ) do{ \
1.77 - xir_op_t ins = xir_append_op2(xbb, op, SOURCE_REGISTER_OPERAND, arg0, SOURCE_REGISTER_OPERAND, arg1); \
1.78 - ins->exc = write_postexc(xbb, (in_delay_slot ? pc-2 : pc) ); \
1.79 - ins->exc->prev = ins; \
1.80 - ins->next = xbb->ir_ptr; \
1.81 - xbb->ir_ptr->prev = ins; \
1.82 - } while(0)
1.83 +/**
1.84 + * Create a standard exception-taking stub sub-block - updates SPC, slice_cycle, and exits
1.85 + * @return the first xir_op_t of the exception block.
1.86 + */
1.87 +static inline xir_op_t write_exc( xir_basic_block_t xbb, sh4addr_t pc, int exc_code )
1.88 +{
1.89 + xir_op_t start = xbb->ir_ptr;
1.90 + XOPCALL1I( sh4_raise_exception, exc_code );
1.91 + if( pc != xbb->pc_begin ) {
1.92 + XOP2IS( OP_ADD, pc - xbb->pc_begin, R_SPC );
1.93 + }
1.94 + XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.95 + XOP1S( OP_BR, R_SPC )->next = NULL;
1.96 + start->prev = NULL;
1.97 + return start;
1.98 +}
1.99 +
1.100 +/**
1.101 + * Create an instruction with a standard post-exception stub sub-block (ie
1.102 + * sh4_raise_exception or similar has already been called - update SPC +
1.103 + * slice_cycle and exit).
1.104 + * @return the first xir_op_t of the exception block.
1.105 + */
1.106 +static xir_op_t xir_append_op2_exc( xir_basic_block_t xbb, int op, int arg0form, uint32_t arg0, int arg1form, uint32_t arg1, sh4addr_t pc )
1.107 +{
1.108 + xir_op_t ins = xir_append_op2( xbb, op, arg0form, arg0, arg1form, arg1 );
1.109 + ins->exc = xbb->ir_ptr;
1.110 + ins->exc->prev = ins;
1.111 +
1.112 + if( pc != xbb->pc_begin ) {
1.113 + XOP2IS( OP_ADD, pc - xbb->pc_begin, R_SPC );
1.114 + }
1.115 + XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.116 + XOP1S( OP_BR, R_SPC )->next = NULL;
1.117 +
1.118 + ins->next = xbb->ir_ptr;
1.119 + xbb->ir_ptr->prev = ins;
1.120 + return ins;
1.121 +}
1.122 +
1.123 +#define XOP1SE( op, arg0 ) xir_append_op2_exc( xbb, op, SOURCE_OPERAND, arg0, NO_OPERAND, 0, (in_delay_slot ? pc-2 : pc))
1.124 +#define XOP1TE( op, arg0 ) xir_append_op2_exc( xbb, op, TEMP_OPERAND, arg0, NO_OPERAND, 0, (in_delay_slot ? pc-2 : pc))
1.125 +#define XOP2SSE( op, arg0, arg1 ) xir_append_op2_exc( xbb, op, SOURCE_OPERAND, arg0, SOURCE_OPERAND, arg1, (in_delay_slot ? pc-2 : pc))
1.126 +#define XOP2STE( op, arg0, arg1 ) xir_append_op2_exc( xbb, op, SOURCE_OPERAND, arg0, TEMP_OPERAND, arg1, (in_delay_slot ? pc-2 : pc))
1.127 +#define XOP2TSE( op, arg0, arg1 ) xir_append_op2_exc( xbb, op, TEMP_OPERAND, arg0, SOURCE_OPERAND, arg1, (in_delay_slot ? pc-2 : pc))
1.128 +#define XOP2TTE( op, arg0, arg1 ) xir_append_op2_exc( xbb, op, TEMP_OPERAND, arg0, TEMP_OPERAND, arg1, (in_delay_slot ? pc-2 : pc))
1.129 +
1.130 #define ALIGN(m,r,code) do { \
1.131 - xir_op_t ins = xir_append_op2(xbb, OP_RAISEMNE, INT_IMM_OPERAND, m, SOURCE_REGISTER_OPERAND, r); \
1.132 + xir_op_t ins = xir_append_op2(xbb, OP_RAISEMNE, IMMEDIATE_OPERAND, m, SOURCE_OPERAND, r); \
1.133 ins->exc = write_exc(xbb, (in_delay_slot ? pc-2 : pc), code); \
1.134 ins->exc->prev = ins; \
1.135 ins->next = xbb->ir_ptr; \
1.136 @@ -115,7 +187,7 @@
1.137
1.138 #define UNDEF(ir) if( in_delay_slot ) { SLOTILLEGAL(); return 2; } else { ILLEGAL(); return 2; }
1.139 #define CHECKFPUEN() if( !sh4_xir.fpuen_checked ) { \
1.140 - xir_op_t ins = XOP2I( OP_RAISEMNE, SR_FD, R_SR ); \
1.141 + xir_op_t ins = XOP2IS( OP_RAISEMNE, SR_FD, R_SR ); \
1.142 if( in_delay_slot ) { \
1.143 ins->exc = write_exc(xbb, pc-2, EXC_SLOT_FPU_DISABLED); \
1.144 } else { \
1.145 @@ -138,370 +210,336 @@
1.146 #define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
1.147
1.148 #define EMU_DELAY_SLOT() do { \
1.149 - XOP2I( OP_ADD, (pc+2 - xbb->pc_begin), R_PC ); \
1.150 - XOP2I( OP_MOV, 1, R_DELAY_SLOT ); \
1.151 + XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin), R_PC ); \
1.152 + XOP2IS( OP_MOV, 1, R_DELAY_SLOT ); \
1.153 XOP0( OP_BARRIER ); \
1.154 XOPCALL0( sh4_execute_instruction ); \
1.155 - XOP1( OP_BR, R_PC ); \
1.156 + XOP1S( OP_BR, R_PC ); \
1.157 } while(0)
1.158
1.159
1.160 -/**
1.161 - * Create a standard post-exception stub sub-block (ie sh4_raise_exception or similar has
1.162 - * already been called - update SPC + slice_cycle and exit).
1.163 - * @return the first xir_op_t of the exception block.
1.164 - */
1.165 -static inline xir_op_t write_postexc( xir_basic_block_t xbb, sh4addr_t pc )
1.166 -{
1.167 - xir_op_t start = xbb->ir_ptr;
1.168 - if( pc != xbb->pc_begin ) {
1.169 - XOP2I( OP_ADD, pc - xbb->pc_begin, R_SPC );
1.170 - }
1.171 - XOP2I( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.172 - XOP1( OP_BR, R_SPC )->next = NULL;
1.173 - start->prev = NULL;
1.174 - return start;
1.175 -}
1.176 -
1.177 -/**
1.178 - * Create a standard exception-taking stub sub-block - updates SPC, slice_cycle, and exits
1.179 - * @return the first xir_op_t of the exception block.
1.180 - */
1.181 -static inline xir_op_t write_exc( xir_basic_block_t xbb, sh4addr_t pc, int exc_code )
1.182 -{
1.183 - xir_op_t start = xbb->ir_ptr;
1.184 - XOPCALL1I( sh4_raise_exception, exc_code );
1.185 - if( pc != xbb->pc_begin ) {
1.186 - XOP2I( OP_ADD, pc - xbb->pc_begin, R_SPC );
1.187 - }
1.188 - XOP2I( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.189 - XOP1( OP_BR, R_SPC )->next = NULL;
1.190 - start->prev = NULL;
1.191 - return start;
1.192 -}
1.193 -
1.194 static sh4addr_t sh4_decode_instruction( xir_basic_block_t xbb, sh4addr_t pc, gboolean in_delay_slot )
1.195 {
1.196 assert( IS_IN_ICACHE(pc) );
1.197 uint16_t ir = *(uint16_t *)GET_ICACHE_PTR(pc);
1.198
1.199 %%
1.200 -ADD Rm, Rn {: XOP2( OP_ADD, R_R(Rm), R_R(Rn) ); :}
1.201 -ADD #imm, Rn {: XOP2I( OP_ADD, imm, R_R(Rn) ); :}
1.202 +ADD Rm, Rn {: XOP2SS( OP_ADD, R_R(Rm), R_R(Rn) ); :}
1.203 +ADD #imm, Rn {: XOP2IS( OP_ADD, imm, R_R(Rn) ); :}
1.204 ADDC Rm, Rn {:
1.205 - XOP1CC( OP_LD, CC_C, R_T );
1.206 - XOP2( OP_ADDCS, R_R(Rm), R_R(Rn) );
1.207 - XOP1CC( OP_ST, CC_C, R_T );
1.208 + XOP1SCC( OP_LD, CC_C, R_T );
1.209 + XOP2SS( OP_ADDCS, R_R(Rm), R_R(Rn) );
1.210 + XOP1SCC( OP_ST, CC_C, R_T );
1.211 :}
1.212 -ADDV Rm, Rn {: XOP2( OP_ADDS, R_R(Rm), R_R(Rn) ); XOP1CC( OP_ST, CC_OV, R_T ); :}
1.213 -AND Rm, Rn {: XOP2( OP_AND, R_R(Rm), R_R(Rn) ); :}
1.214 -AND #imm, R0 {: XOP2I( OP_AND, imm, R_R0 ); :}
1.215 -CMP/EQ Rm, Rn {: XOP2( OP_CMP, Rm, R_R(Rn) ); XOP1CC( OP_ST, CC_EQ, R_T ); :}
1.216 -CMP/EQ #imm, R0 {: XOP2I( OP_CMP, imm, R_R0 ); XOP1CC( OP_ST, CC_EQ, R_T ); :}
1.217 -CMP/GE Rm, Rn {: XOP2( OP_CMP, R_R(Rm), R_R(Rn) ); XOP1CC( OP_ST, CC_SGE, R_T ); :}
1.218 -CMP/GT Rm, Rn {: XOP2( OP_CMP, R_R(Rm), R_R(Rn) ); XOP1CC( OP_ST, CC_SGT, R_T ); :}
1.219 -CMP/HI Rm, Rn {: XOP2( OP_CMP, R_R(Rm), R_R(Rn) ); XOP1CC( OP_ST, CC_UGT, R_T ); :}
1.220 -CMP/HS Rm, Rn {: XOP2( OP_CMP, R_R(Rm), R_R(Rn) ); XOP1CC( OP_ST, CC_UGE, R_T ); :}
1.221 -CMP/PL Rn {: XOP2I( OP_CMP, 0, R_R(Rn) ); XOP1CC( OP_ST, CC_SGT, R_T ); :}
1.222 -CMP/PZ Rn {: XOP2I( OP_CMP, 0, R_R(Rn) ); XOP1CC( OP_ST, CC_SGE, R_T ); :}
1.223 -CMP/STR Rm, Rn {: XOP2( OP_CMPSTR, R_R(Rm), R_R(Rn) ); :}
1.224 +ADDV Rm, Rn {: XOP2SS( OP_ADDS, R_R(Rm), R_R(Rn) ); XOP1SCC( OP_ST, CC_OV, R_T ); :}
1.225 +AND Rm, Rn {: XOP2SS( OP_AND, R_R(Rm), R_R(Rn) ); :}
1.226 +AND #imm, R0 {: XOP2IS( OP_AND, imm, R_R0 ); :}
1.227 +CMP/EQ Rm, Rn {: XOP2SS( OP_CMP, Rm, R_R(Rn) ); XOP1SCC( OP_ST, CC_EQ, R_T ); :}
1.228 +CMP/EQ #imm, R0 {: XOP2IS( OP_CMP, imm, R_R0 ); XOP1SCC( OP_ST, CC_EQ, R_T ); :}
1.229 +CMP/GE Rm, Rn {: XOP2SS( OP_CMP, R_R(Rm), R_R(Rn) ); XOP1SCC( OP_ST, CC_SGE, R_T ); :}
1.230 +CMP/GT Rm, Rn {: XOP2SS( OP_CMP, R_R(Rm), R_R(Rn) ); XOP1SCC( OP_ST, CC_SGT, R_T ); :}
1.231 +CMP/HI Rm, Rn {: XOP2SS( OP_CMP, R_R(Rm), R_R(Rn) ); XOP1SCC( OP_ST, CC_UGT, R_T ); :}
1.232 +CMP/HS Rm, Rn {: XOP2SS( OP_CMP, R_R(Rm), R_R(Rn) ); XOP1SCC( OP_ST, CC_UGE, R_T ); :}
1.233 +CMP/PL Rn {: XOP2IS( OP_CMP, 0, R_R(Rn) ); XOP1SCC( OP_ST, CC_SGT, R_T ); :}
1.234 +CMP/PZ Rn {: XOP2IS( OP_CMP, 0, R_R(Rn) ); XOP1SCC( OP_ST, CC_SGE, R_T ); :}
1.235 +CMP/STR Rm, Rn {: XOP2SS( OP_CMPSTR, R_R(Rm), R_R(Rn) ); :}
1.236 DIV0S Rm, Rn {:
1.237 - XOP2( OP_MOV, R_R(Rm), R_M );
1.238 - XOP2I( OP_SLR, 31, R_M );
1.239 - XOP2( OP_MOV, R_R(Rn), R_Q );
1.240 - XOP2I( OP_SLR, 31, R_Q );
1.241 - XOP2( OP_CMP, R_M, R_Q );
1.242 - XOP1CC( OP_ST, CC_NE, R_T );
1.243 + XOP2SS( OP_MOV, R_R(Rm), R_M );
1.244 + XOP2IS( OP_SLR, 31, R_M );
1.245 + XOP2SS( OP_MOV, R_R(Rn), R_Q );
1.246 + XOP2IS( OP_SLR, 31, R_Q );
1.247 + XOP2SS( OP_CMP, R_M, R_Q );
1.248 + XOP1SCC( OP_ST, CC_NE, R_T );
1.249 :}
1.250 DIV0U {:
1.251 - XOP2I( OP_MOV, 0, R_M );
1.252 - XOP2I( OP_MOV, 0, R_Q );
1.253 - XOP2I( OP_MOV, 0, R_T );
1.254 + XOP2IS( OP_MOV, 0, R_M );
1.255 + XOP2IS( OP_MOV, 0, R_Q );
1.256 + XOP2IS( OP_MOV, 0, R_T );
1.257 :}
1.258 -DIV1 Rm, Rn {: XOP2( OP_DIV1, R_R(Rm), R_R(Rn) ); :}
1.259 +DIV1 Rm, Rn {: XOP2SS( OP_DIV1, R_R(Rm), R_R(Rn) ); :}
1.260 DMULS.L Rm, Rn {:
1.261 - XOP2( OP_MOVSX32, R_R(Rm), R_MAC );
1.262 - XOP2( OP_MOVSX32, R_R(Rn), REG_TMP0 );
1.263 - XOP2( OP_MULQ, REG_TMPQ0, R_MAC );
1.264 + XOP2SS( OP_MOVSX32, R_R(Rm), R_MAC );
1.265 + XOP2ST( OP_MOVSX32, R_R(Rn), REG_TMP0 );
1.266 + XOP2TS( OP_MULQ, REG_TMPQ0, R_MAC );
1.267 :}
1.268 DMULU.L Rm, Rn {:
1.269 - XOP2( OP_MOVZX32, R_R(Rm), R_MAC );
1.270 - XOP2( OP_MOVZX32, R_R(Rn), REG_TMP0 ) ;
1.271 - XOP2( OP_MULQ, REG_TMP0, R_MAC );
1.272 + XOP2SS( OP_MOVZX32, R_R(Rm), R_MAC );
1.273 + XOP2ST( OP_MOVZX32, R_R(Rn), REG_TMP0 ) ;
1.274 + XOP2TS( OP_MULQ, REG_TMP0, R_MAC );
1.275 :}
1.276 -DT Rn {: XOP1( OP_DEC, R_R(Rn) ); :}
1.277 -EXTS.B Rm, Rn {: XOP2( OP_MOVSX8, R_R(Rm), R_R(Rn)); :}
1.278 -EXTS.W Rm, Rn {: XOP2( OP_MOVSX16, R_R(Rm), R_R(Rn)); :}
1.279 -EXTU.B Rm, Rn {: XOP2( OP_MOVZX8, R_R(Rm), R_R(Rn)); :}
1.280 -EXTU.W Rm, Rn {: XOP2( OP_MOVZX16, R_R(Rm), R_R(Rn)); :}
1.281 +DT Rn {: XOP1S( OP_DEC, R_R(Rn) ); :}
1.282 +EXTS.B Rm, Rn {: XOP2SS( OP_MOVSX8, R_R(Rm), R_R(Rn)); :}
1.283 +EXTS.W Rm, Rn {: XOP2SS( OP_MOVSX16, R_R(Rm), R_R(Rn)); :}
1.284 +EXTU.B Rm, Rn {: XOP2SS( OP_MOVZX8, R_R(Rm), R_R(Rn)); :}
1.285 +EXTU.W Rm, Rn {: XOP2SS( OP_MOVZX16, R_R(Rm), R_R(Rn)); :}
1.286 MAC.L @Rm+, @Rn+ {:
1.287 RALIGN32(R_R(Rm));
1.288 if( Rm == Rn ) {
1.289 - XOP2E( OP_LOADL, R_R(Rm), REG_TMP0 );
1.290 - XOP2( OP_MOV, R_R(Rm), REG_TMP1 );
1.291 - XOP2I( OP_ADD, 4, REG_TMP1 );
1.292 - XOP2E( OP_LOADL, REG_TMP1, REG_TMP1 );
1.293 - XOP2I( OP_ADD, 8, R_R(Rm) );
1.294 + XOP2STE( OP_LOADL, R_R(Rm), REG_TMP0 );
1.295 + XOP2ST( OP_MOV, R_R(Rm), REG_TMP1 );
1.296 + XOP2IT( OP_ADD, 4, REG_TMP1 );
1.297 + XOP2TTE( OP_LOADL, REG_TMP1, REG_TMP1 );
1.298 + XOP2IS( OP_ADD, 8, R_R(Rm) );
1.299 } else {
1.300 RALIGN32(R_R(Rn));
1.301 - XOP2E( OP_LOADL, R_R(Rm), REG_TMP0 );
1.302 - XOP2E( OP_LOADL, R_R(Rn), REG_TMP1 );
1.303 - XOP2I( OP_ADD, 4, R_R(Rm) );
1.304 - XOP2I( OP_ADD, 4, R_R(Rn) );
1.305 + XOP2STE( OP_LOADL, R_R(Rm), REG_TMP0 );
1.306 + XOP2STE( OP_LOADL, R_R(Rn), REG_TMP1 );
1.307 + XOP2IS( OP_ADD, 4, R_R(Rm) );
1.308 + XOP2IS( OP_ADD, 4, R_R(Rn) );
1.309 }
1.310 - XOP2( OP_MOVSX32, REG_TMP0, REG_TMPQ0 );
1.311 - XOP2( OP_MOVSX32, REG_TMP1, REG_TMPQ1 );
1.312 - XOP2( OP_MULQ, REG_TMPQ0, REG_TMPQ1 );
1.313 - XOP2( OP_ADDQSAT48, REG_TMPQ1, R_MAC );
1.314 + XOP2TT( OP_MOVSX32, REG_TMP0, REG_TMPQ0 );
1.315 + XOP2TT( OP_MOVSX32, REG_TMP1, REG_TMPQ1 );
1.316 + XOP2TT( OP_MULQ, REG_TMPQ0, REG_TMPQ1 );
1.317 + XOP2TS( OP_ADDQSAT48, REG_TMPQ1, R_MAC );
1.318 :}
1.319 MAC.W @Rm+, @Rn+ {:
1.320 RALIGN32(R_R(Rm));
1.321 if( Rm == Rn ) {
1.322 - XOP2E( OP_LOADW, R_R(Rm), REG_TMP0 );
1.323 - XOP2( OP_MOV, R_R(Rm), REG_TMP1 );
1.324 - XOP2I( OP_ADD, 2, REG_TMP1 );
1.325 - XOP2E( OP_LOADW, REG_TMP1, REG_TMP1 );
1.326 - XOP2I( OP_ADD, 4, R_R(Rm) );
1.327 + XOP2STE( OP_LOADW, R_R(Rm), REG_TMP0 );
1.328 + XOP2ST( OP_MOV, R_R(Rm), REG_TMP1 );
1.329 + XOP2IT( OP_ADD, 2, REG_TMP1 );
1.330 + XOP2TTE( OP_LOADW, REG_TMP1, REG_TMP1 );
1.331 + XOP2IS( OP_ADD, 4, R_R(Rm) );
1.332 } else {
1.333 RALIGN32(Rn);
1.334 - XOP2E( OP_LOADW, R_R(Rm), REG_TMP0 );
1.335 - XOP2E( OP_LOADW, R_R(Rn), REG_TMP1 );
1.336 - XOP2I( OP_ADD, 2, R_R(Rm) );
1.337 - XOP2I( OP_ADD, 2, R_R(Rn) );
1.338 + XOP2STE( OP_LOADW, R_R(Rm), REG_TMP0 );
1.339 + XOP2STE( OP_LOADW, R_R(Rn), REG_TMP1 );
1.340 + XOP2IS( OP_ADD, 2, R_R(Rm) );
1.341 + XOP2IS( OP_ADD, 2, R_R(Rn) );
1.342 }
1.343 - XOP2( OP_MOVSX32, REG_TMP0, REG_TMPQ0 );
1.344 - XOP2( OP_MOVSX32, REG_TMP1, REG_TMPQ1 );
1.345 - XOP2( OP_MULQ, REG_TMPQ0, REG_TMPQ1 );
1.346 - XOP2( OP_ADDQSAT32, REG_TMPQ1, R_MAC );
1.347 + XOP2TT( OP_MOVSX32, REG_TMP0, REG_TMPQ0 );
1.348 + XOP2TT( OP_MOVSX32, REG_TMP1, REG_TMPQ1 );
1.349 + XOP2TT( OP_MULQ, REG_TMPQ0, REG_TMPQ1 );
1.350 + XOP2TS( OP_ADDQSAT32, REG_TMPQ1, R_MAC );
1.351 :}
1.352 -MOVT Rn {: XOP2( OP_MOV, R_R(Rn), R_T ); :}
1.353 +MOVT Rn {: XOP2SS( OP_MOV, R_R(Rn), R_T ); :}
1.354 MUL.L Rm, Rn {:
1.355 - XOP2( OP_MOV, R_R(Rm), R_MACL );
1.356 - XOP2( OP_MUL, R_R(Rn), R_MACL );
1.357 + XOP2SS( OP_MOV, R_R(Rm), R_MACL );
1.358 + XOP2SS( OP_MUL, R_R(Rn), R_MACL );
1.359 :}
1.360 MULS.W Rm, Rn {:
1.361 - XOP2( OP_MOVSX16, R_R(Rm), REG_TMP0 );
1.362 - XOP2( OP_MOVSX16, R_R(Rn), R_MACL );
1.363 - XOP2( OP_MUL, REG_TMP0, R_MACL );
1.364 + XOP2ST( OP_MOVSX16, R_R(Rm), REG_TMP0 );
1.365 + XOP2SS( OP_MOVSX16, R_R(Rn), R_MACL );
1.366 + XOP2TS( OP_MUL, REG_TMP0, R_MACL );
1.367 :}
1.368 MULU.W Rm, Rn {:
1.369 - XOP2( OP_MOVZX16, R_R(Rm), REG_TMP0 );
1.370 - XOP2( OP_MOVZX16, R_R(Rn), R_MACL );
1.371 - XOP2( OP_MUL, REG_TMP0, R_MACL );
1.372 + XOP2ST( OP_MOVZX16, R_R(Rm), REG_TMP0 );
1.373 + XOP2SS( OP_MOVZX16, R_R(Rn), R_MACL );
1.374 + XOP2TS( OP_MUL, REG_TMP0, R_MACL );
1.375 :}
1.376 NEG Rm, Rn {:
1.377 - XOP2( OP_NEG, R_R(Rm), R_R(Rn) );
1.378 + XOP2SS( OP_NEG, R_R(Rm), R_R(Rn) );
1.379 :}
1.380 NEGC Rm, Rn {:
1.381 - XOP1CC( OP_LD, CC_C, R_T );
1.382 + XOP1SCC( OP_LD, CC_C, R_T );
1.383 if( Rm == Rn ) {
1.384 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.385 - XOP2I(OP_MOV, 0, R_R(Rn) );
1.386 - XOP2( OP_SUBBS, REG_TMP0, R_R(Rn) );
1.387 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.388 + XOP2IS(OP_MOV, 0, R_R(Rn) );
1.389 + XOP2TS( OP_SUBBS, REG_TMP0, R_R(Rn) );
1.390 } else {
1.391 - XOP2I(OP_MOV, 0, R_R(Rn) );
1.392 - XOP2( OP_SUBBS, R_R(Rm), R_R(Rn) );
1.393 + XOP2IS(OP_MOV, 0, R_R(Rn) );
1.394 + XOP2SS( OP_SUBBS, R_R(Rm), R_R(Rn) );
1.395 }
1.396 - XOP1CC( OP_ST, CC_C, R_T );
1.397 + XOP1SCC( OP_ST, CC_C, R_T );
1.398 :}
1.399 NOT Rm, Rn {:
1.400 - XOP2( OP_NOT, R_R(Rm), R_R(Rn) );
1.401 + XOP2SS( OP_NOT, R_R(Rm), R_R(Rn) );
1.402 :}
1.403 -OR Rm, Rn {: XOP2( OP_OR, R_R(Rm), R_R(Rn) ); :}
1.404 -OR #imm, R0 {: XOP2I( OP_OR, imm, R_R0 ); :}
1.405 -ROTCL Rn {: XOP1CC( OP_LD, CC_C, R_T ); XOP2I( OP_RCL, 1, R_R(Rn) ); XOP1CC( OP_ST, CC_C, R_T); :}
1.406 -ROTCR Rn {: XOP1CC( OP_LD, CC_C, R_T ); XOP2I( OP_RCR, 1, R_R(Rn) ); XOP1CC( OP_ST, CC_C, R_T); :}
1.407 -ROTL Rn {: XOP2I( OP_ROL, 1, R_R(Rn) ); :}
1.408 -ROTR Rn {: XOP2I( OP_ROR, 1, R_R(Rn) ); :}
1.409 -SHAD Rm, Rn {: XOP2( OP_SHAD, R_R(Rm), R_R(Rn) ); :}
1.410 -SHLD Rm, Rn {: XOP2( OP_SHLD, R_R(Rm), R_R(Rn) ); :}
1.411 -SHAL Rn {: XOP2I( OP_SLLS, 1, R_R(Rn) ); XOP1CC( OP_ST, CC_C, R_T); :}
1.412 -SHAR Rn {: XOP2I( OP_SARS, 1, R_R(Rn) ); XOP1CC( OP_ST, CC_C, R_T); :}
1.413 -SHLL Rn {: XOP2I( OP_SLLS, 1, R_R(Rn) ); XOP1CC( OP_ST, CC_C, R_T); :}
1.414 -SHLL2 Rn {: XOP2I( OP_SLL, 2, R_R(Rn) ); :}
1.415 -SHLL8 Rn {: XOP2I( OP_SLL, 8, R_R(Rn) ); :}
1.416 -SHLL16 Rn {: XOP2I( OP_SLL, 16, R_R(Rn) ); :}
1.417 -SHLR Rn {: XOP2I( OP_SLRS, 1, R_R(Rn) ); XOP1CC( OP_ST, CC_C, R_T); :}
1.418 -SHLR2 Rn {: XOP2I( OP_SLR, 2, R_R(Rn) ); :}
1.419 -SHLR8 Rn {: XOP2I( OP_SLR, 8, R_R(Rn) ); :}
1.420 -SHLR16 Rn {: XOP2I( OP_SLR, 16, R_R(Rn) ); :}
1.421 +OR Rm, Rn {: XOP2SS( OP_OR, R_R(Rm), R_R(Rn) ); :}
1.422 +OR #imm, R0 {: XOP2IS( OP_OR, imm, R_R0 ); :}
1.423 +ROTCL Rn {: XOP1SCC( OP_LD, CC_C, R_T ); XOP2IS( OP_RCL, 1, R_R(Rn) ); XOP1SCC( OP_ST, CC_C, R_T); :}
1.424 +ROTCR Rn {: XOP1SCC( OP_LD, CC_C, R_T ); XOP2IS( OP_RCR, 1, R_R(Rn) ); XOP1SCC( OP_ST, CC_C, R_T); :}
1.425 +ROTL Rn {: XOP2IS( OP_ROL, 1, R_R(Rn) ); :}
1.426 +ROTR Rn {: XOP2IS( OP_ROR, 1, R_R(Rn) ); :}
1.427 +SHAD Rm, Rn {: XOP2SS( OP_SHAD, R_R(Rm), R_R(Rn) ); :}
1.428 +SHLD Rm, Rn {: XOP2SS( OP_SHLD, R_R(Rm), R_R(Rn) ); :}
1.429 +SHAL Rn {: XOP2IS( OP_SLLS, 1, R_R(Rn) ); XOP1SCC( OP_ST, CC_C, R_T); :}
1.430 +SHAR Rn {: XOP2IS( OP_SARS, 1, R_R(Rn) ); XOP1SCC( OP_ST, CC_C, R_T); :}
1.431 +SHLL Rn {: XOP2IS( OP_SLLS, 1, R_R(Rn) ); XOP1SCC( OP_ST, CC_C, R_T); :}
1.432 +SHLL2 Rn {: XOP2IS( OP_SLL, 2, R_R(Rn) ); :}
1.433 +SHLL8 Rn {: XOP2IS( OP_SLL, 8, R_R(Rn) ); :}
1.434 +SHLL16 Rn {: XOP2IS( OP_SLL, 16, R_R(Rn) ); :}
1.435 +SHLR Rn {: XOP2IS( OP_SLRS, 1, R_R(Rn) ); XOP1SCC( OP_ST, CC_C, R_T); :}
1.436 +SHLR2 Rn {: XOP2IS( OP_SLR, 2, R_R(Rn) ); :}
1.437 +SHLR8 Rn {: XOP2IS( OP_SLR, 8, R_R(Rn) ); :}
1.438 +SHLR16 Rn {: XOP2IS( OP_SLR, 16, R_R(Rn) ); :}
1.439 SUB Rm, Rn {:
1.440 if( Rm == Rn ) {
1.441 /* Break false dependence */
1.442 - XOP2I( OP_MOV, 0, R_R(Rn) );
1.443 + XOP2IS( OP_MOV, 0, R_R(Rn) );
1.444 } else {
1.445 - XOP2( OP_SUB, R_R(Rm), R_R(Rn) );
1.446 + XOP2SS( OP_SUB, R_R(Rm), R_R(Rn) );
1.447 }
1.448 :}
1.449 -SUBC Rm, Rn {: XOP1CC( OP_LD, CC_C, R_T ); XOP2( OP_SUBBS, R_R(Rm), R_R(Rn) ); XOP1CC( OP_ST, CC_C, R_T ); :}
1.450 -SUBV Rm, Rn {: XOP2( OP_SUB, R_R(Rm), R_R(Rn) ); XOP1CC( OP_ST, CC_OV, R_T ); :}
1.451 +SUBC Rm, Rn {: XOP1SCC( OP_LD, CC_C, R_T ); XOP2SS( OP_SUBBS, R_R(Rm), R_R(Rn) ); XOP1SCC( OP_ST, CC_C, R_T ); :}
1.452 +SUBV Rm, Rn {: XOP2SS( OP_SUB, R_R(Rm), R_R(Rn) ); XOP1SCC( OP_ST, CC_OV, R_T ); :}
1.453 SWAP.B Rm, Rn {:
1.454 if( Rm != Rn ) {
1.455 - XOP2( OP_MOV, R_R(Rm), R_R(Rn) );
1.456 + XOP2SS( OP_MOV, R_R(Rm), R_R(Rn) );
1.457 }
1.458 - XOP2I( OP_SHUFFLE, 0x1243, R_R(Rn) );
1.459 + XOP2IS( OP_SHUFFLE, 0x1243, R_R(Rn) );
1.460 :}
1.461 SWAP.W Rm, Rn {:
1.462 if( Rm != Rn ) {
1.463 - XOP2( OP_MOV, R_R(Rm), R_R(Rn) );
1.464 + XOP2SS( OP_MOV, R_R(Rm), R_R(Rn) );
1.465 }
1.466 - XOP2I( OP_SHUFFLE, 0x3412, R_R(Rn) );
1.467 + XOP2IS( OP_SHUFFLE, 0x3412, R_R(Rn) );
1.468 :}
1.469 -TST Rm, Rn {: XOP2( OP_TST, R_R(Rm), R_R(Rn) ); XOP1CC( OP_ST, CC_EQ, R_T ); :}
1.470 -TST #imm, R0 {: XOP2I( OP_TST, imm, R_R0 ); XOP1CC( OP_ST, CC_EQ, R_T ); :}
1.471 +TST Rm, Rn {: XOP2SS( OP_TST, R_R(Rm), R_R(Rn) ); XOP1SCC( OP_ST, CC_EQ, R_T ); :}
1.472 +TST #imm, R0 {: XOP2IS( OP_TST, imm, R_R0 ); XOP1SCC( OP_ST, CC_EQ, R_T ); :}
1.473 XOR Rm, Rn {:
1.474 if( Rm == Rn ) {
1.475 /* Break false dependence */
1.476 - XOP2I( OP_MOV, 0, R_R(Rn) );
1.477 + XOP2IS( OP_MOV, 0, R_R(Rn) );
1.478 } else {
1.479 - XOP2( OP_XOR, R_R(Rm), R_R(Rn) );
1.480 + XOP2SS( OP_XOR, R_R(Rm), R_R(Rn) );
1.481 }
1.482 :}
1.483 -XOR #imm, R0 {: XOP2I( OP_XOR, imm, R_R0 ); :}
1.484 +XOR #imm, R0 {: XOP2IS( OP_XOR, imm, R_R0 ); :}
1.485 XTRCT Rm, Rn {:
1.486 - XOP2( OP_MOV, R_R(Rm), REG_TMP0 );
1.487 - XOP2I( OP_SLL, 16, REG_TMP0 );
1.488 - XOP2I( OP_SLR, 16, R_R(Rn) );
1.489 - XOP2( OP_OR, REG_TMP0, R_R(Rn) );
1.490 + XOP2ST( OP_MOV, R_R(Rm), REG_TMP0 );
1.491 + XOP2IT( OP_SLL, 16, REG_TMP0 );
1.492 + XOP2IS( OP_SLR, 16, R_R(Rn) );
1.493 + XOP2TS( OP_OR, REG_TMP0, R_R(Rn) );
1.494 :}
1.495 -MOV Rm, Rn {: XOP2( OP_MOV, R_R(Rm), R_R(Rn) ); :}
1.496 -MOV #imm, Rn {: XOP2I( OP_MOV, imm, R_R(Rn) ); :}
1.497 +MOV Rm, Rn {: XOP2SS( OP_MOV, R_R(Rm), R_R(Rn) ); :}
1.498 +MOV #imm, Rn {: XOP2IS( OP_MOV, imm, R_R(Rn) ); :}
1.499
1.500 AND.B #imm, @(R0, GBR) {:
1.501 - XOP2( OP_MOV, R_R0, REG_TMP0 );
1.502 - XOP2( OP_ADD, R_GBR, REG_TMP0 );
1.503 - XOP2E( OP_LOADBFW, REG_TMP0, REG_TMP1 );
1.504 - XOP2I( OP_AND, imm, REG_TMP1 );
1.505 - XOP2E( OP_STOREB, REG_TMP0, REG_TMP1 );
1.506 + XOP2ST( OP_MOV, R_R0, REG_TMP0 );
1.507 + XOP2ST( OP_ADD, R_GBR, REG_TMP0 );
1.508 + XOP2TTE( OP_LOADBFW, REG_TMP0, REG_TMP1 );
1.509 + XOP2IT( OP_AND, imm, REG_TMP1 );
1.510 + XOP2TTE( OP_STOREB, REG_TMP0, REG_TMP1 );
1.511 :}
1.512 OR.B #imm, @(R0, GBR) {:
1.513 - XOP2( OP_MOV, R_R0, REG_TMP0 );
1.514 - XOP2( OP_ADD, R_GBR, REG_TMP0 );
1.515 - XOP2E( OP_LOADBFW, REG_TMP0, REG_TMP1 );
1.516 - XOP2I( OP_OR, imm, REG_TMP1 );
1.517 - XOP2E( OP_STOREB, REG_TMP0, REG_TMP1 );
1.518 + XOP2ST( OP_MOV, R_R0, REG_TMP0 );
1.519 + XOP2ST( OP_ADD, R_GBR, REG_TMP0 );
1.520 + XOP2TTE( OP_LOADBFW, REG_TMP0, REG_TMP1 );
1.521 + XOP2IT( OP_OR, imm, REG_TMP1 );
1.522 + XOP2TTE( OP_STOREB, REG_TMP0, REG_TMP1 );
1.523 :}
1.524 TAS.B @Rn {:
1.525 - XOP1( OP_OCBP, R_R(Rn) );
1.526 - XOP2E( OP_LOADBFW, R_R(Rn), REG_TMP0 );
1.527 - XOP2I( OP_CMP, 0, REG_TMP0 );
1.528 - XOP1CC(OP_ST, CC_EQ, R_T );
1.529 - XOP2I( OP_OR, 0x80, REG_TMP0 );
1.530 - XOP2E( OP_STOREB, R_R(Rn), REG_TMP0 );
1.531 + XOP1S( OP_OCBP, R_R(Rn) );
1.532 + XOP2STE( OP_LOADBFW, R_R(Rn), REG_TMP0 );
1.533 + XOP2IT( OP_CMP, 0, REG_TMP0 );
1.534 + XOP1SCC(OP_ST, CC_EQ, R_T );
1.535 + XOP2IT( OP_OR, 0x80, REG_TMP0 );
1.536 + XOP2STE( OP_STOREB, R_R(Rn), REG_TMP0 );
1.537 :}
1.538 TST.B #imm, @(R0, GBR) {:
1.539 - XOP2( OP_MOV, R_R0, REG_TMP0 );
1.540 - XOP2( OP_ADD, R_GBR, REG_TMP0 );
1.541 - XOP2E( OP_LOADB, REG_TMP0, REG_TMP0 );
1.542 - XOP2I( OP_TST, imm, REG_TMP0 );
1.543 + XOP2ST( OP_MOV, R_R0, REG_TMP0 );
1.544 + XOP2ST( OP_ADD, R_GBR, REG_TMP0 );
1.545 + XOP2TTE( OP_LOADB, REG_TMP0, REG_TMP0 );
1.546 + XOP2IT( OP_TST, imm, REG_TMP0 );
1.547 :}
1.548 XOR.B #imm, @(R0, GBR) {:
1.549 - XOP2( OP_MOV, R_R0, REG_TMP0 );
1.550 - XOP2( OP_ADD, R_GBR, REG_TMP0 );
1.551 - XOP2E( OP_LOADBFW, REG_TMP0, REG_TMP1 );
1.552 - XOP2I( OP_XOR, imm, REG_TMP1 );
1.553 - XOP2E( OP_STOREB, REG_TMP0, REG_TMP1 );
1.554 + XOP2ST( OP_MOV, R_R0, REG_TMP0 );
1.555 + XOP2ST( OP_ADD, R_GBR, REG_TMP0 );
1.556 + XOP2TTE( OP_LOADBFW, REG_TMP0, REG_TMP1 );
1.557 + XOP2IT( OP_XOR, imm, REG_TMP1 );
1.558 + XOP2TTE( OP_STOREB, REG_TMP0, REG_TMP1 );
1.559 :}
1.560
1.561 MOV.B Rm, @Rn {:
1.562 - XOP2E( OP_STOREB, R_R(Rn), R_R(Rm) );
1.563 + XOP2SSE( OP_STOREB, R_R(Rn), R_R(Rm) );
1.564 :}
1.565 MOV.B Rm, @-Rn {:
1.566 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.567 - XOP2I( OP_ADD, -1, REG_TMP0 );
1.568 - XOP2E( OP_STOREB, REG_TMP0, R_R(Rm) );
1.569 - XOP2I( OP_ADD, -1, R_R(Rn) );
1.570 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.571 + XOP2IT( OP_ADD, -1, REG_TMP0 );
1.572 + XOP2TSE( OP_STOREB, REG_TMP0, R_R(Rm) );
1.573 + XOP2IS( OP_ADD, -1, R_R(Rn) );
1.574 :}
1.575 MOV.B Rm, @(R0, Rn) {:
1.576 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.577 - XOP2( OP_ADD, R_R0, REG_TMP0 );
1.578 - XOP2E( OP_STOREB, REG_TMP0, R_R(Rm) );
1.579 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.580 + XOP2ST( OP_ADD, R_R0, REG_TMP0 );
1.581 + XOP2TSE( OP_STOREB, REG_TMP0, R_R(Rm) );
1.582 :}
1.583 MOV.B R0, @(disp, GBR) {:
1.584 - XOP2( OP_MOV, R_GBR, REG_TMP0 );
1.585 - XOP2I( OP_ADD, disp, REG_TMP0 );
1.586 - XOP2E( OP_STOREB, REG_TMP0, R_R0 );
1.587 + XOP2ST( OP_MOV, R_GBR, REG_TMP0 );
1.588 + XOP2IT( OP_ADD, disp, REG_TMP0 );
1.589 + XOP2TSE( OP_STOREB, REG_TMP0, R_R0 );
1.590 :}
1.591 MOV.B R0, @(disp, Rn) {:
1.592 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.593 - XOP2I( OP_ADD, disp, REG_TMP0 );
1.594 - XOP2E( OP_STOREB, REG_TMP0, R_R0 );
1.595 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.596 + XOP2IT( OP_ADD, disp, REG_TMP0 );
1.597 + XOP2TSE( OP_STOREB, REG_TMP0, R_R0 );
1.598 :}
1.599 MOV.B @Rm, Rn {:
1.600 - XOP2E( OP_LOADB, R_R(Rm), R_R(Rn) );
1.601 + XOP2SSE( OP_LOADB, R_R(Rm), R_R(Rn) );
1.602 :}
1.603 MOV.B @Rm+, Rn {:
1.604 - XOP2E( OP_LOADB, R_R(Rm), R_R(Rn) );
1.605 + XOP2SSE( OP_LOADB, R_R(Rm), R_R(Rn) );
1.606 if( Rm != Rn ) {
1.607 - XOP2I( OP_ADD, 1, R_R(Rm) );
1.608 + XOP2IS( OP_ADD, 1, R_R(Rm) );
1.609 }
1.610 :}
1.611 MOV.B @(R0, Rm), Rn {:
1.612 - XOP2( OP_MOV, R_R(Rm), REG_TMP0 );
1.613 - XOP2( OP_ADD, R_R0, REG_TMP0 );
1.614 - XOP2E(OP_LOADB, REG_TMP0, R_R(Rn) );
1.615 + XOP2ST( OP_MOV, R_R(Rm), REG_TMP0 );
1.616 + XOP2ST( OP_ADD, R_R0, REG_TMP0 );
1.617 + XOP2TSE(OP_LOADB, REG_TMP0, R_R(Rn) );
1.618 :}
1.619 MOV.B @(disp, GBR), R0 {:
1.620 - XOP2( OP_MOV, R_GBR, REG_TMP0 );
1.621 - XOP2I(OP_ADD, disp, REG_TMP0 );
1.622 - XOP2E(OP_LOADB, REG_TMP0, R_R0 );
1.623 + XOP2ST( OP_MOV, R_GBR, REG_TMP0 );
1.624 + XOP2IT(OP_ADD, disp, REG_TMP0 );
1.625 + XOP2TSE(OP_LOADB, REG_TMP0, R_R0 );
1.626 :}
1.627 MOV.B @(disp, Rm), R0 {:
1.628 - XOP2( OP_MOV, R_R(Rm), REG_TMP0 );
1.629 - XOP2I(OP_ADD, disp, REG_TMP0 );
1.630 - XOP2E(OP_LOADB, REG_TMP0, R_R0 );
1.631 + XOP2ST( OP_MOV, R_R(Rm), REG_TMP0 );
1.632 + XOP2IT(OP_ADD, disp, REG_TMP0 );
1.633 + XOP2TSE(OP_LOADB, REG_TMP0, R_R0 );
1.634 :}
1.635 MOV.L Rm, @Rn {:
1.636 WALIGN32( R_R(Rn) );
1.637 - XOP2E( OP_STOREL, R_R(Rn), R_R(Rm) );
1.638 + XOP2SSE( OP_STOREL, R_R(Rn), R_R(Rm) );
1.639 :}
1.640 MOV.L Rm, @-Rn {:
1.641 WALIGN32( R_R(Rn) );
1.642 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.643 - XOP2I(OP_ADD, -4, REG_TMP0 );
1.644 - XOP2( OP_STOREL, REG_TMP0, R_R(Rm) );
1.645 - XOP2I(OP_ADD, -4, R_R(Rn) );
1.646 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.647 + XOP2IT(OP_ADD, -4, REG_TMP0 );
1.648 + XOP2TS( OP_STOREL, REG_TMP0, R_R(Rm) );
1.649 + XOP2IS(OP_ADD, -4, R_R(Rn) );
1.650 :}
1.651 MOV.L Rm, @(R0, Rn) {:
1.652 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.653 - XOP2( OP_ADD, R_R0, REG_TMP0 );
1.654 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.655 + XOP2ST( OP_ADD, R_R0, REG_TMP0 );
1.656 WALIGN32( REG_TMP0 );
1.657 - XOP2E(OP_STOREL, REG_TMP0, R_R(Rm) );
1.658 + XOP2TSE(OP_STOREL, REG_TMP0, R_R(Rm) );
1.659 :}
1.660 MOV.L R0, @(disp, GBR) {:
1.661 - XOP2( OP_MOV, R_GBR, REG_TMP0 );
1.662 - XOP2I(OP_ADD, disp, REG_TMP0 );
1.663 + XOP2ST( OP_MOV, R_GBR, REG_TMP0 );
1.664 + XOP2IT(OP_ADD, disp, REG_TMP0 );
1.665 WALIGN32( REG_TMP0 );
1.666 - XOP2E(OP_STOREL, REG_TMP0, R_R0 );
1.667 + XOP2TSE(OP_STOREL, REG_TMP0, R_R0 );
1.668 :}
1.669 MOV.L Rm, @(disp, Rn) {:
1.670 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.671 - XOP2I(OP_ADD, disp, REG_TMP0 );
1.672 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.673 + XOP2IT(OP_ADD, disp, REG_TMP0 );
1.674 WALIGN32( REG_TMP0 );
1.675 - XOP2E(OP_STOREL, REG_TMP0, R_R(Rm) );
1.676 + XOP2TSE(OP_STOREL, REG_TMP0, R_R(Rm) );
1.677 :}
1.678 MOV.L @Rm, Rn {:
1.679 RALIGN32( R_R(Rm) );
1.680 - XOP2E(OP_LOADL, R_R(Rm), R_R(Rn) );
1.681 + XOP2SSE(OP_LOADL, R_R(Rm), R_R(Rn) );
1.682 :}
1.683 MOV.L @Rm+, Rn {:
1.684 RALIGN32( R_R(Rm) );
1.685 - XOP2E( OP_LOADL, R_R(Rm), R_R(Rn) );
1.686 + XOP2SSE( OP_LOADL, R_R(Rm), R_R(Rn) );
1.687 if( R_R(Rm) != R_R(Rn) ) {
1.688 - XOP2I( OP_ADD, 4, R_R(Rm) );
1.689 + XOP2IS( OP_ADD, 4, R_R(Rm) );
1.690 }
1.691 :}
1.692 MOV.L @(R0, Rm), Rn {:
1.693 - XOP2( OP_MOV, R_R0, REG_TMP0 );
1.694 - XOP2( OP_ADD, R_R(Rm), REG_TMP0 );
1.695 + XOP2ST( OP_MOV, R_R0, REG_TMP0 );
1.696 + XOP2ST( OP_ADD, R_R(Rm), REG_TMP0 );
1.697 RALIGN32( REG_TMP0 );
1.698 - XOP2E(OP_LOADL, REG_TMP0, R_R(Rn) );
1.699 + XOP2TSE(OP_LOADL, REG_TMP0, R_R(Rn) );
1.700 :}
1.701 MOV.L @(disp, GBR), R0 {:
1.702 - XOP2( OP_MOV, R_GBR, REG_TMP0 );
1.703 - XOP2I(OP_ADD, disp, REG_TMP0 );
1.704 + XOP2ST( OP_MOV, R_GBR, REG_TMP0 );
1.705 + XOP2IT(OP_ADD, disp, REG_TMP0 );
1.706 RALIGN32( REG_TMP0 );
1.707 - XOP2E(OP_LOADL, REG_TMP0, R_R0 );
1.708 + XOP2TSE(OP_LOADL, REG_TMP0, R_R0 );
1.709 :}
1.710 MOV.L @(disp, PC), Rn {:
1.711 if( in_delay_slot ) {
1.712 @@ -520,74 +558,74 @@
1.713 // behaviour to confirm) Unlikely to be anyone depending on this
1.714 // behaviour though.
1.715 sh4ptr_t ptr = GET_ICACHE_PTR(target);
1.716 - XOP2P( OP_MOV, ptr, R_R(Rn) );
1.717 + XOP2PS( OP_LOADPTRL, ptr, R_R(Rn) );
1.718 } else {
1.719 // Note: we use sh4r.pc for the calc as we could be running at a
1.720 // different virtual address than the translation was done with,
1.721 // but we can safely assume that the low bits are the same.
1.722 - XOP2( OP_MOV, R_PC, REG_TMP0 );
1.723 - XOP2( OP_ADD, (pc-xbb->pc_begin) + disp + 4 - (pc&0x03), REG_TMP0 );
1.724 - XOP2E(OP_LOADL, REG_TMP0, R_R(Rn) );
1.725 + XOP2ST( OP_MOV, R_PC, REG_TMP0 );
1.726 + XOP2IT( OP_ADD, (pc-xbb->pc_begin) + disp + 4 - (pc&0x03), REG_TMP0 );
1.727 + XOP2TSE(OP_LOADL, REG_TMP0, R_R(Rn) );
1.728 }
1.729 }
1.730 :}
1.731 MOV.L @(disp, Rm), Rn {:
1.732 - XOP2( OP_MOV, R_R(Rm), REG_TMP0 );
1.733 - XOP2I(OP_ADD, disp, REG_TMP0 );
1.734 + XOP2ST( OP_MOV, R_R(Rm), REG_TMP0 );
1.735 + XOP2IT(OP_ADD, disp, REG_TMP0 );
1.736 RALIGN32( REG_TMP0 );
1.737 - XOP2E(OP_LOADL, REG_TMP0, R_R(Rn) );
1.738 + XOP2TSE(OP_LOADL, REG_TMP0, R_R(Rn) );
1.739 :}
1.740 MOV.W Rm, @Rn {:
1.741 WALIGN16( R_R(Rn) );
1.742 - XOP2E(OP_STOREW, R_R(Rn), R_R(Rm) );
1.743 + XOP2SSE(OP_STOREW, R_R(Rn), R_R(Rm) );
1.744 :}
1.745 MOV.W Rm, @-Rn {:
1.746 WALIGN16( R_R(Rn) );
1.747 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.748 - XOP2I(OP_ADD, -2, REG_TMP0 );
1.749 - XOP2E(OP_STOREW, REG_TMP0, R_R(Rm) );
1.750 - XOP2I(OP_ADD, -2, R_R(Rn) );
1.751 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.752 + XOP2IT(OP_ADD, -2, REG_TMP0 );
1.753 + XOP2TSE(OP_STOREW, REG_TMP0, R_R(Rm) );
1.754 + XOP2IS(OP_ADD, -2, R_R(Rn) );
1.755 :}
1.756 MOV.W Rm, @(R0, Rn) {:
1.757 - XOP2( OP_MOV, R_R0, REG_TMP0 );
1.758 - XOP2( OP_ADD, R_R(Rn), REG_TMP0 );
1.759 + XOP2ST( OP_MOV, R_R0, REG_TMP0 );
1.760 + XOP2ST( OP_ADD, R_R(Rn), REG_TMP0 );
1.761 WALIGN16( REG_TMP0 );
1.762 - XOP2E(OP_STOREW, REG_TMP0, R_R(Rm) );
1.763 + XOP2TSE(OP_STOREW, REG_TMP0, R_R(Rm) );
1.764 :}
1.765 MOV.W R0, @(disp, GBR) {:
1.766 - XOP2( OP_MOV, R_GBR, REG_TMP0 );
1.767 - XOP2I(OP_ADD, disp, REG_TMP0 );
1.768 + XOP2ST( OP_MOV, R_GBR, REG_TMP0 );
1.769 + XOP2IT(OP_ADD, disp, REG_TMP0 );
1.770 WALIGN16( REG_TMP0 );
1.771 - XOP2( OP_STOREW, REG_TMP0, R_R0 );
1.772 + XOP2TS( OP_STOREW, REG_TMP0, R_R0 );
1.773 :}
1.774 MOV.W R0, @(disp, Rn) {:
1.775 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.776 - XOP2I(OP_ADD, disp, REG_TMP0 );
1.777 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.778 + XOP2IT(OP_ADD, disp, REG_TMP0 );
1.779 WALIGN16( REG_TMP0 );
1.780 - XOP2E(OP_STOREW, REG_TMP0, R_R0 );
1.781 + XOP2TSE(OP_STOREW, REG_TMP0, R_R0 );
1.782 :}
1.783 MOV.W @Rm, Rn {:
1.784 RALIGN16( R_R(Rm) );
1.785 - XOP2E(OP_LOADW, R_R(Rm), R_R(Rn) );
1.786 + XOP2SSE(OP_LOADW, R_R(Rm), R_R(Rn) );
1.787 :}
1.788 MOV.W @Rm+, Rn {:
1.789 RALIGN16( R_R(Rm) );
1.790 - XOP2E(OP_LOADW, R_R(Rm), R_R(Rn) );
1.791 + XOP2SSE(OP_LOADW, R_R(Rm), R_R(Rn) );
1.792 if( Rm != Rn ) {
1.793 - XOP2I( OP_ADD, 2, R_R(Rm) );
1.794 + XOP2IS( OP_ADD, 2, R_R(Rm) );
1.795 }
1.796 :}
1.797 MOV.W @(R0, Rm), Rn {:
1.798 - XOP2( OP_MOV, R_R0, REG_TMP0 );
1.799 - XOP2( OP_ADD, R_R(Rm), REG_TMP0 );
1.800 + XOP2ST( OP_MOV, R_R0, REG_TMP0 );
1.801 + XOP2ST( OP_ADD, R_R(Rm), REG_TMP0 );
1.802 RALIGN16( REG_TMP0 );
1.803 - XOP2E(OP_LOADW, REG_TMP0, R_R(Rn) );
1.804 + XOP2TSE(OP_LOADW, REG_TMP0, R_R(Rn) );
1.805 :}
1.806 MOV.W @(disp, GBR), R0 {:
1.807 - XOP2( OP_MOV, R_GBR, REG_TMP0 );
1.808 - XOP2I(OP_ADD, disp, REG_TMP0 );
1.809 + XOP2ST( OP_MOV, R_GBR, REG_TMP0 );
1.810 + XOP2IT(OP_ADD, disp, REG_TMP0 );
1.811 RALIGN16( REG_TMP0 );
1.812 - XOP2E(OP_LOADW, REG_TMP0, R_R0 );
1.813 + XOP2TSE(OP_LOADW, REG_TMP0, R_R0 );
1.814 :}
1.815 MOV.W @(disp, PC), Rn {:
1.816 if( in_delay_slot ) {
1.817 @@ -606,296 +644,296 @@
1.818 // behaviour to confirm) Unlikely to be anyone depending on this
1.819 // behaviour though.
1.820 sh4ptr_t ptr = GET_ICACHE_PTR(target);
1.821 - XOP2P( OP_MOV, ptr, REG_TMP0 );
1.822 - XOP2( OP_MOVSX16, REG_TMP0, R_R(Rn) );
1.823 + XOP2PT( OP_LOADPTRL, ptr, REG_TMP0 );
1.824 + XOP2TS( OP_MOVSX16, REG_TMP0, R_R(Rn) );
1.825 } else {
1.826 // Note: we use sh4r.pc for the calc as we could be running at a
1.827 // different virtual address than the translation was done with,
1.828 // but we can safely assume that the low bits are the same.
1.829 - XOP2( OP_MOV, R_PC, REG_TMP0 );
1.830 - XOP2( OP_ADD, (pc - xbb->pc_begin) + disp + 4, REG_TMP0 );
1.831 - XOP2E(OP_LOADW, REG_TMP0, R_R(Rn) );
1.832 + XOP2ST( OP_MOV, R_PC, REG_TMP0 );
1.833 + XOP2IT( OP_ADD, (pc - xbb->pc_begin) + disp + 4, REG_TMP0 );
1.834 + XOP2TSE(OP_LOADW, REG_TMP0, R_R(Rn) );
1.835 }
1.836 }
1.837 :}
1.838 MOV.W @(disp, Rm), R0 {:
1.839 - XOP2( OP_MOV, R_R(Rm), REG_TMP0 );
1.840 - XOP2I(OP_ADD, disp, REG_TMP0 );
1.841 + XOP2ST( OP_MOV, R_R(Rm), REG_TMP0 );
1.842 + XOP2IT(OP_ADD, disp, REG_TMP0 );
1.843 RALIGN16( REG_TMP0 );
1.844 - XOP2E(OP_LOADW, REG_TMP0, R_R0 );
1.845 + XOP2TSE(OP_LOADW, REG_TMP0, R_R0 );
1.846 :}
1.847 MOVA @(disp, PC), R0 {:
1.848 if( in_delay_slot ) {
1.849 SLOTILLEGAL();
1.850 return 2;
1.851 } else {
1.852 - XOP2( OP_MOV, R_PC, R_R0 );
1.853 - XOP2I( OP_ADD, (pc - xbb->pc_begin) + disp + 4 - (pc&0x03), R_R0 );
1.854 + XOP2SS( OP_MOV, R_PC, R_R0 );
1.855 + XOP2IS( OP_ADD, (pc - xbb->pc_begin) + disp + 4 - (pc&0x03), R_R0 );
1.856 }
1.857 :}
1.858 MOVCA.L R0, @Rn {:
1.859 - XOP2E(OP_STORELCA, R_R(Rn), R_R0 );
1.860 + XOP2SSE(OP_STORELCA, R_R(Rn), R_R0 );
1.861 :}
1.862 LDTLB {:
1.863 CHECKPRIV();
1.864 XOPCALL0( MMU_ldtlb );
1.865 :}
1.866 -OCBI @Rn {: XOP1E( OP_OCBI, R_R(Rn) ); :}
1.867 -OCBP @Rn {: XOP1E( OP_OCBP, R_R(Rn) ); :}
1.868 -OCBWB @Rn {: XOP1E( OP_OCBWB, R_R(Rn) ); :}
1.869 -PREF @Rn {: XOP1E( OP_PREF, R_R(Rn) ); :}
1.870 +OCBI @Rn {: XOP1SE( OP_OCBI, R_R(Rn) ); :}
1.871 +OCBP @Rn {: XOP1SE( OP_OCBP, R_R(Rn) ); :}
1.872 +OCBWB @Rn {: XOP1SE( OP_OCBWB, R_R(Rn) ); :}
1.873 +PREF @Rn {: XOP1SE( OP_PREF, R_R(Rn) ); :}
1.874
1.875 CLRMAC {:
1.876 - XOP2I( OP_MOV, 0, R_MACL );
1.877 - XOP2I( OP_MOV, 0, R_MACH );
1.878 + XOP2IS( OP_MOV, 0, R_MACL );
1.879 + XOP2IS( OP_MOV, 0, R_MACH );
1.880 :}
1.881 -CLRS {: XOP2I( OP_MOV, 0, R_S ); :}
1.882 -CLRT {: XOP2I( OP_MOV, 0, R_T ); :}
1.883 -SETS {: XOP2I( OP_MOV, 1, R_S ); :}
1.884 -SETT {: XOP2I( OP_MOV, 1, R_T ); :}
1.885 +CLRS {: XOP2IS( OP_MOV, 0, R_S ); :}
1.886 +CLRT {: XOP2IS( OP_MOV, 0, R_T ); :}
1.887 +SETS {: XOP2IS( OP_MOV, 1, R_S ); :}
1.888 +SETT {: XOP2IS( OP_MOV, 1, R_T ); :}
1.889 FMOV FRm, FRn {:
1.890 CHECKFPUEN();
1.891 if( sh4_xir.double_size ) {
1.892 - XOP2( OP_MOVQ, (FRm&1) ? R_XD(FRm) : R_DR(FRm), (FRn&1) ? R_XD(FRn) : R_DR(FRn) );
1.893 + XOP2SS( OP_MOVQ, (FRm&1) ? R_XD(FRm) : R_DR(FRm), (FRn&1) ? R_XD(FRn) : R_DR(FRn) );
1.894 } else {
1.895 - XOP2( OP_MOV, R_FR(FRm), R_FR(FRn) );
1.896 + XOP2SS( OP_MOV, R_FR(FRm), R_FR(FRn) );
1.897 }
1.898 :}
1.899 FMOV FRm, @Rn {:
1.900 CHECKFPUEN();
1.901 if( sh4_xir.double_size ) {
1.902 WALIGN64( R_R(Rn) );
1.903 - XOP2E( OP_STOREQ, R_R(Rn), (FRm&1) ? R_XD(FRm) : R_DR(FRm) );
1.904 + XOP2SSE( OP_STOREQ, R_R(Rn), (FRm&1) ? R_XD(FRm) : R_DR(FRm) );
1.905 } else {
1.906 WALIGN32( R_R(Rn) );
1.907 - XOP2E( OP_STOREL, R_R(Rn), R_FR(FRm) );
1.908 + XOP2SSE( OP_STOREL, R_R(Rn), R_FR(FRm) );
1.909 }
1.910 :}
1.911 FMOV @Rm, FRn {:
1.912 CHECKFPUEN();
1.913 if( sh4_xir.double_size ) {
1.914 RALIGN64( R_R(Rm) );
1.915 - XOP2E( OP_LOADQ, R_R(Rm), (FRn&1) ? R_XD(FRn) : R_DR(FRn) );
1.916 + XOP2SSE( OP_LOADQ, R_R(Rm), (FRn&1) ? R_XD(FRn) : R_DR(FRn) );
1.917 } else {
1.918 RALIGN32( R_R(Rm) );
1.919 - XOP2E( OP_LOADL, R_R(Rm), R_FR(FRn) );
1.920 + XOP2SSE( OP_LOADL, R_R(Rm), R_FR(FRn) );
1.921 }
1.922 :}
1.923 FMOV FRm, @-Rn {:
1.924 CHECKFPUEN();
1.925 if( sh4_xir.double_size ) {
1.926 WALIGN64( R_R(Rn) );
1.927 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.928 - XOP2I(OP_ADD, -8, REG_TMP0 );
1.929 - XOP2E(OP_STOREQ, REG_TMP0, (FRm&1) ? R_XD(FRm) : R_DR(FRm) );
1.930 - XOP2I(OP_ADD, -8, R_R(Rn) );
1.931 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.932 + XOP2IT(OP_ADD, -8, REG_TMP0 );
1.933 + XOP2TSE(OP_STOREQ, REG_TMP0, (FRm&1) ? R_XD(FRm) : R_DR(FRm) );
1.934 + XOP2IS(OP_ADD, -8, R_R(Rn) );
1.935 } else {
1.936 WALIGN32( R_R(Rn) );
1.937 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.938 - XOP2I(OP_ADD, -4, REG_TMP0 );
1.939 - XOP2E(OP_STOREL, REG_TMP0, R_FR(FRm) );
1.940 - XOP2I(OP_ADD, -4, R_R(Rn) );
1.941 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.942 + XOP2IT(OP_ADD, -4, REG_TMP0 );
1.943 + XOP2TSE(OP_STOREL, REG_TMP0, R_FR(FRm) );
1.944 + XOP2IS(OP_ADD, -4, R_R(Rn) );
1.945 }
1.946 :}
1.947 FMOV @Rm+, FRn {:
1.948 CHECKFPUEN();
1.949 if( sh4_xir.double_size ) {
1.950 RALIGN64( R_R(Rm) );
1.951 - XOP2( OP_LOADQ, R_R(Rm), (FRn&1) ? R_XD(FRn) : R_DR(FRn) );
1.952 - XOP2I( OP_ADD, 8, R_R(Rm) );
1.953 + XOP2SSE( OP_LOADQ, R_R(Rm), (FRn&1) ? R_XD(FRn) : R_DR(FRn) );
1.954 + XOP2IS( OP_ADD, 8, R_R(Rm) );
1.955 } else {
1.956 RALIGN32( R_R(Rm) );
1.957 - XOP2( OP_LOADL, R_R(Rm), R_FR(FRn) );
1.958 - XOP2I( OP_ADD, 4, R_R(Rm) );
1.959 + XOP2SSE( OP_LOADL, R_R(Rm), R_FR(FRn) );
1.960 + XOP2IS( OP_ADD, 4, R_R(Rm) );
1.961 }
1.962 :}
1.963 FMOV FRm, @(R0, Rn) {:
1.964 CHECKFPUEN();
1.965 - XOP2( OP_MOV, R_R0, REG_TMP0 );
1.966 - XOP2( OP_ADD, R_R(Rn), REG_TMP0 );
1.967 + XOP2ST( OP_MOV, R_R0, REG_TMP0 );
1.968 + XOP2ST( OP_ADD, R_R(Rn), REG_TMP0 );
1.969 if( sh4_xir.double_size ) {
1.970 WALIGN64( REG_TMP0 );
1.971 - XOP2E( OP_STOREQ, REG_TMP0, (FRm&1) ? R_XD(FRm) : R_DR(FRm) );
1.972 + XOP2TSE( OP_STOREQ, REG_TMP0, (FRm&1) ? R_XD(FRm) : R_DR(FRm) );
1.973 } else {
1.974 WALIGN32( REG_TMP0 );
1.975 - XOP2E( OP_STOREL, REG_TMP0, R_FR(FRm) );
1.976 + XOP2TSE( OP_STOREL, REG_TMP0, R_FR(FRm) );
1.977 }
1.978 :}
1.979 FMOV @(R0, Rm), FRn {:
1.980 CHECKFPUEN();
1.981 - XOP2( OP_MOV, R_R0, REG_TMP0 );
1.982 - XOP2( OP_ADD, R_R(Rm), REG_TMP0 );
1.983 + XOP2ST( OP_MOV, R_R0, REG_TMP0 );
1.984 + XOP2ST( OP_ADD, R_R(Rm), REG_TMP0 );
1.985 if( sh4_xir.double_size ) {
1.986 RALIGN64( REG_TMP0 );
1.987 - XOP2E( OP_LOADQ, REG_TMP0, (FRn&1) ? R_XD(FRn) : R_DR(FRn) );
1.988 + XOP2TSE( OP_LOADQ, REG_TMP0, (FRn&1) ? R_XD(FRn) : R_DR(FRn) );
1.989 } else {
1.990 RALIGN32( REG_TMP0 );
1.991 - XOP2E( OP_LOADL, REG_TMP0, R_FR(FRn) );
1.992 + XOP2TSE( OP_LOADL, REG_TMP0, R_FR(FRn) );
1.993 }
1.994 :}
1.995 FLDI0 FRn {: /* IFF PR=0 */
1.996 CHECKFPUEN();
1.997 if( sh4_xir.double_prec == 0 ) {
1.998 - XOP2F( OP_MOV, 0.0, R_FR(FRn) );
1.999 + XOP2FS( OP_MOV, 0.0, R_FR(FRn) );
1.1000 }
1.1001 :}
1.1002 FLDI1 FRn {: /* IFF PR=0 */
1.1003 CHECKFPUEN();
1.1004 if( sh4_xir.double_prec == 0 ) {
1.1005 - XOP2F( OP_MOV, 1.0, R_FR(FRn) );
1.1006 + XOP2FS( OP_MOV, 1.0, R_FR(FRn) );
1.1007 }
1.1008 :}
1.1009 FLOAT FPUL, FRn {:
1.1010 CHECKFPUEN();
1.1011 if( sh4_xir.double_prec ) {
1.1012 - XOP2( OP_ITOD, R_FPUL, R_DR(FRn) );
1.1013 + XOP2SS( OP_ITOD, R_FPUL, R_DR(FRn) );
1.1014 } else {
1.1015 - XOP2( OP_ITOF, R_FPUL, R_FR(FRn) );
1.1016 + XOP2SS( OP_ITOF, R_FPUL, R_FR(FRn) );
1.1017 }
1.1018 :}
1.1019 FTRC FRm, FPUL {:
1.1020 CHECKFPUEN();
1.1021 if( sh4_xir.double_prec ) {
1.1022 - XOP2( OP_DTOI, R_DR(FRm), R_FPUL );
1.1023 + XOP2SS( OP_DTOI, R_DR(FRm), R_FPUL );
1.1024 } else {
1.1025 - XOP2( OP_FTOI, R_FR(FRm), R_FPUL );
1.1026 + XOP2SS( OP_FTOI, R_FR(FRm), R_FPUL );
1.1027 }
1.1028 :}
1.1029 FLDS FRm, FPUL {:
1.1030 CHECKFPUEN();
1.1031 - XOP2( OP_MOV, R_FR(FRm), R_FPUL );
1.1032 + XOP2SS( OP_MOV, R_FR(FRm), R_FPUL );
1.1033 :}
1.1034 FSTS FPUL, FRn {:
1.1035 CHECKFPUEN();
1.1036 - XOP2( OP_MOV, R_FPUL, R_FR(FRn) );
1.1037 + XOP2SS( OP_MOV, R_FPUL, R_FR(FRn) );
1.1038 :}
1.1039 FCNVDS FRm, FPUL {:
1.1040 CHECKFPUEN();
1.1041 if( sh4_xir.double_prec && !sh4_xir.double_size ) {
1.1042 - XOP2( OP_DTOF, R_DR(FRm), R_FPUL );
1.1043 + XOP2SS( OP_DTOF, R_DR(FRm), R_FPUL );
1.1044 }
1.1045 :}
1.1046 FCNVSD FPUL, FRn {:
1.1047 CHECKFPUEN();
1.1048 if( sh4_xir.double_prec && !sh4_xir.double_size ) {
1.1049 - XOP2( OP_FTOD, R_FPUL, R_DR(FRn) );
1.1050 + XOP2SS( OP_FTOD, R_FPUL, R_DR(FRn) );
1.1051 }
1.1052 :}
1.1053 FABS FRn {:
1.1054 CHECKFPUEN();
1.1055 if( sh4_xir.double_prec ) {
1.1056 - XOP1( OP_ABSD, R_DR(FRn) );
1.1057 + XOP2SS( OP_ABSD, R_DR(FRn), R_DR(FRn) );
1.1058 } else {
1.1059 - XOP1( OP_ABSF, R_FR(FRn) );
1.1060 + XOP2SS( OP_ABSF, R_FR(FRn), R_FR(FRn) );
1.1061 }
1.1062 :}
1.1063 FADD FRm, FRn {:
1.1064 CHECKFPUEN();
1.1065 if( sh4_xir.double_prec ) {
1.1066 - XOP2( OP_ADDD, R_DR(FRm), R_DR(FRn) );
1.1067 + XOP2SS( OP_ADDD, R_DR(FRm), R_DR(FRn) );
1.1068 } else {
1.1069 - XOP2( OP_ADDF, R_FR(FRm), R_FR(FRn) );
1.1070 + XOP2SS( OP_ADDF, R_FR(FRm), R_FR(FRn) );
1.1071 }
1.1072 :}
1.1073 FDIV FRm, FRn {:
1.1074 CHECKFPUEN();
1.1075 if( sh4_xir.double_prec ) {
1.1076 - XOP2( OP_DIVD, R_DR(FRm), R_DR(FRn) );
1.1077 + XOP2SS( OP_DIVD, R_DR(FRm), R_DR(FRn) );
1.1078 } else {
1.1079 - XOP2( OP_DIVF, R_FR(FRm), R_FR(FRn) );
1.1080 + XOP2SS( OP_DIVF, R_FR(FRm), R_FR(FRn) );
1.1081 }
1.1082 :}
1.1083 FMAC FR0, FRm, FRn {:
1.1084 CHECKFPUEN();
1.1085 if( sh4_xir.double_prec == 0 ) {
1.1086 - XOP2( OP_MOV, R_FR(0), REG_TMP0 );
1.1087 - XOP2( OP_MULF, R_FR(FRm), REG_TMP0 );
1.1088 - XOP2( OP_ADDF, REG_TMP0, R_FR(FRn) );
1.1089 + XOP2ST( OP_MOV, R_FR(0), REG_TMP0 );
1.1090 + XOP2ST( OP_MULF, R_FR(FRm), REG_TMP0 );
1.1091 + XOP2TS( OP_ADDF, REG_TMP0, R_FR(FRn) );
1.1092 }
1.1093 :}
1.1094 FMUL FRm, FRn {:
1.1095 CHECKFPUEN();
1.1096 if( sh4_xir.double_prec ) {
1.1097 - XOP2( OP_MULD, R_DR(FRm), R_DR(FRn) );
1.1098 + XOP2SS( OP_MULD, R_DR(FRm), R_DR(FRn) );
1.1099 } else {
1.1100 - XOP2( OP_MULF, R_FR(FRm), R_FR(FRn) );
1.1101 + XOP2SS( OP_MULF, R_FR(FRm), R_FR(FRn) );
1.1102 }
1.1103 :}
1.1104 FNEG FRn {:
1.1105 CHECKFPUEN();
1.1106 if( sh4_xir.double_prec ) {
1.1107 - XOP1( OP_NEGD, R_DR(FRn) );
1.1108 + XOP2SS( OP_NEGD, R_DR(FRn), R_DR(FRn) );
1.1109 } else {
1.1110 - XOP1( OP_NEGF, R_FR(FRn) );
1.1111 + XOP2SS( OP_NEGF, R_FR(FRn), R_FR(FRn) );
1.1112 }
1.1113 :}
1.1114 FSRRA FRn {:
1.1115 CHECKFPUEN();
1.1116 if( sh4_xir.double_prec == 0 ) {
1.1117 - XOP1( OP_RSQRTF, R_FR(FRn) );
1.1118 + XOP2SS( OP_RSQRTF, R_FR(FRn), R_FR(FRn) );
1.1119 }
1.1120 :}
1.1121 FSQRT FRn {:
1.1122 CHECKFPUEN();
1.1123 if( sh4_xir.double_prec ) {
1.1124 - XOP1( OP_SQRTD, R_DR(FRn) );
1.1125 + XOP2SS( OP_SQRTD, R_DR(FRn), R_DR(FRn) );
1.1126 } else {
1.1127 - XOP1( OP_SQRTF, R_FR(FRn) );
1.1128 + XOP2SS( OP_SQRTF, R_FR(FRn), R_FR(FRn) );
1.1129 }
1.1130 :}
1.1131 FSUB FRm, FRn {:
1.1132 CHECKFPUEN();
1.1133 if( sh4_xir.double_prec ) {
1.1134 - XOP2( OP_SUBD, R_DR(FRm), R_DR(FRn) );
1.1135 + XOP2SS( OP_SUBD, R_DR(FRm), R_DR(FRn) );
1.1136 } else {
1.1137 - XOP2( OP_SUBF, R_FR(FRm), R_FR(FRn) );
1.1138 + XOP2SS( OP_SUBF, R_FR(FRm), R_FR(FRn) );
1.1139 }
1.1140 :}
1.1141 FCMP/EQ FRm, FRn {:
1.1142 CHECKFPUEN();
1.1143 if( sh4_xir.double_prec ) {
1.1144 - XOP2( OP_CMPD, R_DR(FRm), R_DR(FRn) );
1.1145 + XOP2SS( OP_CMPD, R_DR(FRm), R_DR(FRn) );
1.1146 } else {
1.1147 - XOP2( OP_CMPF, R_FR(FRm), R_FR(FRn) );
1.1148 + XOP2SS( OP_CMPF, R_FR(FRm), R_FR(FRn) );
1.1149 }
1.1150 - XOP1CC( OP_ST, CC_EQ, R_T );
1.1151 + XOP1SCC( OP_ST, CC_EQ, R_T );
1.1152 :}
1.1153 FCMP/GT FRm, FRn {:
1.1154 CHECKFPUEN();
1.1155 if( sh4_xir.double_prec ) {
1.1156 - XOP2( OP_CMPD, R_DR(FRm), R_DR(FRn) );
1.1157 + XOP2SS( OP_CMPD, R_DR(FRm), R_DR(FRn) );
1.1158 } else {
1.1159 - XOP2( OP_CMPF, R_FR(FRm), R_FR(FRn) );
1.1160 + XOP2SS( OP_CMPF, R_FR(FRm), R_FR(FRn) );
1.1161 }
1.1162 - XOP1CC( OP_ST, CC_SGT, R_T );
1.1163 + XOP1SCC( OP_ST, CC_SGT, R_T );
1.1164 :}
1.1165 FSCA FPUL, FRn {:
1.1166 CHECKFPUEN();
1.1167 if( sh4_xir.double_prec == 0 ) {
1.1168 - XOP2( OP_SINCOSF, R_FPUL, R_DR(FRn) );
1.1169 + XOP2SS( OP_SINCOSF, R_FPUL, R_DR(FRn) );
1.1170 }
1.1171 :}
1.1172 FIPR FVm, FVn {:
1.1173 CHECKFPUEN();
1.1174 if( sh4_xir.double_prec == 0 ) {
1.1175 - XOP2( OP_DOTPRODV, R_FV(FVm), R_FV(FVn) );
1.1176 + XOP2SS( OP_DOTPRODV, R_FV(FVm), R_FV(FVn) );
1.1177 }
1.1178 :}
1.1179 FTRV XMTRX, FVn {:
1.1180 CHECKFPUEN();
1.1181 if( sh4_xir.double_prec == 0 ) {
1.1182 - XOP2( OP_MATMULV, R_XMTRX, R_FV(FVn) );
1.1183 + XOP2SS( OP_MATMULV, R_XMTRX, R_FV(FVn) );
1.1184 }
1.1185 :}
1.1186 FRCHG {:
1.1187 CHECKFPUEN();
1.1188 - XOP2I( OP_XOR, FPSCR_FR, R_FPSCR );
1.1189 + XOP2IS( OP_XOR, FPSCR_FR, R_FPSCR );
1.1190 XOPCALL0( sh4_switch_fr_banks );
1.1191 :}
1.1192 FSCHG {:
1.1193 CHECKFPUEN();
1.1194 - XOP2I( OP_XOR, FPSCR_SZ, R_FPSCR );
1.1195 - XOP2I( OP_XOR, FPSCR_SZ, R_SH4_MODE );
1.1196 + XOP2IS( OP_XOR, FPSCR_SZ, R_FPSCR );
1.1197 + XOP2IS( OP_XOR, FPSCR_SZ, R_SH4_MODE );
1.1198 sh4_xir.double_size = !sh4_xir.double_size;
1.1199 :}
1.1200 LDC Rm, SR {:
1.1201 @@ -903,20 +941,20 @@
1.1202 SLOTILLEGAL();
1.1203 } else {
1.1204 CHECKPRIV();
1.1205 - XOPCALL1( sh4_write_sr, R_R(Rm) );
1.1206 + XOPCALL1S( sh4_write_sr, R_R(Rm) );
1.1207 }
1.1208 return 2;
1.1209 :}
1.1210 -LDC Rm, GBR {: XOP2( OP_MOV, R_R(Rm), R_GBR ); :}
1.1211 -LDC Rm, VBR {: CHECKPRIV(); XOP2( OP_MOV, R_R(Rm), R_VBR ); :}
1.1212 -LDC Rm, SSR {: CHECKPRIV(); XOP2( OP_MOV, R_R(Rm), R_SSR ); :}
1.1213 -LDC Rm, SGR {: CHECKPRIV(); XOP2( OP_MOV, R_R(Rm), R_SGR ); :}
1.1214 -LDC Rm, SPC {: CHECKPRIV(); XOP2( OP_MOV, R_R(Rm), R_SPC ); :}
1.1215 -LDC Rm, DBR {: CHECKPRIV(); XOP2( OP_MOV, R_R(Rm), R_DBR ); :}
1.1216 -LDC Rm, Rn_BANK {: CHECKPRIV(); XOP2( OP_MOV, R_R(Rm), R_BANK(Rn_BANK) ); :}
1.1217 +LDC Rm, GBR {: XOP2SS( OP_MOV, R_R(Rm), R_GBR ); :}
1.1218 +LDC Rm, VBR {: CHECKPRIV(); XOP2SS( OP_MOV, R_R(Rm), R_VBR ); :}
1.1219 +LDC Rm, SSR {: CHECKPRIV(); XOP2SS( OP_MOV, R_R(Rm), R_SSR ); :}
1.1220 +LDC Rm, SGR {: CHECKPRIV(); XOP2SS( OP_MOV, R_R(Rm), R_SGR ); :}
1.1221 +LDC Rm, SPC {: CHECKPRIV(); XOP2SS( OP_MOV, R_R(Rm), R_SPC ); :}
1.1222 +LDC Rm, DBR {: CHECKPRIV(); XOP2SS( OP_MOV, R_R(Rm), R_DBR ); :}
1.1223 +LDC Rm, Rn_BANK {: CHECKPRIV(); XOP2SS( OP_MOV, R_R(Rm), R_BANK(Rn_BANK) ); :}
1.1224 LDC.L @Rm+, GBR {:
1.1225 - XOP2E( OP_LOADL, R_R(Rm), R_GBR );
1.1226 - XOP2I( OP_ADD, 4, R_R(Rm) );
1.1227 + XOP2SSE( OP_LOADL, R_R(Rm), R_GBR );
1.1228 + XOP2IS( OP_ADD, 4, R_R(Rm) );
1.1229 :}
1.1230 LDC.L @Rm+, SR {:
1.1231 if( in_delay_slot ) {
1.1232 @@ -924,225 +962,225 @@
1.1233 } else {
1.1234 CHECKPRIV();
1.1235 RALIGN32( R_R(Rm) );
1.1236 - XOP2E( OP_LOADL, R_R(Rm), REG_TMP0 );
1.1237 - XOP2I( OP_ADD, 4, R_R(Rm) );
1.1238 - XOPCALL1( sh4_write_sr, REG_TMP0 );
1.1239 + XOP2STE( OP_LOADL, R_R(Rm), REG_TMP0 );
1.1240 + XOP2IS( OP_ADD, 4, R_R(Rm) );
1.1241 + XOPCALL1T( sh4_write_sr, REG_TMP0 );
1.1242 }
1.1243 return 2;
1.1244 :}
1.1245 LDC.L @Rm+, VBR {:
1.1246 CHECKPRIV();
1.1247 RALIGN32( R_R(Rm) );
1.1248 - XOP2E( OP_LOADL, R_R(Rm), R_VBR );
1.1249 - XOP2I( OP_ADD, 4, R_R(Rm) );
1.1250 + XOP2SSE( OP_LOADL, R_R(Rm), R_VBR );
1.1251 + XOP2IS( OP_ADD, 4, R_R(Rm) );
1.1252 :}
1.1253 LDC.L @Rm+, SSR {:
1.1254 CHECKPRIV();
1.1255 RALIGN32( R_R(Rm) );
1.1256 - XOP2E( OP_LOADL, R_R(Rm), R_SSR );
1.1257 - XOP2I( OP_ADD, 4, R_R(Rm) );
1.1258 + XOP2SSE( OP_LOADL, R_R(Rm), R_SSR );
1.1259 + XOP2IS( OP_ADD, 4, R_R(Rm) );
1.1260 :}
1.1261 LDC.L @Rm+, SGR {:
1.1262 CHECKPRIV();
1.1263 RALIGN32( R_R(Rm) );
1.1264 - XOP2E( OP_LOADL, R_R(Rm), R_SGR );
1.1265 - XOP2I( OP_ADD, 4, R_R(Rm) );
1.1266 + XOP2SSE( OP_LOADL, R_R(Rm), R_SGR );
1.1267 + XOP2IS( OP_ADD, 4, R_R(Rm) );
1.1268 :}
1.1269 LDC.L @Rm+, SPC {:
1.1270 CHECKPRIV();
1.1271 RALIGN32( R_R(Rm) );
1.1272 - XOP2E( OP_LOADL, R_R(Rm), R_SPC );
1.1273 - XOP2I( OP_ADD, 4, R_R(Rm) );
1.1274 + XOP2SSE( OP_LOADL, R_R(Rm), R_SPC );
1.1275 + XOP2IS( OP_ADD, 4, R_R(Rm) );
1.1276 :}
1.1277 LDC.L @Rm+, DBR {:
1.1278 CHECKPRIV();
1.1279 RALIGN32( R_R(Rm) );
1.1280 - XOP2E( OP_LOADL, R_R(Rm), R_DBR );
1.1281 - XOP2I( OP_ADD, 4, R_R(Rm) );
1.1282 + XOP2SSE( OP_LOADL, R_R(Rm), R_DBR );
1.1283 + XOP2IS( OP_ADD, 4, R_R(Rm) );
1.1284 :}
1.1285 LDC.L @Rm+, Rn_BANK {:
1.1286 CHECKPRIV();
1.1287 RALIGN32( R_R(Rm) );
1.1288 - XOP2E( OP_LOADL, R_R(Rm), R_BANK(Rn_BANK) );
1.1289 - XOP2I( OP_ADD, 4, R_R(Rm) );
1.1290 + XOP2SSE( OP_LOADL, R_R(Rm), R_BANK(Rn_BANK) );
1.1291 + XOP2IS( OP_ADD, 4, R_R(Rm) );
1.1292 :}
1.1293 LDS Rm, FPSCR {:
1.1294 CHECKFPUEN();
1.1295 - XOPCALL1( sh4_write_fpscr, R_R(Rm) );
1.1296 + XOPCALL1S( sh4_write_fpscr, R_R(Rm) );
1.1297 return 2;
1.1298 :}
1.1299 LDS Rm, FPUL {:
1.1300 CHECKFPUEN();
1.1301 - XOP2( OP_MOV, R_R(Rm), R_FPUL );
1.1302 + XOP2SS( OP_MOV, R_R(Rm), R_FPUL );
1.1303 :}
1.1304 -LDS Rm, MACH {: XOP2( OP_MOV, R_R(Rm), R_MACH ); :}
1.1305 -LDS Rm, MACL {: XOP2( OP_MOV, R_R(Rm), R_MACL ); :}
1.1306 -LDS Rm, PR {: XOP2( OP_MOV, R_R(Rm), R_PR ); :}
1.1307 +LDS Rm, MACH {: XOP2SS( OP_MOV, R_R(Rm), R_MACH ); :}
1.1308 +LDS Rm, MACL {: XOP2SS( OP_MOV, R_R(Rm), R_MACL ); :}
1.1309 +LDS Rm, PR {: XOP2SS( OP_MOV, R_R(Rm), R_PR ); :}
1.1310 LDS.L @Rm+, FPSCR {:
1.1311 CHECKFPUEN();
1.1312 RALIGN32( R_R(Rm) );
1.1313 - XOP2E( OP_LOADL, R_R(Rm), REG_TMP0 );
1.1314 - XOP2I( OP_ADD, 4, R_R(Rm) );
1.1315 - XOPCALL1( sh4_write_fpscr, REG_TMP0 );
1.1316 + XOP2STE( OP_LOADL, R_R(Rm), REG_TMP0 );
1.1317 + XOP2IS( OP_ADD, 4, R_R(Rm) );
1.1318 + XOPCALL1T( sh4_write_fpscr, REG_TMP0 );
1.1319 return 2;
1.1320 :}
1.1321 LDS.L @Rm+, FPUL {:
1.1322 CHECKFPUEN();
1.1323 RALIGN32( R_R(Rm) );
1.1324 - XOP2E( OP_LOADL, R_R(Rm), R_FPUL );
1.1325 - XOP2I( OP_ADD, 4, R_R(Rm) );
1.1326 + XOP2SSE( OP_LOADL, R_R(Rm), R_FPUL );
1.1327 + XOP2IS( OP_ADD, 4, R_R(Rm) );
1.1328 :}
1.1329 LDS.L @Rm+, MACH {:
1.1330 RALIGN32( R_R(Rm) );
1.1331 - XOP2E( OP_LOADL, R_R(Rm), R_MACH );
1.1332 - XOP2I( OP_ADD, 4, R_R(Rm) );
1.1333 + XOP2SSE( OP_LOADL, R_R(Rm), R_MACH );
1.1334 + XOP2IS( OP_ADD, 4, R_R(Rm) );
1.1335 :}
1.1336 LDS.L @Rm+, MACL {:
1.1337 RALIGN32( R_R(Rm) );
1.1338 - XOP2E( OP_LOADL, R_R(Rm), R_MACL );
1.1339 - XOP2I( OP_ADD, 4, R_R(Rm) );
1.1340 + XOP2SSE( OP_LOADL, R_R(Rm), R_MACL );
1.1341 + XOP2IS( OP_ADD, 4, R_R(Rm) );
1.1342 :}
1.1343 LDS.L @Rm+, PR {:
1.1344 RALIGN32( R_R(Rm) );
1.1345 - XOP2E( OP_LOADL, R_R(Rm), R_PR );
1.1346 - XOP2I( OP_ADD, 4, R_R(Rm) );
1.1347 + XOP2SSE( OP_LOADL, R_R(Rm), R_PR );
1.1348 + XOP2IS( OP_ADD, 4, R_R(Rm) );
1.1349 :}
1.1350 STC SR, Rn {:
1.1351 CHECKPRIV();
1.1352 - XOPCALLR( sh4_read_sr, R_R(Rn) );
1.1353 + XOPCALLRS( sh4_read_sr, R_R(Rn) );
1.1354 :}
1.1355 -STC GBR, Rn {: XOP2( OP_MOV, R_GBR, R_R(Rn) ); :}
1.1356 -STC VBR, Rn {: CHECKPRIV(); XOP2( OP_MOV, R_VBR, R_R(Rn) ); :}
1.1357 -STC SSR, Rn {: CHECKPRIV(); XOP2( OP_MOV, R_SSR, R_R(Rn) ); :}
1.1358 -STC SPC, Rn {: CHECKPRIV(); XOP2( OP_MOV, R_SPC, R_R(Rn) ); :}
1.1359 -STC SGR, Rn {: CHECKPRIV(); XOP2( OP_MOV, R_SGR, R_R(Rn) ); :}
1.1360 -STC DBR, Rn {: CHECKPRIV(); XOP2( OP_MOV, R_DBR, R_R(Rn) ); :}
1.1361 -STC Rm_BANK, Rn {: CHECKPRIV(); XOP2( OP_MOV, R_BANK(Rm_BANK), R_R(Rn) ); :}
1.1362 +STC GBR, Rn {: XOP2SS( OP_MOV, R_GBR, R_R(Rn) ); :}
1.1363 +STC VBR, Rn {: CHECKPRIV(); XOP2SS( OP_MOV, R_VBR, R_R(Rn) ); :}
1.1364 +STC SSR, Rn {: CHECKPRIV(); XOP2SS( OP_MOV, R_SSR, R_R(Rn) ); :}
1.1365 +STC SPC, Rn {: CHECKPRIV(); XOP2SS( OP_MOV, R_SPC, R_R(Rn) ); :}
1.1366 +STC SGR, Rn {: CHECKPRIV(); XOP2SS( OP_MOV, R_SGR, R_R(Rn) ); :}
1.1367 +STC DBR, Rn {: CHECKPRIV(); XOP2SS( OP_MOV, R_DBR, R_R(Rn) ); :}
1.1368 +STC Rm_BANK, Rn {: CHECKPRIV(); XOP2SS( OP_MOV, R_BANK(Rm_BANK), R_R(Rn) ); :}
1.1369 STC.L SR, @-Rn {:
1.1370 CHECKPRIV();
1.1371 - XOPCALLR( sh4_read_sr, REG_TMP1 );
1.1372 + XOPCALLRT( sh4_read_sr, REG_TMP1 );
1.1373 WALIGN32( R_R(Rn) );
1.1374 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.1375 - XOP2I(OP_ADD, -4, REG_TMP0 );
1.1376 - XOP2E(OP_STOREL, REG_TMP0, REG_TMP1 );
1.1377 - XOP2I(OP_ADD, -4, R_R(Rn) );
1.1378 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.1379 + XOP2IT(OP_ADD, -4, REG_TMP0 );
1.1380 + XOP2TTE(OP_STOREL, REG_TMP0, REG_TMP1 );
1.1381 + XOP2IS(OP_ADD, -4, R_R(Rn) );
1.1382 :}
1.1383 STC.L VBR, @-Rn {:
1.1384 CHECKPRIV();
1.1385 WALIGN32( R_R(Rn) );
1.1386 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.1387 - XOP2I(OP_ADD, -4, REG_TMP0 );
1.1388 - XOP2E(OP_STOREL, REG_TMP0, R_VBR );
1.1389 - XOP2I(OP_ADD, -4, R_R(Rn) );
1.1390 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.1391 + XOP2IT(OP_ADD, -4, REG_TMP0 );
1.1392 + XOP2TSE(OP_STOREL, REG_TMP0, R_VBR );
1.1393 + XOP2IS(OP_ADD, -4, R_R(Rn) );
1.1394 :}
1.1395 STC.L SSR, @-Rn {:
1.1396 CHECKPRIV();
1.1397 WALIGN32( R_R(Rn) );
1.1398 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.1399 - XOP2I(OP_ADD, -4, REG_TMP0 );
1.1400 - XOP2E(OP_STOREL, REG_TMP0, R_SSR );
1.1401 - XOP2I(OP_ADD, -4, R_R(Rn) );
1.1402 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.1403 + XOP2IT(OP_ADD, -4, REG_TMP0 );
1.1404 + XOP2TSE(OP_STOREL, REG_TMP0, R_SSR );
1.1405 + XOP2IS(OP_ADD, -4, R_R(Rn) );
1.1406 :}
1.1407 STC.L SPC, @-Rn {:
1.1408 CHECKPRIV();
1.1409 WALIGN32( R_R(Rn) );
1.1410 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.1411 - XOP2I(OP_ADD, -4, REG_TMP0 );
1.1412 - XOP2E(OP_STOREL, REG_TMP0, R_SPC );
1.1413 - XOP2I(OP_ADD, -4, R_R(Rn) );
1.1414 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.1415 + XOP2IT(OP_ADD, -4, REG_TMP0 );
1.1416 + XOP2TSE(OP_STOREL, REG_TMP0, R_SPC );
1.1417 + XOP2IS(OP_ADD, -4, R_R(Rn) );
1.1418 :}
1.1419 STC.L SGR, @-Rn {:
1.1420 CHECKPRIV();
1.1421 WALIGN32( R_R(Rn) );
1.1422 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.1423 - XOP2I(OP_ADD, -4, REG_TMP0 );
1.1424 - XOP2E(OP_STOREL, REG_TMP0, R_SGR );
1.1425 - XOP2I(OP_ADD, -4, R_R(Rn) );
1.1426 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.1427 + XOP2IT(OP_ADD, -4, REG_TMP0 );
1.1428 + XOP2TSE(OP_STOREL, REG_TMP0, R_SGR );
1.1429 + XOP2IS(OP_ADD, -4, R_R(Rn) );
1.1430 :}
1.1431 STC.L DBR, @-Rn {:
1.1432 CHECKPRIV();
1.1433 WALIGN32( R_R(Rn) );
1.1434 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.1435 - XOP2I(OP_ADD, -4, REG_TMP0 );
1.1436 - XOP2E(OP_STOREL, REG_TMP0, R_DBR );
1.1437 - XOP2I(OP_ADD, -4, R_R(Rn) );
1.1438 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.1439 + XOP2IT(OP_ADD, -4, REG_TMP0 );
1.1440 + XOP2TSE(OP_STOREL, REG_TMP0, R_DBR );
1.1441 + XOP2IS(OP_ADD, -4, R_R(Rn) );
1.1442 :}
1.1443 STC.L Rm_BANK, @-Rn {:
1.1444 CHECKPRIV();
1.1445 WALIGN32( R_R(Rn) );
1.1446 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.1447 - XOP2I(OP_ADD, -4, REG_TMP0 );
1.1448 - XOP2E(OP_STOREL, REG_TMP0, R_BANK(Rm_BANK) );
1.1449 - XOP2I(OP_ADD, -4, R_R(Rn) );
1.1450 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.1451 + XOP2IT(OP_ADD, -4, REG_TMP0 );
1.1452 + XOP2TSE(OP_STOREL, REG_TMP0, R_BANK(Rm_BANK) );
1.1453 + XOP2IS(OP_ADD, -4, R_R(Rn) );
1.1454 :}
1.1455 STC.L GBR, @-Rn {:
1.1456 WALIGN32( R_R(Rn) );
1.1457 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.1458 - XOP2I(OP_ADD, -4, REG_TMP0 );
1.1459 - XOP2E(OP_STOREL, REG_TMP0, R_GBR );
1.1460 - XOP2I(OP_ADD, -4, R_R(Rn) );
1.1461 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.1462 + XOP2IT(OP_ADD, -4, REG_TMP0 );
1.1463 + XOP2TSE(OP_STOREL, REG_TMP0, R_GBR );
1.1464 + XOP2IS(OP_ADD, -4, R_R(Rn) );
1.1465 :}
1.1466 STS FPSCR, Rn {:
1.1467 CHECKFPUEN();
1.1468 - XOP2( OP_MOV, R_FPSCR, R_R(Rn) );
1.1469 + XOP2SS( OP_MOV, R_FPSCR, R_R(Rn) );
1.1470 :}
1.1471 STS FPUL, Rn {:
1.1472 CHECKFPUEN();
1.1473 - XOP2( OP_MOV, R_FPUL, R_R(Rn) );
1.1474 + XOP2SS( OP_MOV, R_FPUL, R_R(Rn) );
1.1475 :}
1.1476 STS MACH, Rn {:
1.1477 - XOP2( OP_MOV, R_MACH, R_R(Rn) );
1.1478 + XOP2SS( OP_MOV, R_MACH, R_R(Rn) );
1.1479 :}
1.1480 STS MACL, Rn {:
1.1481 - XOP2( OP_MOV, R_MACL, R_R(Rn) );
1.1482 + XOP2SS( OP_MOV, R_MACL, R_R(Rn) );
1.1483 :}
1.1484 STS PR, Rn {:
1.1485 - XOP2( OP_MOV, R_PR, R_R(Rn) );
1.1486 + XOP2SS( OP_MOV, R_PR, R_R(Rn) );
1.1487 :}
1.1488 STS.L FPSCR, @-Rn {:
1.1489 CHECKFPUEN();
1.1490 WALIGN32( R_R(Rn) );
1.1491 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.1492 - XOP2I(OP_ADD, -4, REG_TMP0 );
1.1493 - XOP2E(OP_STOREL, REG_TMP0, R_FPSCR );
1.1494 - XOP2I(OP_ADD, -4, R_R(Rn) );
1.1495 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.1496 + XOP2IT(OP_ADD, -4, REG_TMP0 );
1.1497 + XOP2TSE(OP_STOREL, REG_TMP0, R_FPSCR );
1.1498 + XOP2IS(OP_ADD, -4, R_R(Rn) );
1.1499 :}
1.1500 STS.L FPUL, @-Rn {:
1.1501 CHECKFPUEN();
1.1502 WALIGN32( R_R(Rn) );
1.1503 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.1504 - XOP2I(OP_ADD, -4, REG_TMP0 );
1.1505 - XOP2E(OP_STOREL, REG_TMP0, R_FPUL );
1.1506 - XOP2I(OP_ADD, -4, R_R(Rn) );
1.1507 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.1508 + XOP2IT(OP_ADD, -4, REG_TMP0 );
1.1509 + XOP2TSE(OP_STOREL, REG_TMP0, R_FPUL );
1.1510 + XOP2IS(OP_ADD, -4, R_R(Rn) );
1.1511 :}
1.1512 STS.L MACH, @-Rn {:
1.1513 WALIGN32( R_R(Rn) );
1.1514 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.1515 - XOP2I(OP_ADD, -4, REG_TMP0 );
1.1516 - XOP2E(OP_STOREL, REG_TMP0, R_MACH );
1.1517 - XOP2I(OP_ADD, -4, R_R(Rn) );
1.1518 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.1519 + XOP2IT(OP_ADD, -4, REG_TMP0 );
1.1520 + XOP2TSE(OP_STOREL, REG_TMP0, R_MACH );
1.1521 + XOP2IS(OP_ADD, -4, R_R(Rn) );
1.1522 :}
1.1523 STS.L MACL, @-Rn {:
1.1524 WALIGN32( R_R(Rn) );
1.1525 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.1526 - XOP2I(OP_ADD, -4, REG_TMP0 );
1.1527 - XOP2E(OP_STOREL, REG_TMP0, R_MACL );
1.1528 - XOP2I(OP_ADD, -4, R_R(Rn) );
1.1529 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.1530 + XOP2IT(OP_ADD, -4, REG_TMP0 );
1.1531 + XOP2TSE(OP_STOREL, REG_TMP0, R_MACL );
1.1532 + XOP2IS(OP_ADD, -4, R_R(Rn) );
1.1533 :}
1.1534 STS.L PR, @-Rn {:
1.1535 WALIGN32( R_R(Rn) );
1.1536 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
1.1537 - XOP2I(OP_ADD, -4, REG_TMP0 );
1.1538 - XOP2E(OP_STOREL, REG_TMP0, R_PR );
1.1539 - XOP2I(OP_ADD, -4, R_R(Rn) );
1.1540 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
1.1541 + XOP2IT(OP_ADD, -4, REG_TMP0 );
1.1542 + XOP2TSE(OP_STOREL, REG_TMP0, R_PR );
1.1543 + XOP2IS(OP_ADD, -4, R_R(Rn) );
1.1544 :}
1.1545
1.1546 BF disp {:
1.1547 if( in_delay_slot ) {
1.1548 SLOTILLEGAL();
1.1549 } else {
1.1550 - XOP2I( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1551 - XOP2I( OP_CMP, 0, R_T );
1.1552 + XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1553 + XOP2IS( OP_CMP, 0, R_T );
1.1554 XOP2IICC( OP_BRCOND, CC_EQ, disp+pc+4-xbb->pc_begin, pc+2-xbb->pc_begin );
1.1555 }
1.1556 return 2;
1.1557 @@ -1153,16 +1191,16 @@
1.1558 return 2;
1.1559 } else {
1.1560 if( UNTRANSLATABLE(pc+2 ) ) {
1.1561 - XOP2I( OP_CMP, 0, R_T );
1.1562 + XOP2IS( OP_CMP, 0, R_T );
1.1563 XOP2IICC( OP_BRCONDDEL, CC_EQ, disp+pc+4-xbb->pc_begin, pc+4-xbb->pc_begin );
1.1564 EMU_DELAY_SLOT();
1.1565 return 2;
1.1566 } else {
1.1567 - XOP2( OP_MOV, R_T, REG_TMP2 );
1.1568 + XOP2ST( OP_MOV, R_T, REG_TMP2 );
1.1569 sh4_decode_instruction( xbb, pc+2, TRUE );
1.1570 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
1.1571 - XOP2I( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1572 - XOP2I( OP_CMP, 0, REG_TMP2 );
1.1573 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1574 + XOP2IT( OP_CMP, 0, REG_TMP2 );
1.1575 XOP2IICC( OP_BRCOND, CC_EQ, disp+pc+4-xbb->pc_begin, pc+4-xbb->pc_begin );
1.1576 }
1.1577 return 4;
1.1578 @@ -1173,8 +1211,8 @@
1.1579 if( in_delay_slot ) {
1.1580 SLOTILLEGAL();
1.1581 } else {
1.1582 - XOP2I( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1583 - XOP2I( OP_CMP, 1, R_T );
1.1584 + XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1585 + XOP2IS( OP_CMP, 1, R_T );
1.1586 XOP2IICC( OP_BRCOND, CC_EQ, disp+pc+4-xbb->pc_begin, pc+2-xbb->pc_begin );
1.1587 }
1.1588 return 2;
1.1589 @@ -1185,16 +1223,16 @@
1.1590 return 2;
1.1591 } else {
1.1592 if( UNTRANSLATABLE(pc+2 ) ) {
1.1593 - XOP2I( OP_CMP, 1, R_T );
1.1594 + XOP2IS( OP_CMP, 1, R_T );
1.1595 XOP2IICC( OP_BRCONDDEL, CC_EQ, disp+pc+4-xbb->pc_begin, pc+2-xbb->pc_begin );
1.1596 EMU_DELAY_SLOT();
1.1597 return 2;
1.1598 } else {
1.1599 - XOP2( OP_MOV, R_T, REG_TMP2 );
1.1600 + XOP2ST( OP_MOV, R_T, REG_TMP2 );
1.1601 sh4_decode_instruction( xbb, pc+2, TRUE );
1.1602 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
1.1603 - XOP2I( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1604 - XOP2I( OP_CMP, 1, REG_TMP2 );
1.1605 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1606 + XOP2IT( OP_CMP, 1, REG_TMP2 );
1.1607 XOP2IICC( OP_BRCOND, CC_EQ, disp+pc+4-xbb->pc_begin, pc+4-xbb->pc_begin );
1.1608 }
1.1609 return 4;
1.1610 @@ -1207,14 +1245,14 @@
1.1611 return 2;
1.1612 } else {
1.1613 if( UNTRANSLATABLE(pc+2) ) {
1.1614 - XOP2( OP_MOV, R_PC, R_NEW_PC );
1.1615 - XOP2I( OP_ADD, pc+disp+4-xbb->pc_begin, R_NEW_PC );
1.1616 + XOP2SS( OP_MOV, R_PC, R_NEW_PC );
1.1617 + XOP2IS( OP_ADD, pc+disp+4-xbb->pc_begin, R_NEW_PC );
1.1618 EMU_DELAY_SLOT();
1.1619 return 2;
1.1620 } else {
1.1621 sh4_decode_instruction( xbb, pc+2, TRUE );
1.1622 if( xbb->ir_ptr->prev == NULL || !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
1.1623 - XOP2I( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1624 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1625 XOP1I( OP_BRREL, pc+disp+4-xbb->pc_begin );
1.1626 }
1.1627 return 4;
1.1628 @@ -1226,18 +1264,18 @@
1.1629 SLOTILLEGAL();
1.1630 return 2;
1.1631 } else {
1.1632 - XOP2( OP_MOV, R_R(Rn), REG_TMP2 );
1.1633 - XOP2( OP_ADD, R_PC, REG_TMP2 );
1.1634 - XOP2I( OP_ADD, pc - xbb->pc_begin + 4, REG_TMP2 );
1.1635 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP2 );
1.1636 + XOP2ST( OP_ADD, R_PC, REG_TMP2 );
1.1637 + XOP2IT( OP_ADD, pc - xbb->pc_begin + 4, REG_TMP2 );
1.1638 if( UNTRANSLATABLE(pc+2) ) {
1.1639 - XOP2( OP_MOV, REG_TMP2, R_NEW_PC );
1.1640 + XOP2TS( OP_MOV, REG_TMP2, R_NEW_PC );
1.1641 EMU_DELAY_SLOT();
1.1642 return 2;
1.1643 } else {
1.1644 sh4_decode_instruction( xbb, pc + 2, TRUE );
1.1645 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
1.1646 - XOP2I( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1647 - XOP1( OP_BR, REG_TMP2 );
1.1648 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1649 + XOP1T( OP_BR, REG_TMP2 );
1.1650 }
1.1651 return 4;
1.1652 }
1.1653 @@ -1248,17 +1286,17 @@
1.1654 SLOTILLEGAL();
1.1655 return 2;
1.1656 } else {
1.1657 - XOP2( OP_MOV, R_PC, R_PR );
1.1658 - XOP2I( OP_ADD, pc - xbb->pc_begin + 4, R_PR );
1.1659 + XOP2SS( OP_MOV, R_PC, R_PR );
1.1660 + XOP2IS( OP_ADD, pc - xbb->pc_begin + 4, R_PR );
1.1661 if( UNTRANSLATABLE(pc+2) ) {
1.1662 - XOP2( OP_MOV, R_PC, R_NEW_PC );
1.1663 - XOP2I( OP_ADD, pc+disp+4-xbb->pc_begin, R_NEW_PC );
1.1664 + XOP2SS( OP_MOV, R_PC, R_NEW_PC );
1.1665 + XOP2IS( OP_ADD, pc+disp+4-xbb->pc_begin, R_NEW_PC );
1.1666 EMU_DELAY_SLOT();
1.1667 return 2;
1.1668 } else {
1.1669 sh4_decode_instruction( xbb, pc+2, TRUE );
1.1670 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
1.1671 - XOP2I( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1672 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1673 XOP1I( OP_BRREL, pc+disp+4-xbb->pc_begin );
1.1674 }
1.1675 return 4;
1.1676 @@ -1270,20 +1308,20 @@
1.1677 SLOTILLEGAL();
1.1678 return 2;
1.1679 } else {
1.1680 - XOP2( OP_MOV, R_PC, R_PR );
1.1681 - XOP2I( OP_ADD, pc - xbb->pc_begin + 4, R_PR );
1.1682 - XOP2( OP_MOV, R_R(Rn), REG_TMP2 );
1.1683 - XOP2( OP_ADD, R_PC, REG_TMP2 );
1.1684 - XOP2I( OP_ADD, pc - xbb->pc_begin + 4, REG_TMP2 );
1.1685 + XOP2SS( OP_MOV, R_PC, R_PR );
1.1686 + XOP2IS( OP_ADD, pc - xbb->pc_begin + 4, R_PR );
1.1687 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP2 );
1.1688 + XOP2ST( OP_ADD, R_PC, REG_TMP2 );
1.1689 + XOP2IT( OP_ADD, pc - xbb->pc_begin + 4, REG_TMP2 );
1.1690 if( UNTRANSLATABLE(pc+2) ) {
1.1691 - XOP2( OP_MOV, REG_TMP2, R_NEW_PC );
1.1692 + XOP2TS( OP_MOV, REG_TMP2, R_NEW_PC );
1.1693 EMU_DELAY_SLOT();
1.1694 return 2;
1.1695 } else {
1.1696 sh4_decode_instruction( xbb, pc+2, TRUE );
1.1697 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
1.1698 - XOP2I( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1699 - XOP1( OP_BR, REG_TMP2 );
1.1700 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1701 + XOP1T( OP_BR, REG_TMP2 );
1.1702 }
1.1703 return 4;
1.1704 }
1.1705 @@ -1295,15 +1333,15 @@
1.1706 return 2;
1.1707 } else {
1.1708 if( UNTRANSLATABLE(pc+2) ) {
1.1709 - XOP2( OP_MOV, R_R(Rn), R_NEW_PC );
1.1710 + XOP2SS( OP_MOV, R_R(Rn), R_NEW_PC );
1.1711 EMU_DELAY_SLOT();
1.1712 return 2;
1.1713 } else {
1.1714 - XOP2( OP_MOV, R_R(Rn), REG_TMP2 );
1.1715 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP2 );
1.1716 sh4_decode_instruction( xbb, pc+2, TRUE );
1.1717 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
1.1718 - XOP2I( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1719 - XOP1( OP_BR, REG_TMP2 );
1.1720 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1721 + XOP1T( OP_BR, REG_TMP2 );
1.1722 }
1.1723 return 4;
1.1724 }
1.1725 @@ -1314,18 +1352,18 @@
1.1726 SLOTILLEGAL();
1.1727 return 2;
1.1728 } else {
1.1729 - XOP2( OP_MOV, R_PC, R_PR );
1.1730 - XOP2I( OP_ADD, pc - xbb->pc_begin + 4, R_PR );
1.1731 + XOP2SS( OP_MOV, R_PC, R_PR );
1.1732 + XOP2IS( OP_ADD, pc - xbb->pc_begin + 4, R_PR );
1.1733 if( UNTRANSLATABLE(pc+2) ) {
1.1734 - XOP2( OP_MOV, R_R(Rn), R_NEW_PC );
1.1735 + XOP2SS( OP_MOV, R_R(Rn), R_NEW_PC );
1.1736 EMU_DELAY_SLOT();
1.1737 return 2;
1.1738 } else {
1.1739 - XOP2( OP_MOV, R_R(Rn), REG_TMP2 );
1.1740 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP2 );
1.1741 sh4_decode_instruction( xbb, pc+2, TRUE );
1.1742 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
1.1743 - XOP2I( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1744 - XOP1( OP_BR, REG_TMP2 );
1.1745 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1746 + XOP1T( OP_BR, REG_TMP2 );
1.1747 }
1.1748 return 4;
1.1749 }
1.1750 @@ -1338,16 +1376,16 @@
1.1751 return 2;
1.1752 } else {
1.1753 if( UNTRANSLATABLE(pc+2) ) {
1.1754 - XOP2( OP_MOV, R_SPC, R_NEW_PC );
1.1755 + XOP2SS( OP_MOV, R_SPC, R_NEW_PC );
1.1756 EMU_DELAY_SLOT();
1.1757 return 2;
1.1758 } else {
1.1759 - XOP2( OP_MOV, R_SPC, REG_TMP2 );
1.1760 - XOPCALL1( sh4_write_sr, R_SSR );
1.1761 + XOP2ST( OP_MOV, R_SPC, REG_TMP2 );
1.1762 + XOPCALL1S( sh4_write_sr, R_SSR );
1.1763 sh4_decode_instruction( xbb, pc+2, TRUE );
1.1764 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
1.1765 - XOP2I( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1766 - XOP1( OP_BR, REG_TMP2 );
1.1767 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1768 + XOP1T( OP_BR, REG_TMP2 );
1.1769 }
1.1770 return 4;
1.1771 }
1.1772 @@ -1359,15 +1397,15 @@
1.1773 return 2;
1.1774 } else {
1.1775 if( UNTRANSLATABLE(pc+2) ) {
1.1776 - XOP2( OP_MOV, R_PR, R_NEW_PC );
1.1777 + XOP2SS( OP_MOV, R_PR, R_NEW_PC );
1.1778 EMU_DELAY_SLOT();
1.1779 return 2;
1.1780 } else {
1.1781 - XOP2( OP_MOV, R_PR, REG_TMP2 );
1.1782 + XOP2ST( OP_MOV, R_PR, REG_TMP2 );
1.1783 sh4_decode_instruction( xbb, pc+2, TRUE );
1.1784 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
1.1785 - XOP2I( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1786 - XOP1( OP_BR, REG_TMP2 );
1.1787 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.1788 + XOP1T( OP_BR, REG_TMP2 );
1.1789 }
1.1790 return 4;
1.1791 }
.