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lxdream.org :: lxdream/src/xlat/x86/x86op.h :: diff
lxdream 0.9.1
released Jun 29
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filename src/xlat/x86/x86op.h
changeset 1011:fdd58619b760
prev1006:3a169c224c12
author nkeynes
date Sun Apr 12 07:24:45 2009 +0000 (13 years ago)
branchxlat-refactor
permissions -rw-r--r--
last change Restructure operand types -
rename to forms to avoid conflict for actual data types
temporary operands are now a first class form
remove explicit types for immediates - now implied by opcode
Initial work on promote-source-reg pass
file annotate diff log raw
1.1 --- a/src/xlat/x86/x86op.h Tue Apr 07 10:55:03 2009 +0000
1.2 +++ b/src/xlat/x86/x86op.h Sun Apr 12 07:24:45 2009 +0000
1.3 @@ -317,16 +317,16 @@
1.4 #define x86_encode_r32_mem32(opcode,rr,rb,rx,ss,disp32) x86_encode_modrm(0,opcode,rr,rb,rx,ss,disp32)
1.5 #define x86_encode_r64_mem64(opcode,rr,rb,rx,ss,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,rb,rx,ss,disp32)
1.6 #define x86_encode_rptr_memptr(opcode,rr,rb,rx,ss,disp32) x86_encode_modrm(PREF_PTR,opcode,rr,rb,rx,ss,disp32)
1.7 -#define x86_encode_r32_mem32disp32(opcode,rr,rb,disp32) x86_encode_modrm(0,opcode,rr,rb,-1,0,disp32)
1.8 -#define x86_encode_r64_mem64disp64(opcode,rr,rb,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,rb,-1,0,disp32)
1.9 +#define x86_encode_r32_r32disp32(opcode,rr,rb,disp32) x86_encode_modrm(0,opcode,rr,rb,-1,0,disp32)
1.10 +#define x86_encode_r64_r64disp32(opcode,rr,rb,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,rb,-1,0,disp32)
1.11 #define x86_encode_r32_ripdisp32(opcode,rr,disp32) x86_encode_modrm_rip(0,opcode,rr,disp32)
1.12 #define x86_encode_r64_ripdisp64(opcode,rr,disp32) x86_encode_modrm_rip(PREF_REXW,opcode,rr,disp32)
1.13
1.14 /* Convenience versions for the common rbp/rsp relative displacements */
1.15 #define x86_encode_r32_rbpdisp32(opcode,rr,disp32) x86_encode_modrm(0,opcode,rr,REG_RBP,-1,0,disp32)
1.16 -#define x86_encode_r64_rbpdisp64(opcode,rr,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,REG_RBP,-1,0,disp32)
1.17 +#define x86_encode_r64_rbpdisp32(opcode,rr,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,REG_RBP,-1,0,disp32)
1.18 #define x86_encode_r32_rspdisp32(opcode,rr,disp32) x86_encode_modrm(0,opcode,rr,REG_RSP,-1,0,disp32)
1.19 -#define x86_encode_r64_rspdisp64(opcode,rr,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,REG_RSP,-1,0,disp32)
1.20 +#define x86_encode_r64_rspdisp32(opcode,rr,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,REG_RSP,-1,0,disp32)
1.21
1.22 /* Immediate-selection variants (for instructions with imm8s/imm32 variants) */
1.23 #define x86_encode_imms_rm32(opcode8,opcode32,reg,imm,rb) \
1.24 @@ -342,11 +342,11 @@
1.25 if( IS_INT8(((int32_t)imm)) ) { x86_encode_r32_rbpdisp32(opcode8,reg,disp); OP((int8_t)imm); \
1.26 } else { x86_encode_r32_rbpdisp32(opcode32,reg,disp); OP32(imm); }
1.27 #define x86_encode_imms_r32disp32(opcode8,opcode32,reg,imm,rb,disp) \
1.28 - if( IS_INT8(((int32_t)imm)) ) { x86_encode_r32_mem32disp32(opcode8,reg,rb,disp); OP((int8_t)imm); \
1.29 - } else { x86_encode_r32_mem32disp32(opcode32,reg,rb,disp); OP32(imm); }
1.30 -#define x86_encode_imms_rbpdisp64(opcode8,opcode32,reg,imm,disp) \
1.31 - if( IS_INT8(((int32_t)imm)) ) { x86_encode_r64_rbpdisp64(opcode8,reg,disp); OP((int8_t)imm); \
1.32 - } else { x86_encode_r64_rbpdisp64(opcode32,reg,disp); OP32(imm); }
1.33 + if( IS_INT8(((int32_t)imm)) ) { x86_encode_r32_r32disp32(opcode8,reg,rb,disp); OP((int8_t)imm); \
1.34 + } else { x86_encode_r32_r32disp32(opcode32,reg,rb,disp); OP32(imm); }
1.35 +#define x86_encode_imms_r64disp32(opcode8,opcode32,reg,imm,rb,disp) \
1.36 + if( IS_INT8(((int32_t)imm)) ) { x86_encode_r64_r64disp32(opcode8,reg,rb,disp); OP((int8_t)imm); \
1.37 + } else { x86_encode_r64_r64disp32(opcode32,reg,rb,disp); OP32(imm); }
1.38
1.39 /*************************** Instruction definitions ***********************/
1.40 /* Note this does not try to be an exhaustive definition of the instruction -
1.41 @@ -356,9 +356,12 @@
1.42 #define ADCB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 2, r1); OP(imm)
1.43 #define ADCB_r8_r8(r1,r2) x86_encode_r32_rm32(0x10, r1, r2)
1.44 #define ADCL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 2, imm, r1)
1.45 +#define ADCL_imms_r32disp(imm,rb,d) x86_encode_imms_r32disp32(0x83, 0x81, 2, imm, rb, d)
1.46 #define ADCL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83, 0x81, 2, imm, disp)
1.47 #define ADCL_r32_r32(r1,r2) x86_encode_r32_rm32(0x11, r1, r2)
1.48 +#define ADCL_r32_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x11, r1, rb, d)
1.49 #define ADCL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x11, r1, disp)
1.50 +#define ADCL_r32disp_r32(rb,disp,r1) x86_encode_r32_r32disp32(0x13, r1, rb, disp)
1.51 #define ADCL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x13, r1, disp)
1.52 #define ADCQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 2, imm, r1)
1.53 #define ADCQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x11, r1, r2)
1.54 @@ -369,8 +372,9 @@
1.55 #define ADDL_imms_r32disp(imm,rb,d) x86_encode_imms_r32disp32(0x83, 0x81, 0, imm, rb, d)
1.56 #define ADDL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83, 0x81, 0, imm, disp)
1.57 #define ADDL_r32_r32(r1,r2) x86_encode_r32_rm32(0x01, r1, r2)
1.58 +#define ADDL_r32_r32disp(r1,r2,dsp) x86_encode_r32_r32disp32(0x01, r1, r2, dsp)
1.59 #define ADDL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x01, r1, disp)
1.60 -#define ADDL_r32_r32disp(r1,r2,dsp) x86_encode_r32_mem32disp32(0x01, r1, r2, dsp)
1.61 +#define ADDL_r32disp_r32(rb,disp,r1) x86_encode_r32_r32disp32(0x03, r1, rb, disp)
1.62 #define ADDL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x03, r1, disp)
1.63 #define ADDQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 0, imm, r1)
1.64 #define ADDQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x01, r1, r2)
1.65 @@ -378,9 +382,12 @@
1.66 #define ANDB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 4, r1); OP(imm)
1.67 #define ANDB_r8_r8(r1,r2) x86_encode_r32_rm32(0x20, r1, r2)
1.68 #define ANDL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 4, imm, r1)
1.69 +#define ANDL_imms_r32disp(imm,rb,d) x86_encode_imms_r32disp32(0x83,0x81,4,imm,rb,d)
1.70 #define ANDL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83,0x81,4,imm,disp)
1.71 #define ANDL_r32_r32(r1,r2) x86_encode_r32_rm32(0x21, r1, r2)
1.72 +#define ANDL_r32_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x21, r1, rb, d)
1.73 #define ANDL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x21, r1, disp)
1.74 +#define ANDL_r32disp_r32(rb,d,r1) x86_encode_r32_r32disp32(0x23, r1, rb, d)
1.75 #define ANDL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x23, r1, disp)
1.76 #define ANDQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x21, r1, r2)
1.77 #define ANDQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 4, imm, r1)
1.78 @@ -393,16 +400,21 @@
1.79 #define CLD() OP(0xFC)
1.80 #define CMC() OP(0xF5)
1.81
1.82 -#define CMOVCCL_cc_r32_r32(cc,r1,r2) x86_encode_r32_rm32(0x0F40+(cc), r2, r1)
1.83 -#define CMOVCCL_cc_rbpdisp_r32(cc,d,r1) x86_encode_r32_rbpdisp32(0x0F40+(cc), r1, d)
1.84 +#define CMOVCCL_cc_r32_r32(cc,r1,r2) x86_encode_r32_rm32(0x0F40+(cc), r2, r1)
1.85 +#define CMOVCCL_cc_r32disp_r32(cc,rb,d,r1) x86_encode_r32_r32disp32(0x0F40+(cc), r1, rb, d)
1.86 +#define CMOVCCL_cc_rbpdisp_r32(cc,d,r1) x86_encode_r32_rbpdisp32(0x0F40+(cc), r1, d)
1.87
1.88 #define CMPB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 7, r1); OP(imm)
1.89 +#define CMPB_imms_r32disp(imm,rb,d) x86_encode_r32_r32disp32(0x80, 7, rb, d); OP(imm)
1.90 #define CMPB_imms_rbpdisp(imm,disp) x86_encode_r32_rbpdisp32(0x80, 7, disp); OP(imm)
1.91 #define CMPB_r8_r8(r1,r2) x86_encode_r32_rm32(0x38, r1, r2)
1.92 #define CMPL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 7, imm, r1)
1.93 +#define CMPL_imms_r32disp(imm,rb,d) x86_encode_imms_r32disp32(0x83, 0x81, 7, imm, rb, d)
1.94 #define CMPL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83, 0x81, 7, imm, disp)
1.95 #define CMPL_r32_r32(r1,r2) x86_encode_r32_rm32(0x39, r1, r2)
1.96 +#define CMPL_r32_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x39, r1, rb, d)
1.97 #define CMPL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x39, r1, disp)
1.98 +#define CMPL_r32disp_r32(rb,d,r1) x86_encode_r32_r32disp32(0x3B, r1, rb, d)
1.99 #define CMPL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x3B, r1, disp)
1.100 #define CMPQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 7, imm, r1)
1.101 #define CMPQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x39, r1, r2)
1.102 @@ -411,60 +423,71 @@
1.103 #define CDOQ() OP(PREF_REXW); OP(0x99)
1.104
1.105 #define DECL_r32(r1) x86_encode_r32_rm32(0xFF,1,r1) /* NB single-op form unavailable in 64-bit mode */
1.106 +#define DECL_r32disp(rb,d) x86_encode_r32_r32disp32(0xFF,1,rb,d)
1.107 #define DECL_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xFF,1,disp)
1.108 #define DECQ_r64(r1) x86_encode_r64_rm64(0xFF,1,r1)
1.109 -#define DECQ_rbpdisp(disp) x86_encode_r64_rbpdisp64(0xFF,1,disp)
1.110 +#define DECQ_r64disp(rb,d) x86_encode_r64_r64disp32(0xFF,1,rb,d)
1.111 +#define DECQ_rbpdisp(disp) x86_encode_r64_rbpdisp32(0xFF,1,disp)
1.112
1.113 #define IDIVL_r32(r1) x86_encode_r32_rm32(0xF7, 7, r1)
1.114 +#define IDIVL_r32disp(rb,d) x86_encode_r32_r32disp32(0xF7, 7, rb, d)
1.115 #define IDIVL_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xF7, 7, disp)
1.116 #define IDIVQ_r64(r1) x86_encode_r64_rm64(0xF7, 7, r1)
1.117
1.118 #define IMULL_imms_r32(imm,r1) x86_encode_imms_rm32(0x6B,0x69, r1, imm, r1)
1.119 #define IMULL_r32(r1) x86_encode_r32_rm32(0xF7, 5, r1)
1.120 #define IMULL_r32_r32(r1,r2) x86_encode_r32_rm32(0x0FAF, r2, r1)
1.121 +#define IMULL_r32disp(rb,d) x86_encode_r32_r32disp32(0xF7, 5, rb, d)
1.122 +#define IMULL_r32disp_r32(rb,d,r1) x86_encode_r32_r32disp32(0x0FAF, r1, rb, d)
1.123 #define IMULL_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xF7, 5, disp)
1.124 #define IMULL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x0FAF, r1, disp)
1.125 #define IMULL_rspdisp(disp) x86_encode_r32_rspdisp32(0xF7, 5, disp)
1.126 #define IMULL_rspdisp_r32(disp,r1) x86_encode_r32_rspdisp32(0x0FAF, r1, disp)
1.127 #define IMULQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x6B,0x69, r1, imm, r1)
1.128 #define IMULQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x0FAF, r2, r1)
1.129 -#define IMULQ_rbpdisp_r64(disp,r1) x86_encode_r64_rbpdisp64(0x0FAF, r1, disp)
1.130 +#define IMULQ_r64disp_r64(rb,d,r1) x86_encode_r64_r64disp32(0x0FAF, r1, rb, d)
1.131 +#define IMULQ_rbpdisp_r64(disp,r1) x86_encode_r64_rbpdisp32(0x0FAF, r1, disp)
1.132
1.133 #define INCL_r32(r1) x86_encode_r32_rm32(0xFF,0,r1) /* NB single-op form unavailable in 64-bit mode */
1.134 +#define INCL_r32disp(rb,d) x86_encode_r32_r32disp32(0xFF,0,rb,d)
1.135 #define INCL_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xFF,0,disp)
1.136 #define INCQ_r64(r1) x86_encode_r64_rm64(0xFF,0,r1)
1.137 -#define INCQ_rbpdisp(disp) x86_encode_r64_rbpdisp64(0xFF,0,disp)
1.138 +#define INCQ_r64disp(rb,d) x86_encode_r64_r64disp32(0xFF,0,rb,d)
1.139 +#define INCQ_rbpdisp(disp) x86_encode_r64_rbpdisp32(0xFF,0,disp)
1.140
1.141 #define LEAL_r32disp_r32(r1,disp,r2) x86_encode_r32_mem32(0x8D, r2, r1, -1, 0, disp)
1.142 #define LEAL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x8D, r1, disp)
1.143 #define LEAL_sib_r32(ss,ii,bb,d,r1) x86_encode_r32_mem32(0x8D, r1, bb, ii, ss, d)
1.144 -#define LEAQ_r64disp_r64(r1,disp,r2) x86_encode_r64_mem64(0x8D, r2, r1, -1, 0, disp)
1.145 -#define LEAQ_rbpdisp_r64(disp,r1) x86_encode_r64_rbpdisp64(0x8D, r1, disp)
1.146 +#define LEAQ_r64disp_r64(r1,disp,r2) x86_encode_r64_r64disp32(0x8D, r2, r1, disp)
1.147 +#define LEAQ_rbpdisp_r64(disp,r1) x86_encode_r64_rbpdisp32(0x8D, r1, disp)
1.148 #define LEAP_rptrdisp_rptr(r1,d,r2) x86_encode_rptr_memptr(0x8D, r2, r1, -1, 0, disp)
1.149 #define LEAP_rbpdisp_rptr(disp,r1) x86_encode_rptr_memptr(0x8D, r1, REG_RBP, -1, 0, disp)
1.150 #define LEAP_sib_rptr(ss,ii,bb,d,r1) x86_encode_rptr_memptr(0x8D, r1, bb, ii, ss, d)
1.151
1.152 #define MOVB_r8_r8(r1,r2) x86_encode_r32_rm32(0x88, r1, r2)
1.153 #define MOVL_imm32_r32(i32,r1) x86_encode_opcode32(0xB8, r1); OP32(i32)
1.154 +#define MOVL_imm32_r32disp(i,rb,d) x86_encode_r32_r32disp32(0xC7,0,rb,d); OP32(i)
1.155 #define MOVL_imm32_rbpdisp(i,disp) x86_encode_r32_rbpdisp32(0xC7,0,disp); OP32(i)
1.156 #define MOVL_imm32_rspdisp(i,disp) x86_encode_r32_rspdisp32(0xC7,0,disp); OP32(i)
1.157 #define MOVL_moffptr_eax(p) OP(0xA1); OPPTR(p)
1.158 #define MOVL_r32_r32(r1,r2) x86_encode_r32_rm32(0x89, r1, r2)
1.159 -#define MOVL_r32_r32disp(r1,r2,dsp) x86_encode_r32_mem32disp32(0x89, r1, r2, dsp)
1.160 +#define MOVL_r32_r32disp(r1,r2,dsp) x86_encode_r32_r32disp32(0x89, r1, r2, dsp)
1.161 #define MOVL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x89, r1, disp)
1.162 #define MOVL_r32_rspdisp(r1,disp) x86_encode_r32_rspdisp32(0x89, r1, disp)
1.163 #define MOVL_r32_sib(r1,ss,ii,bb,d) x86_encode_r32_mem32(0x89, r1, bb, ii, ss, d)
1.164 -#define MOVL_r32disp_r32(r1,dsp,r2) x86_encode_r32_mem32disp32(0x8B, r2, r1, dsp)
1.165 +#define MOVL_r32disp_r32(r1,dsp,r2) x86_encode_r32_r32disp32(0x8B, r2, r1, dsp)
1.166 #define MOVL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x8B, r1, disp)
1.167 #define MOVL_rspdisp_r32(disp,r1) x86_encode_r32_rspdisp32(0x8B, r1, disp)
1.168 #define MOVL_sib_r32(ss,ii,bb,d,r1) x86_encode_r32_mem32(0x8B, r1, bb, ii, ss, d)
1.169 #define MOVQ_imm64_r64(i64,r1) x86_encode_opcode64(0xB8, r1); OP64(i64)
1.170 #define MOVQ_moffptr_rax(p) OP(PREF_REXW); OP(0xA1); OPPTR(p)
1.171 #define MOVQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x89, r1, r2)
1.172 -#define MOVQ_r64_rbpdisp(r1,disp) x86_encode_r64_rbpdisp64(0x89, r1, disp)
1.173 -#define MOVQ_r64_rspdisp(r1,disp) x86_encode_r64_rspdisp64(0x89, r1, disp)
1.174 -#define MOVQ_rbpdisp_r64(disp,r1) x86_encode_r64_rbpdisp64(0x8B, r1, disp)
1.175 -#define MOVQ_rspdisp_r64(disp,r1) x86_encode_r64_rspdisp64(0x8B, r1, disp)
1.176 +#define MOVQ_r64_r64disp(r1,rb,d) x86_encode_r64_r64disp32(0x89, r1, rb, d)
1.177 +#define MOVQ_r64_rbpdisp(r1,disp) x86_encode_r64_rbpdisp32(0x89, r1, disp)
1.178 +#define MOVQ_r64_rspdisp(r1,disp) x86_encode_r64_rspdisp32(0x89, r1, disp)
1.179 +#define MOVQ_r64disp_r64(rb,d,r1) x86_encode_r64_r64disp32(0x8B, r1, rb, d)
1.180 +#define MOVQ_rbpdisp_r64(disp,r1) x86_encode_r64_rbpdisp32(0x8B, r1, disp)
1.181 +#define MOVQ_rspdisp_r64(disp,r1) x86_encode_r64_rspdisp32(0x8B, r1, disp)
1.182 #define MOVP_immptr_rptr(p,r1) x86_encode_opcodereg( PREF_PTR, 0xB8, r1); OPPTR(p)
1.183 #define MOVP_moffptr_rax(p) if( sizeof(void*)==8 ) { OP(PREF_REXW); } OP(0xA1); OPPTR(p)
1.184 #define MOVP_rptr_rptr(r1,r2) x86_encode_reg_rm(PREF_PTR, 0x89, r1, r2)
1.185 @@ -472,39 +495,50 @@
1.186
1.187 #define MOVSXL_r8_r32(r1,r2) x86_encode_r32_rm32(0x0FBE, r2, r1)
1.188 #define MOVSXL_r16_r32(r1,r2) x86_encode_r32_rm32(0x0FBF, r2, r1)
1.189 +#define MOVSXL_r32disp8_r32(r,d,r1) x86_encode_r32_r32disp32(0x0FBE, r1, r, d)
1.190 +#define MOVSXL_r32disp16_r32(r,d,r1) x86_encode_r32_r32disp32(0x0FBF, r1, r, d)
1.191 #define MOVSXL_rbpdisp8_r32(disp,r1) x86_encode_r32_rbpdisp32(0x0FBE, r1, disp)
1.192 #define MOVSXL_rbpdisp16_r32(dsp,r1) x86_encode_r32_rbpdisp32(0x0FBF, r1, dsp)
1.193 #define MOVSXQ_imm32_r64(i32,r1) x86_encode_r64_rm64(0xC7, 0, r1); OP32(i32) /* Technically a MOV */
1.194 #define MOVSXQ_r8_r64(r1,r2) x86_encode_r64_rm64(0x0FBE, r2, r1)
1.195 #define MOVSXQ_r16_r64(r1,r2) x86_encode_r64_rm64(0x0FBF, r2, r1)
1.196 #define MOVSXQ_r32_r64(r1,r2) x86_encode_r64_rm64(0x63, r2, r1)
1.197 -#define MOVSXQ_rbpdisp32_r64(dsp,r1) x86_encode_r64_rbpdisp64(0x63, r1, dsp)
1.198 +#define MOVSXQ_r64disp32_r64(r,d,r1) x86_encode_r64_r64disp32(0x63, r1, r, d)
1.199 +#define MOVSXQ_rbpdisp32_r64(dsp,r1) x86_encode_r64_rbpdisp32(0x63, r1, dsp)
1.200
1.201 #define MOVZXL_r8_r32(r1,r2) x86_encode_r32_rm32(0x0FB6, r2, r1)
1.202 #define MOVZXL_r16_r32(r1,r2) x86_encode_r32_rm32(0x0FB7, r2, r1)
1.203 +#define MOVZXL_r32disp8_r32(r,d,r1) x86_encode_r32_r32disp32(0x0FB6, r1, r, d)
1.204 +#define MOVZXL_r32disp16_r32(r,d,r1) x86_encode_r32_r32disp32(0x0FB7, r1, r, d)
1.205 #define MOVZXL_rbpdisp8_r32(disp,r1) x86_encode_r32_rbpdisp32(0x0FB6, r1, disp)
1.206 #define MOVZXL_rbpdisp16_r32(dsp,r1) x86_encode_r32_rbpdisp32(0x0FB7, r1, dsp)
1.207
1.208 #define MULL_r32(r1) x86_encode_r32_rm32(0xF7, 4, r1)
1.209 +#define MULL_r32disp(rb,d) x86_encode_r32_r32disp32(0xF7,4,rb,d)
1.210 #define MULL_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xF7,4,disp)
1.211 #define MULL_rspdisp(disp) x86_encode_r32_rspdisp32(0xF7,4,disp)
1.212
1.213 #define NEGB_r8(r1) x86_encode_r32_rm32(0xF6, 3, r1)
1.214 #define NEGL_r32(r1) x86_encode_r32_rm32(0xF7, 3, r1)
1.215 +#define NEGL_r32disp(rb,d) x86_encode_r32_r32disp32(0xF7, 3, rb, d)
1.216 #define NEGL_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xF7, 3, disp)
1.217 #define NEGQ_r64(r1) x86_encode_r64_rm64(0xF7, 3, r1)
1.218
1.219 #define NOTB_r8(r1) x86_encode_r32_rm32(0xF6, 2, r1)
1.220 #define NOTL_r32(r1) x86_encode_r32_rm32(0xF7, 2, r1)
1.221 +#define NOTL_r32disp(rb,d) x86_encode_r32_r32disp32(0xF7, 2, rb, d)
1.222 #define NOTL_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xF7, 2, disp)
1.223 #define NOTQ_r64(r1) x86_encode_r64_rm64(0xF7, 2, r1)
1.224
1.225 #define ORB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 1, r1); OP(imm)
1.226 #define ORB_r8_r8(r1,r2) x86_encode_r32_rm32(0x08, r1, r2)
1.227 #define ORL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 1, imm, r1)
1.228 +#define ORL_imms_r32disp(imm,rb,d) x86_encode_imms_r32disp32(0x83,0x81,1,imm,rb,d)
1.229 #define ORL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83,0x81,1,imm,disp)
1.230 #define ORL_r32_r32(r1,r2) x86_encode_r32_rm32(0x09, r1, r2)
1.231 +#define ORL_r32_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x09, r1, rb, d)
1.232 #define ORL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x09, r1, disp)
1.233 +#define ORL_r32disp_r32(rb,d,r1) x86_encode_r32_r32disp32(0x0B, r1, rb, d)
1.234 #define ORL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x0B, r1, disp)
1.235 #define ORQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 1, imm, r1)
1.236 #define ORQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x09, r1, r2)
1.237 @@ -515,97 +549,101 @@
1.238 #define PUSH_r32(r1) x86_encode_opcode32(0x50, r1)
1.239
1.240 #define RCLL_cl_r32(r1) x86_encode_r32_rm32(0xD3,2,r1)
1.241 -#define RCLL_cl_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xD3,2,disp)
1.242 +#define RCLL_cl_r32disp(rb,d) x86_encode_r32_r32disp32(0xD3,2,rb,d)
1.243 #define RCLL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,2,r1); } else { x86_encode_r32_rm32(0xC1,2,r1); OP(imm); }
1.244 -#define RCLL_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r32_rbpdisp32(0xD1,2,disp); } else { x86_encode_r32_rbpdisp32(0xC1,2,disp); OP(imm); }
1.245 +#define RCLL_imm_r32disp(imm,rb,d) if( imm == 1 ) { x86_encode_r32_r32disp32(0xD1,2,rb,d); } else { x86_encode_r32_r32disp32(0xC1,2,rb,d); OP(imm); }
1.246 #define RCLQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,2,r1)
1.247 -#define RCLQ_cl_rbpdisp(disp) x86_encode_r64_rbpdisp64(0xD3,2,disp)
1.248 +#define RCLQ_cl_r64disp(rb,d) x86_encode_r64_r64disp32(0xD3,2,rb,d)
1.249 #define RCLQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,2,r1); } else { x86_encode_r64_rm64(0xC1,2,r1); OP(imm); }
1.250 -#define RCLQ_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r64_rbpdisp64(0xD1,2,disp); } else { x86_encode_r64_rbpdisp64(0xC1,2,disp); OP(imm); }
1.251 +#define RCLQ_imm_r64disp(imm,rb,d) if( imm == 1 ) { x86_encode_r64_r64disp32(0xD1,2,rb,d); } else { x86_encode_r64_r64disp32(0xC1,2,rb,d); OP(imm); }
1.252
1.253 #define RCRL_cl_r32(r1) x86_encode_r32_rm32(0xD3,3,r1)
1.254 -#define RCRL_cl_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xD3,3,disp)
1.255 +#define RCRL_cl_r32disp(rb,d) x86_encode_r32_r32disp32(0xD3,3,rb,d)
1.256 #define RCRL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,3,r1); } else { x86_encode_r32_rm32(0xC1,3,r1); OP(imm); }
1.257 -#define RCRL_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r32_rbpdisp32(0xD1,3,disp); } else { x86_encode_r32_rbpdisp32(0xC1,3,disp); OP(imm); }
1.258 +#define RCRL_imm_r32disp(imm,rb,d) if( imm == 1 ) { x86_encode_r32_r32disp32(0xD1,3,rb,d); } else { x86_encode_r32_r32disp32(0xC1,3,rb,d); OP(imm); }
1.259 #define RCRQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,3,r1)
1.260 -#define RCRQ_cl_rbpdisp(disp) x86_encode_r64_rbpdisp64(0xD3,3,disp)
1.261 +#define RCRQ_cl_r64disp(rb,d) x86_encode_r64_r64disp32(0xD3,3,rb,d)
1.262 #define RCRQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,3,r1); } else { x86_encode_r64_rm64(0xC1,3,r1); OP(imm); }
1.263 -#define RCRQ_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r64_rbpdisp64(0xD1,3,disp); } else { x86_encode_r64_rbpdisp64(0xC1,3,disp); OP(imm); }
1.264 +#define RCRQ_imm_r64disp(imm,rb,d) if( imm == 1 ) { x86_encode_r64_r64disp32(0xD1,3,rb,d); } else { x86_encode_r64_r64disp32(0xC1,3,rb,d); OP(imm); }
1.265
1.266 #define ROLL_cl_r32(r1) x86_encode_r32_rm32(0xD3,0,r1)
1.267 -#define ROLL_cl_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xD3,0,disp)
1.268 +#define ROLL_cl_r32disp(rb,d) x86_encode_r32_r32disp32(0xD3,0,rb,d)
1.269 #define ROLL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,0,r1); } else { x86_encode_r32_rm32(0xC1,0,r1); OP(imm); }
1.270 -#define ROLL_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r32_rbpdisp32(0xD1,0,disp); } else { x86_encode_r32_rbpdisp32(0xC1,0,disp); OP(imm); }
1.271 +#define ROLL_imm_r32disp(imm,rb,d) if( imm == 1 ) { x86_encode_r32_r32disp32(0xD1,0,rb,d); } else { x86_encode_r32_r32disp32(0xC1,0,rb,d); OP(imm); }
1.272 #define ROLQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,0,r1)
1.273 -#define ROLQ_cl_rbpdisp(disp) x86_encode_r64_rbpdisp64(0xD3,0,disp)
1.274 +#define ROLQ_cl_r64disp(rb,d) x86_encode_r64_r64disp32(0xD3,0,rb,d)
1.275 #define ROLQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,0,r1); } else { x86_encode_r64_rm64(0xC1,0,r1); OP(imm); }
1.276 -#define ROLQ_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r64_rbpdisp64(0xD1,0,disp); } else { x86_encode_r64_rbpdisp64(0xC1,0,disp); OP(imm); }
1.277 +#define ROLQ_imm_r64disp(imm,rb,d) if( imm == 1 ) { x86_encode_r64_r64disp32(0xD1,0,rb,d); } else { x86_encode_r64_r64disp32(0xC1,0,rb,d); OP(imm); }
1.278
1.279 #define RORL_cl_r32(r1) x86_encode_r32_rm32(0xD3,1,r1)
1.280 -#define RORL_cl_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xD3,1,disp)
1.281 +#define RORL_cl_r32disp(rb,d) x86_encode_r32_r32disp32(0xD3,1,rb,d)
1.282 #define RORL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,1,r1); } else { x86_encode_r32_rm32(0xC1,1,r1); OP(imm); }
1.283 -#define RORL_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r32_rbpdisp32(0xD1,1,disp); } else { x86_encode_r32_rbpdisp32(0xC1,1,disp); OP(imm); }
1.284 +#define RORL_imm_r32disp(imm,rb,d) if( imm == 1 ) { x86_encode_r32_r32disp32(0xD1,1,rb,d); } else { x86_encode_r32_r32disp32(0xC1,1,rb,d); OP(imm); }
1.285 #define RORQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,1,r1)
1.286 -#define RORQ_cl_rbpdisp(disp) x86_encode_r64_rbpdisp64(0xD3,1,disp)
1.287 +#define RORQ_cl_r64disp(rb,d) x86_encode_r64_r64disp32(0xD3,1,rb,d)
1.288 #define RORQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,1,r1); } else { x86_encode_r64_rm64(0xC1,1,r1); OP(imm); }
1.289 -#define RORQ_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r64_rbpdisp64(0xD1,1,disp); } else { x86_encode_r64_rbpdisp64(0xC1,1,disp); OP(imm); }
1.290 +#define RORQ_imm_r64disp(imm,rb,d) if( imm == 1 ) { x86_encode_r64_r64disp32(0xD1,1,rb,d); } else { x86_encode_r64_r64disp32(0xC1,1,rb,d); OP(imm); }
1.291
1.292 #define SARL_cl_r32(r1) x86_encode_r32_rm32(0xD3,7,r1)
1.293 -#define SARL_cl_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xD3,7,disp)
1.294 +#define SARL_cl_r32disp(rb,d) x86_encode_r32_r32disp32(0xD3,7,rb,d)
1.295 #define SARL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,7,r1); } else { x86_encode_r32_rm32(0xC1,7,r1); OP(imm); }
1.296 -#define SARL_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r32_rbpdisp32(0xD1,7,disp); } else { x86_encode_r32_rbpdisp32(0xC1,7,disp); OP(imm); }
1.297 +#define SARL_imm_r32disp(imm,rb,d) if( imm == 1 ) { x86_encode_r32_r32disp32(0xD1,7,rb,d); } else { x86_encode_r32_r32disp32(0xC1,7,rb,d); OP(imm); }
1.298 #define SARQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,7,r1)
1.299 -#define SARQ_cl_rbpdisp(disp) x86_encode_r64_rbpdisp64(0xD3,7,disp)
1.300 +#define SARQ_cl_r64disp(rb,d) x86_encode_r64_r64disp32(0xD3,7,rb,d)
1.301 #define SARQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,7,r1); } else { x86_encode_r64_rm64(0xC1,7,r1); OP(imm); }
1.302 -#define SARQ_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r64_rbpdisp64(0xD1,7,disp); } else { x86_encode_r64_rbpdisp64(0xC1,7,disp); OP(imm); }
1.303 +#define SARQ_imm_r64disp(imm,rb,d) if( imm == 1 ) { x86_encode_r64_r64disp32(0xD1,7,rb,d); } else { x86_encode_r64_r64disp32(0xC1,7,rb,d); OP(imm); }
1.304
1.305 #define SHLL_cl_r32(r1) x86_encode_r32_rm32(0xD3,4,r1)
1.306 -#define SHLL_cl_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xD3,4,disp)
1.307 +#define SHLL_cl_r32disp(rb,d) x86_encode_r32_r32disp32(0xD3,4,rb,d)
1.308 #define SHLL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,4,r1); } else { x86_encode_r32_rm32(0xC1,4,r1); OP(imm); }
1.309 -#define SHLL_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r32_rbpdisp32(0xD1,4,disp); } else { x86_encode_r32_rbpdisp32(0xC1,4,disp); OP(imm); }
1.310 +#define SHLL_imm_r32disp(imm,rb,d) if( imm == 1 ) { x86_encode_r32_r32disp32(0xD1,4,rb,d); } else { x86_encode_r32_r32disp32(0xC1,4,rb,d); OP(imm); }
1.311 #define SHLQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,4,r1)
1.312 -#define SHLQ_cl_rbpdisp(disp) x86_encode_r64_rbpdisp64(0xD3,4,disp)
1.313 +#define SHLQ_cl_r64disp(rb,d) x86_encode_r64_r64disp32(0xD3,4,rb,d)
1.314 #define SHLQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,4,r1); } else { x86_encode_r64_rm64(0xC1,4,r1); OP(imm); }
1.315 -#define SHLQ_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r64_rbpdisp64(0xD1,4,disp); } else { x86_encode_r64_rbpdisp64(0xC1,4,disp); OP(imm); }
1.316 +#define SHLQ_imm_r64disp(imm,rb,d) if( imm == 1 ) { x86_encode_r64_r64disp32(0xD1,4,rb,d); } else { x86_encode_r64_r64disp32(0xC1,4,rb,d); OP(imm); }
1.317
1.318 #define SHLDL_cl_r32_r32(r1,r2) x86_encode_r32_rm32(0x0FA5,r1,r2)
1.319 -#define SHLDL_cl_r32_rbpdisp(r1,d) x86_encode_r32_rbpdisp32(0x0FA5,r1,d)
1.320 +#define SHLDL_cl_r32_r32disp(r1,d) x86_encode_r32_r32disp32(0x0FA5,r1,d)
1.321 #define SHLDL_imm_r32_r32(imm,r1,r2) x86_encode_r32_rm32(0x0FA4,r1,r2); OP(imm)
1.322 -#define SHLDL_imm_r32_rbpdisp(i,r,d) x86_encode_r32_rbpdisp32(0x0FA4,r,d); OP(imm)
1.323 +#define SHLDL_imm_r32_r32disp(i,r,d) x86_encode_r32_r32disp32(0x0FA4,r,d); OP(imm)
1.324 #define SHLDQ_cl_r64_r64(r1,r2) x86_encode_r64_rm64(0x0FA5,r1,r2)
1.325 -#define SHLDQ_cl_r64_rbpdisp(r1,d) x86_encode_r64_rbpdisp64(0x0FA5,r1,d)
1.326 +#define SHLDQ_cl_r64_r64disp(r1,d) x86_encode_r64_r64disp32(0x0FA5,r1,d)
1.327 #define SHLDQ_imm_r64_r64(imm,r1,r2) x86_encode_r64_rm64(0x0FA4,r1,r2); OP(imm)
1.328 -#define SHLDQ_imm_r64_rbpdisp(i,r,d) x86_encode_r64_rbpdisp64(0x0FA4,r,d); OP(imm)
1.329 +#define SHLDQ_imm_r64_r64disp(i,r,d) x86_encode_r64_r64disp32(0x0FA4,r,d); OP(imm)
1.330
1.331 #define SHRL_cl_r32(r1) x86_encode_r32_rm32(0xD3,5,r1)
1.332 -#define SHRL_cl_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xD3,5,disp)
1.333 +#define SHRL_cl_r32disp(rb,d) x86_encode_r32_r32disp32(0xD3,5,rb,d)
1.334 #define SHRL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,5,r1); } else { x86_encode_r32_rm32(0xC1,5,r1); OP(imm); }
1.335 -#define SHRL_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r32_rbpdisp32(0xD1,5,disp); } else { x86_encode_r32_rbpdisp32(0xC1,5,disp); OP(imm); }
1.336 +#define SHRL_imm_r32disp(imm,rb,d) if( imm == 1 ) { x86_encode_r32_r32disp32(0xD1,5,rb,d); } else { x86_encode_r32_r32disp32(0xC1,5,rb,d); OP(imm); }
1.337 #define SHRQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,5,r1)
1.338 -#define SHRQ_cl_rbpdisp(disp) x86_encode_r64_rbpdisp64(0xD3,5,disp)
1.339 +#define SHRQ_cl_r64disp(rb,d) x86_encode_r64_r64disp32(0xD3,5,rb,d)
1.340 #define SHRQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,5,r1); } else { x86_encode_r64_rm64(0xC1,5,r1); OP(imm); }
1.341 -#define SHRQ_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r64_rbpdisp64(0xD1,5,disp); } else { x86_encode_r64_rbpdisp64(0xC1,5,disp); OP(imm); }
1.342 +#define SHRQ_imm_r64disp(imm,rb,d) if( imm == 1 ) { x86_encode_r64_r64disp32(0xD1,5,rb,d); } else { x86_encode_r64_r64disp32(0xC1,5,rb,d); OP(imm); }
1.343
1.344 -#define SHRDL_cl_r32_r32(r1,r2) x86_encode_r32_rm32(0x0FAD,r1,r2)
1.345 -#define SHRDL_cl_r32_rbpdisp(r1,d) x86_encode_r32_rbpdisp32(0x0FAD,r1,d)
1.346 -#define SHRDL_imm_r32_r32(imm,r1,r2) x86_encode_r32_rm32(0x0FAC,r1,r2); OP(imm)
1.347 -#define SHRDL_imm_r32_rbpdisp(i,r,d) x86_encode_r32_rbpdisp32(0x0FAC,r,d); OP(imm)
1.348 -#define SHRDQ_cl_r64_r64(r1,r2) x86_encode_r64_rm64(0x0FAD,r1,r2)
1.349 -#define SHRDQ_cl_r64_rbpdisp(r1,d) x86_encode_r64_rbpdisp64(0x0FAD,r1,d)
1.350 -#define SHRDQ_imm_r64_r64(imm,r1,r2) x86_encode_r64_rm64(0x0FAC,r1,r2); OP(imm)
1.351 -#define SHRDQ_imm_r64_rbpdisp(i,r,d) x86_encode_r64_rbpdisp64(0x0FAC,r,d); OP(imm)
1.352 +#define SHRDL_cl_r32_r32(r1,r2) x86_encode_r32_rm32(0x0FAD,r1,r2)
1.353 +#define SHRDL_cl_r32_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x0FAD,r1,rb,d)
1.354 +#define SHRDL_imm_r32_r32(imm,r1,r2) x86_encode_r32_rm32(0x0FAC,r1,r2); OP(imm)
1.355 +#define SHRDL_imm_r32_r32disp(i,r,rb,d) x86_encode_r32_r32disp32(0x0FAC,r,rb,d); OP(imm)
1.356 +#define SHRDQ_cl_r64_r64(r1,r2) x86_encode_r64_rm64(0x0FAD,r1,r2)
1.357 +#define SHRDQ_cl_r64_r64disp(r1,rb,d) x86_encode_r64_r64disp32(0x0FAD,r1,rb,d)
1.358 +#define SHRDQ_imm_r64_r64(imm,r1,r2) x86_encode_r64_rm64(0x0FAC,r1,r2); OP(imm)
1.359 +#define SHRDQ_imm_r64_r64disp(i,r,rb,d) x86_encode_r64_r64disp32(0x0FAC,r,rb,d); OP(imm)
1.360
1.361 #define SBBB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 3, r1); OP(imm)
1.362 #define SBBB_r8_r8(r1,r2) x86_encode_r32_rm32(0x18, r1, r2)
1.363 #define SBBL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 3, imm, r1)
1.364 +#define SBBL_imms_r32disp(imm,rb,d) x86_encode_imms_r32disp32(0x83,0x81,3,imm,rb,d)
1.365 #define SBBL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83,0x81,3,imm,disp)
1.366 #define SBBL_r32_r32(r1,r2) x86_encode_r32_rm32(0x19, r1, r2)
1.367 +#define SBBL_r32_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x19, r1, rb,d)
1.368 #define SBBL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x19, r1, disp)
1.369 +#define SBBL_r32disp_r32(rb,d,r1) x86_encode_r32_r32disp32(0x1B, r1, rb,d)
1.370 #define SBBL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x1B, r1, disp)
1.371 #define SBBQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 3, imm, r1)
1.372 #define SBBQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x19, r1, r2)
1.373
1.374 #define SETCCB_cc_r8(cc,r1) x86_encode_r32_rm32(0x0F90+(cc), 0, r1)
1.375 +#define SETCCB_cc_r32disp(cc,rb,d) x86_encode_r32_r32disp32(0x0F90+(cc), 0, rb, d)
1.376 #define SETCCB_cc_rbpdisp(cc,disp) x86_encode_r32_rbpdisp32(0x0F90+(cc), 0, disp)
1.377
1.378 #define STC() OP(0xF9)
1.379 @@ -614,9 +652,12 @@
1.380 #define SUBB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 5, r1); OP(imm)
1.381 #define SUBB_r8_r8(r1,r2) x86_encode_r32_rm32(0x28, r1, r2)
1.382 #define SUBL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 5, imm, r1)
1.383 +#define SUBL_imms_r32disp(imm,rb,d) x86_encode_imms_r32disp32(0x83,0x81,5,imm,rb,d)
1.384 #define SUBL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83,0x81,5,imm,disp)
1.385 #define SUBL_r32_r32(r1,r2) x86_encode_r32_rm32(0x29, r1, r2)
1.386 +#define SUBL_r32_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x29, r1, rb, d)
1.387 #define SUBL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x29, r1, disp)
1.388 +#define SUBL_r32disp_r32(rb,d,r1) x86_encode_r32_r32disp32(0x2B, r1, rb, d)
1.389 #define SUBL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x2B, r1, disp)
1.390 #define SUBQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 5, imm, r1)
1.391 #define SUBQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x29, r1, r2)
1.392 @@ -624,9 +665,12 @@
1.393 #define TESTB_imms_r8(imm,r1) x86_encode_r32_rm32(0xF6, 0, r1); OP(imm)
1.394 #define TESTB_r8_r8(r1,r2) x86_encode_r32_rm32(0x84, r1, r2)
1.395 #define TESTL_imms_r32(imm,r1) x86_encode_r32_rm32(0xF7, 0, r1); OP32(imm)
1.396 +#define TESTL_imms_r32disp(imm,r,d) x86_encode_r32_r32disp32(0xF7, 0, r, d); OP32(imm)
1.397 #define TESTL_imms_rbpdisp(imm,dsp) x86_encode_r32_rbpdisp32(0xF7, 0, dsp); OP32(imm)
1.398 #define TESTL_r32_r32(r1,r2) x86_encode_r32_rm32(0x85, r1, r2)
1.399 +#define TESTL_r32_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x85, r1, rb, d)
1.400 #define TESTL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x85, r1, disp)
1.401 +#define TESTL_r32disp_r32(rb,d,r1) x86_encode_r32_r32disp32(0x85, r1, rb, d) /* Same OP */
1.402 #define TESTL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x85, r1, disp) /* Same OP */
1.403 #define TESTQ_imms_r64(imm,r1) x86_encode_r64_rm64(0xF7, 0, r1); OP32(imm)
1.404 #define TESTQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x85, r1, r2)
1.405 @@ -638,18 +682,21 @@
1.406 #define XORB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 6, r1); OP(imm)
1.407 #define XORB_r8_r8(r1,r2) x86_encode_r32_rm32(0x30, r1, r2)
1.408 #define XORL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 6, imm, r1)
1.409 +#define XORL_imms_r32disp(imm,rb,d) x86_encode_imms_r32disp32(0x83,0x81,6,imm,rb,d)
1.410 #define XORL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83,0x81,6,imm,disp)
1.411 #define XORL_r32_r32(r1,r2) x86_encode_r32_rm32(0x31, r1, r2)
1.412 +#define XORL_r32_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x31, r1, rb, d)
1.413 #define XORL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x31, r1, disp)
1.414 +#define XORL_r32disp_r32(rb,d,r1) x86_encode_r32_r32disp32(0x33, r1, rb, d)
1.415 #define XORL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x33, r1, disp)
1.416 #define XORQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 6, imm, r1)
1.417 #define XORQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x31, r1, r2)
1.418
1.419 /* Control flow */
1.420 #define CALL_rel(rel) OP(0xE8); OP32(rel)
1.421 -#define CALL_imm32(ptr) x86_encode_r32_mem32disp32(0xFF, 2, -1, ptr)
1.422 +#define CALL_imm32(ptr) x86_encode_r32_r32disp32(0xFF, 2, -1, ptr)
1.423 #define CALL_r32(r1) x86_encode_r32_rm32(0xFF, 2, r1)
1.424 -#define CALL_r32disp(r1,disp) x86_encode_r32_mem32disp32(0xFF, 2, r1, disp)
1.425 +#define CALL_r32disp(r1,disp) x86_encode_r32_r32disp32(0xFF, 2, r1, disp)
1.426 #define CALL_sib(ss,ii,bb,disp) x86_encode_r32_mem32(0xFF, 2, bb, ii, ss, disp)
1.427
1.428 #define JCC_cc_rel8(cc,rel) OP(0x70+(cc)); OP(rel)
1.429 @@ -661,7 +708,7 @@
1.430 #define JMP_rel(rel) if( IS_INT8(rel) ) { JMP_rel8((int8_t)rel); } else { JMP_rel32(rel); }
1.431 #define JMP_prerel(rel) if( IS_INT8(((int32_t)rel)-2) ) { JMP_rel8(((int8_t)rel)-2); } else { JMP_rel32(((int32_t)rel)-5); }
1.432 #define JMP_r32(r1,disp) x86_encode_r32_rm32(0xFF, 4, r1)
1.433 -#define JMP_r32disp(r1,disp) x86_encode_r32_mem32disp32(0xFF, 4, r1, disp)
1.434 +#define JMP_r32disp(r1,disp) x86_encode_r32_r32disp32(0xFF, 4, r1, disp)
1.435 #define RET() OP(0xC3)
1.436 #define RET_imm(imm) OP(0xC2); OP16(imm)
1.437
1.438 @@ -686,12 +733,12 @@
1.439 #define FCHS_st0() OP(0xD9); OP(0xE0)
1.440 #define FCOMIP_st(st) OP(0xDF); OP(0xF0+(st))
1.441 #define FDIVP_st(st) OP(0xDE); OP(0xF8+(st))
1.442 -#define FILD_r32disp(r32, disp) x86_encode_r32_mem32disp32(0xDB, 0, r32, disp)
1.443 +#define FILD_r32disp(r32, disp) x86_encode_r32_r32disp32(0xDB, 0, r32, disp)
1.444 #define FLD0_st0() OP(0xD9); OP(0xEE);
1.445 #define FLD1_st0() OP(0xD9); OP(0xE8);
1.446 -#define FLDCW_r32disp(r32, disp) x86_encode_r32_mem32disp32(0xD9, 5, r32, disp)
1.447 +#define FLDCW_r32disp(r32, disp) x86_encode_r32_r32disp32(0xD9, 5, r32, disp)
1.448 #define FMULP_st(st) OP(0xDE); OP(0xC8+(st))
1.449 -#define FNSTCW_r32disp(r32, disp) x86_encode_r32_mem32disp32(0xD9, 7, r32, disp)
1.450 +#define FNSTCW_r32disp(r32, disp) x86_encode_r32_r32disp32(0xD9, 7, r32, disp)
1.451 #define FPOP_st() OP(0xDD); OP(0xC0); OP(0xD9); OP(0xF7)
1.452 #define FSUBP_st(st) OP(0xDE); OP(0xE8+(st))
1.453 #define FSQRT_st0() OP(0xD9); OP(0xFA)
1.454 @@ -711,190 +758,190 @@
1.455 #define MOVQ_xmm_r64(r1,r2) OP(0x66); x86_encode_r64_rm64(0x0F7E, r1, r2)
1.456
1.457 /* SSE Packed floating point instructions */
1.458 -#define ADDPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F58, r1, disp)
1.459 +#define ADDPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F58, r1, rb,d)
1.460 #define ADDPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F58, r2, r1)
1.461 -#define ANDPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F54, r1, disp)
1.462 +#define ANDPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F54, r1, rb,d)
1.463 #define ANDPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F54, r2, r1)
1.464 -#define ANDNPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F55, r1, disp)
1.465 +#define ANDNPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F55, r1, rb,d)
1.466 #define ANDNPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F55, r2, r1)
1.467 -#define CMPPS_cc_rbpdisp_xmm(cc,d,r) x86_encode_r32_rbpdisp32(0x0FC2, r, d); OP(cc)
1.468 +#define CMPPS_cc_r32disp_xmm(cc,rb,d,r) x86_encode_r32_r32disp32(0x0FC2, r, rb, d); OP(cc)
1.469 #define CMPPS_cc_xmm_xmm(cc,r1,r2) x86_encode_r32_rm32(0x0FC2, r2, r1); OP(cc)
1.470 -#define DIVPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F5E, r1, disp)
1.471 +#define DIVPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F5E, r1, rb,d)
1.472 #define DIVPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F5E, r2, r1)
1.473 -#define MAXPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F5F, r1, disp)
1.474 +#define MAXPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F5F, r1, rb,d)
1.475 #define MAXPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F5F, r2, r1)
1.476 -#define MINPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F5D, r1, disp)
1.477 +#define MINPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F5D, r1, rb,d)
1.478 #define MINPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F5D, r2, r1)
1.479 #define MOV_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F28, r2, r1)
1.480 -#define MOVAPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F28, r1, disp)
1.481 -#define MOVAPS_xmm_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x0F29, r1, disp)
1.482 +#define MOVAPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F28, r1, rb,d)
1.483 +#define MOVAPS_xmm_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x0F29, r1, rb,d)
1.484 #define MOVHLPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F12, r2, r1)
1.485 -#define MOVHPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F16, r1, disp)
1.486 -#define MOVHPS_xmm_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x0F17, r1, disp)
1.487 +#define MOVHPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F16, r1, rb,d)
1.488 +#define MOVHPS_xmm_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x0F17, r1, rb,d)
1.489 #define MOVLHPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F16, r2, r1)
1.490 -#define MOVLPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F12, r1, disp)
1.491 -#define MOVLPS_xmm_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x0F13, r1, disp)
1.492 -#define MOVUPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F10, r1, disp)
1.493 -#define MOVUPS_xmm_rbpdisp(disp,r1) x86_encode_r32_rbpdisp32(0x0F11, r1, disp)
1.494 +#define MOVLPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F12, r1, rb,d)
1.495 +#define MOVLPS_xmm_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x0F13, r1, rb,d)
1.496 +#define MOVUPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F10, r1, rb,d)
1.497 +#define MOVUPS_xmm_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x0F11, r1, rb,d)
1.498 #define MULPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F59, r2, r1)
1.499 -#define MULPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0xF59, r1, disp)
1.500 -#define ORPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F56, r1, disp)
1.501 +#define MULPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0xF59, r1, rb,d)
1.502 +#define ORPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F56, r1, rb,d)
1.503 #define ORPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F56, r2, r1)
1.504 -#define RCPPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0xF53, r1, disp)
1.505 +#define RCPPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0xF53, r1, rb,d)
1.506 #define RCPPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F53, r2, r1)
1.507 -#define RSQRTPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F52, r1, disp)
1.508 +#define RSQRTPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F52, r1, rb,d)
1.509 #define RSQRTPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F52, r2, r1)
1.510 -#define SHUFPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0FC6, r1, disp)
1.511 +#define SHUFPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0FC6, r1, rb,d)
1.512 #define SHUFPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0FC6, r2, r1)
1.513 -#define SQRTPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F51, r1, disp)
1.514 +#define SQRTPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F51, r1, rb,d)
1.515 #define SQRTPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F51, r2, r1)
1.516 -#define SUBPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F5C, r1, disp)
1.517 +#define SUBPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F5C, r1, rb,d)
1.518 #define SUBPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F5C, r2, r1)
1.519 -#define UNPCKHPS_rbpdisp_xmm(dsp,r1) x86_encode_r32_rbpdisp32(0x0F15, r1, disp)
1.520 +#define UNPCKHPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F15, r1, rb,d)
1.521 #define UNPCKHPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F15, r2, r1)
1.522 -#define UNPCKLPS_rbpdisp_xmm(dsp,r1) x86_encode_r32_rbpdisp32(0x0F14, r1, disp)
1.523 +#define UNPCKLPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F14, r1, rb,d)
1.524 #define UNPCKLPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F14, r2, r1)
1.525 -#define XORPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F57, r1, disp)
1.526 +#define XORPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F57, r1, rb,d)
1.527 #define XORPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F57, r2, r1)
1.528
1.529 /* SSE Scalar floating point instructions */
1.530 -#define ADDSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F58, r1, disp)
1.531 +#define ADDSS_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F58, r1, rb,d)
1.532 #define ADDSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F58, r2, r1)
1.533 -#define CMPSS_cc_rbpdisp_xmm(cc,d,r) OP(0xF3); x86_encode_r32_rbpdisp32(0x0FC2, r, d); OP(cc)
1.534 +#define CMPSS_cc_r32disp_xmm(cc,rb,d,r) OP(0xF3); x86_encode_r32_r32disp32(0x0FC2, r, rb, d); OP(cc)
1.535 #define CMPSS_cc_xmm_xmm(cc,r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0FC2, r2, r1); OP(cc)
1.536 -#define COMISS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F2F, r1, disp)
1.537 +#define COMISS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F2F, r1, rb,d)
1.538 #define COMISS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F2F, r2, r1)
1.539 #define CVTSI2SSL_r32_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F2A, r2, r1)
1.540 -#define CVTSI2SSL_rbpdisp_xmm(d,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F2A, r1, d)
1.541 +#define CVTSI2SSL_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F2A, r1, rb,d)
1.542 #define CVTSI2SSQ_r64_xmm(r1,r2) OP(0xF3); x86_encode_r64_rm64(0x0F2A, r2, r1)
1.543 -#define CVTSI2SSQ_rbpdisp_xmm(d,r1) OP(0xF3); x86_encode_r64_rbpdisp64(0x0F2A, r1, d)
1.544 +#define CVTSI2SSQ_r64disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r64_r64disp32(0x0F2A, r1, rb,d)
1.545 #define CVTSS2SIL_xmm_r32(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F2D, r2, r1)
1.546 -#define CVTSS2SIL_rbpdisp_r32(d,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F2D, r1, d)
1.547 +#define CVTSS2SIL_r32disp_r32(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F2D, r1, rb, d)
1.548 #define CVTSS2SIQ_xmm_r64(r1,r2) OP(0xF3); x86_encode_r64_rm64(0x0F2D, r2, r1)
1.549 -#define CVTSS2SIQ_rbpdisp_r64(d,r1) OP(0xF3); x86_encode_r64_rbpdisp64(0x0F2D, r1, d)
1.550 +#define CVTSS2SIQ_r64disp_r64(rb,d,r1) OP(0xF3); x86_encode_r64_r64disp32(0x0F2D, r1, rb, d)
1.551 #define CVTTSS2SIL_xmm_r32(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F2C, r2, r1)
1.552 -#define CVTTSS2SIL_rbpdisp_r32(d,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F2C, r1, d)
1.553 +#define CVTTSS2SIL_r32disp_r32(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F2C, r1, rb, d)
1.554 #define CVTTSS2SIQ_xmm_r64(r1,r2) OP(0xF3); x86_encode_r64_rm64(0x0F2C, r2, r1)
1.555 -#define CVTTSS2SIQ_rbpdisp_r64(d,r1) OP(0xF3); x86_encode_r64_rbpdisp64(0x0F2C, r1, d)
1.556 -#define DIVSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F5E, r1, disp)
1.557 +#define CVTTSS2SIQ_r64disp_r64(rb,d,r1) OP(0xF3); x86_encode_r64_r64disp32(0x0F2C, r1, rb, d)
1.558 +#define DIVSS_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F5E, r1, rb,d)
1.559 #define DIVSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F5E, r2, r1)
1.560 -#define MAXSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F5F, r1, disp)
1.561 +#define MAXSS_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F5F, r1, rb,d)
1.562 #define MAXSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F5F, r2, r1)
1.563 -#define MINSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F5D, r1, disp)
1.564 +#define MINSS_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F5D, r1, rb,d)
1.565 #define MINSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F5D, r2, r1)
1.566 -#define MOVSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F10, r1, disp)
1.567 -#define MOVSS_xmm_rbpdisp(r1,disp) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F11, r1, disp)
1.568 +#define MOVSS_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F10, r1, rb,d)
1.569 +#define MOVSS_xmm_r32disp(r1,rb,d) OP(0xF3); x86_encode_r32_r32disp32(0x0F11, r1, rb,d)
1.570 #define MOVSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F10, r2, r1)
1.571 -#define MULSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0xF59, r1, disp)
1.572 +#define MULSS_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0xF59, r1, rb,d)
1.573 #define MULSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F59, r2, r1)
1.574 -#define RCPSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0xF53, r1, disp)
1.575 +#define RCPSS_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0xF53, r1, rb,d)
1.576 #define RCPSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F53, r2, r1)
1.577 -#define RSQRTSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F52, r1, disp)
1.578 +#define RSQRTSS_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F52, r1, rb,d)
1.579 #define RSQRTSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F52, r2, r1)
1.580 -#define SQRTSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F51, r1, disp)
1.581 +#define SQRTSS_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F51, r1, rb,d)
1.582 #define SQRTSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F51, r2, r1)
1.583 -#define SUBSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F5C, r1, disp)
1.584 +#define SUBSS_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F5C, r1, rb,d)
1.585 #define SUBSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F5C, r2, r1)
1.586 -#define UCOMISS_rbpdisp_xmm(dsp,r1) x86_encode_r32_rbpdisp32(0x0F2E, r1, dsp)
1.587 +#define UCOMISS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F2E, r1, rb,d)
1.588 #define UCOMISS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F2E, r2, r1)
1.589
1.590 /* SSE2 Packed floating point instructions */
1.591 -#define ADDPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F58, r1, disp)
1.592 +#define ADDPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F58, r1, rb,d)
1.593 #define ADDPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F58, r2, r1)
1.594 -#define ANDPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F54, r1, disp)
1.595 +#define ANDPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F54, r1, rb,d)
1.596 #define ANDPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F54, r2, r1)
1.597 -#define ANDNPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F55, r1, disp)
1.598 +#define ANDNPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F55, r1, rb,d)
1.599 #define ANDNPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F55, r2, r1)
1.600 -#define CMPPD_cc_rbpdisp_xmm(cc,d,r) OP(0x66); x86_encode_r32_rbpdisp32(0x0FC2, r, d); OP(cc)
1.601 +#define CMPPD_cc_r32disp_xmm(cc,rb,d,r) OP(0x66); x86_encode_r32_r32disp32(0x0FC2, r, rb, d); OP(cc)
1.602 #define CMPPD_cc_xmm_xmm(cc,r1,r2) OP(0x66); x86_encode_r32_rm32(0x0FC2, r2, r1); OP(cc)
1.603 -#define CVTPD2PS_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F5A, r1, dsp)
1.604 +#define CVTPD2PS_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F5A, r1, rb,d)
1.605 #define CVTPD2PS_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F5A, r2, r1)
1.606 -#define CVTPS2PD_rbpdisp_xmm(dsp,r1) x86_encode_r32_rbpdisp32(0x0F5A, r1, dsp)
1.607 +#define CVTPS2PD_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F5A, r1, rb,d)
1.608 #define CVTPS2PD_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F5A, r2, r1)
1.609 -#define DIVPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F5E, r1, disp)
1.610 +#define DIVPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F5E, r1, rb,d)
1.611 #define DIVPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F5E, r2, r1)
1.612 -#define MAXPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F5F, r1, disp)
1.613 +#define MAXPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F5F, r1, rb,d)
1.614 #define MAXPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F5F, r2, r1)
1.615 -#define MINPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F5D, r1, disp)
1.616 +#define MINPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F5D, r1, rb,d)
1.617 #define MINPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F5D, r2, r1)
1.618 -#define MOVHPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F16, r1, disp)
1.619 -#define MOVHPD_xmm_rbpdisp(r1,disp) OP(0x66); x86_encode_r32_rbpdisp32(0x0F17, r1, disp)
1.620 -#define MOVLPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F12, r1, disp)
1.621 -#define MOVLPD_xmm_rbpdisp(r1,disp) OP(0x66); x86_encode_r32_rbpdisp32(0x0F13, r1, disp)
1.622 -#define MULPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0xF59, r1, disp)
1.623 +#define MOVHPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F16, r1, rb,d)
1.624 +#define MOVHPD_xmm_r32disp(r1,rb,d) OP(0x66); x86_encode_r32_r32disp32(0x0F17, r1, rb,d)
1.625 +#define MOVLPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F12, r1, rb,d)
1.626 +#define MOVLPD_xmm_r32disp(r1,rb,d) OP(0x66); x86_encode_r32_r32disp32(0x0F13, r1, rb,d)
1.627 +#define MULPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0xF59, r1, rb,d)
1.628 #define MULPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F59, r2, r1)
1.629 -#define ORPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F56, r1, disp)
1.630 +#define ORPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F56, r1, rb,d)
1.631 #define ORPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F56, r2, r1)
1.632 -#define SHUFPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0FC6, r1, disp)
1.633 +#define SHUFPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0FC6, r1, rb,d)
1.634 #define SHUFPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0FC6, r2, r1)
1.635 -#define SUBPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F5C, r1, disp)
1.636 +#define SUBPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F5C, r1, rb,d)
1.637 #define SUBPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F5C, r2, r1)
1.638 -#define UNPCKHPD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F15, r1, disp)
1.639 +#define UNPCKHPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F15, r1, disp)
1.640 #define UNPCKHPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F15, r2, r1)
1.641 -#define UNPCKLPD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F14, r1, disp)
1.642 +#define UNPCKLPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F14, r1, disp)
1.643 #define UNPCKLPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F14, r2, r1)
1.644 -#define XORPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F57, r1, disp)
1.645 +#define XORPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F57, r1, rb,d)
1.646 #define XORPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F57, r2, r1)
1.647
1.648
1.649 /* SSE2 Scalar floating point instructions */
1.650 -#define ADDSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F58, r1, disp)
1.651 +#define ADDSD_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F58, r1, rb,d)
1.652 #define ADDSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F58, r2, r1)
1.653 -#define CMPSD_cc_rbpdisp_xmm(cc,d,r) OP(0xF2); x86_encode_r32_rbpdisp32(0x0FC2, r, d); OP(cc)
1.654 +#define CMPSD_cc_r32disp_xmm(cc,rb,d,r) OP(0xF2); x86_encode_r32_r32disp32(0x0FC2, r, rb, d); OP(cc)
1.655 #define CMPSD_cc_xmm_xmm(cc,r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0FC2, r2, r1); OP(cc)
1.656 #define CVTSI2SDL_r32_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F2A, r2, r1)
1.657 -#define CVTSI2SDL_rbpdisp_xmm(d,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F2A, r1, d)
1.658 +#define CVTSI2SDL_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F2A, r1, rb,d)
1.659 #define CVTSI2SDQ_r64_xmm(r1,r2) OP(0xF2); x86_encode_r64_rm64(0x0F2A, r2, r1)
1.660 -#define CVTSI2SDQ_rbpdisp_xmm(d,r1) OP(0xF2); x86_encode_r64_rbpdisp64(0x0F2A, r1, d)
1.661 +#define CVTSI2SDQ_r64disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r64_r64disp32(0x0F2A, r1, rb,d)
1.662 #define CVTSD2SIL_xmm_r32(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F2D, r2, r1)
1.663 -#define CVTSD2SIL_rbpdisp_r32(d,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F2D, r1, d)
1.664 +#define CVTSD2SIL_r32disp_r32(rb, d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F2D, r1, rb, d)
1.665 #define CVTSD2SIQ_xmm_r64(r1,r2) OP(0xF2); x86_encode_r64_rm64(0x0F2D, r2, r1)
1.666 -#define CVTSD2SIQ_rbpdisp_r64(d,r1) OP(0xF2); x86_encode_r64_rbpdisp64(0x0F2D, r1, d)
1.667 -#define CVTSD2SS_rbpdisp_xmm(dsp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F5A, r1, dsp)
1.668 +#define CVTSD2SIQ_r64disp_r64(rb,d,r1) OP(0xF2); x86_encode_r64_r64disp32(0x0F2D, r1, rb, d)
1.669 +#define CVTSD2SS_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F5A, r1, rb,d)
1.670 #define CVTSD2SS_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F5A, r2, r1)
1.671 -#define CVTSS2SD_rbpdisp_xmm(dsp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F5A, r1, dsp)
1.672 +#define CVTSS2SD_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F5A, r1, rb,d)
1.673 #define CVTSS2SD_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F5A, r2, r1)
1.674 #define CVTTSD2SIL_xmm_r32(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F2C, r2, r1)
1.675 -#define CVTTSD2SIL_rbpdisp_r32(d,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F2C, r1, d)
1.676 +#define CVTTSD2SIL_r32disp_r32(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F2C, r1, rb, d)
1.677 #define CVTTSD2SIQ_xmm_r64(r1,r2) OP(0xF2); x86_encode_r64_rm64(0x0F2C, r2, r1)
1.678 -#define CVTTSD2SIQ_rbpdisp_r64(d,r1) OP(0xF2); x86_encode_r64_rbpdisp64(0x0F2C, r1, d)
1.679 +#define CVTTSD2SIQ_r64disp_r64(rb,d,r1) OP(0xF2); x86_encode_r64_r64disp32(0x0F2C, r1, rb, d)
1.680
1.681 -#define COMISD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F2F, r1, disp)
1.682 +#define COMISD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F2F, r1, rb,d)
1.683 #define COMISD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F2F, r2, r1)
1.684 -#define DIVSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F5E, r1, disp)
1.685 +#define DIVSD_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F5E, r1, rb,d)
1.686 #define DIVSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F5E, r2, r1)
1.687 -#define MAXSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F5F, r1, disp)
1.688 +#define MAXSD_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F5F, r1, rb,d)
1.689 #define MAXSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F5F, r2, r1)
1.690 -#define MINSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F5D, r1, disp)
1.691 +#define MINSD_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F5D, r1, rb,d)
1.692 #define MINSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F5D, r2, r1)
1.693 -#define MOVSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F10, r1, disp)
1.694 -#define MOVSD_xmm_rbpdisp(r1,disp) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F11, r1, disp)
1.695 +#define MOVSD_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F10, r1, rb,d)
1.696 +#define MOVSD_xmm_r32disp(r1,rb,d) OP(0xF2); x86_encode_r32_r32disp32(0x0F11, r1, rb,d)
1.697 #define MOVSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F10, r2, r1)
1.698 -#define MULSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0xF59, r1, disp)
1.699 +#define MULSD_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0xF59, r1, rb,d)
1.700 #define MULSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F59, r2, r1)
1.701 -#define SQRTSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F51, r1, disp)
1.702 +#define SQRTSD_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F51, r1, rb,d)
1.703 #define SQRTSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F51, r2, r1)
1.704 -#define SUBSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F5C, r1, disp)
1.705 +#define SUBSD_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F5C, r1, rb,d)
1.706 #define SUBSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F5C, r2, r1)
1.707 -#define UCOMISD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F2E, r1, dsp)
1.708 +#define UCOMISD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F2E, r1, rb,d)
1.709 #define UCOMISD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F2E, r2, r1)
1.710
1.711 /* SSE3 floating point instructions */
1.712 -#define ADDSUBPD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0FD0, r1, dsp)
1.713 +#define ADDSUBPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0FD0, r1, rb,d)
1.714 #define ADDSUBPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0FD0, r2, r1)
1.715 -#define ADDSUBPS_rbpdisp_xmm(dsp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0FD0, r1, dsp)
1.716 +#define ADDSUBPS_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0FD0, r1, rb,d)
1.717 #define ADDSUBPS_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0FD0, r2, r1)
1.718 -#define HADDPD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F7C, r1, dsp)
1.719 +#define HADDPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F7C, r1, rb,d)
1.720 #define HADDPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F7C, r2, r1)
1.721 -#define HADDPS_rbpdisp_xmm(dsp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F7C, r1, dsp)
1.722 +#define HADDPS_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F7C, r1, rb,d)
1.723 #define HADDPS_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F7C, r2, r1)
1.724 -#define HSUBPD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F7D, r1, dsp)
1.725 +#define HSUBPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F7D, r1, rb,d)
1.726 #define HSUBPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F7D, r2, r1)
1.727 -#define HSUBPS_rbpdisp_xmm(dsp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F7D, r1, dsp)
1.728 +#define HSUBPS_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F7D, r1, rb,d)
1.729 #define HSUBPS_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F7D, r2, r1)
1.730 -#define MOVSHDUP_rbpdisp_xmm(dsp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F16, r1, dsp)
1.731 +#define MOVSHDUP_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F16, r1, rb,d)
1.732 #define MOVSHDUP_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F16, r2, r1)
1.733 -#define MOVSLDUP_rbpdisp_xmm(dsp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F12, r1, dsp)
1.734 +#define MOVSLDUP_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F12, r1, rb,d)
1.735 #define MOVSLDUP_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F12, r2, r1)
1.736
1.737 /************************ Import calling conventions *************************/
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