4 * SH4 MMU implementation based on address space page maps. This module
5 * is responsible for all address decoding functions.
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 #define MODULE sh4_module
23 #include "sh4/sh4mmio.h"
24 #include "sh4/sh4core.h"
25 #include "sh4/sh4trans.h"
26 #include "dreamcast.h"
30 #define RAISE_TLB_ERROR(code, vpn) sh4_raise_tlb_exception(code, vpn)
31 #define RAISE_MEM_ERROR(code, vpn) \
32 MMIO_WRITE(MMU, TEA, vpn); \
33 MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
34 sh4_raise_exception(code);
35 #define RAISE_TLB_MULTIHIT_ERROR(vpn) sh4_raise_tlb_multihit(vpn)
37 /* An entry is a 1K entry if it's one of the mmu_utlb_1k_pages entries */
38 #define IS_1K_PAGE_ENTRY(ent) ( ((uintptr_t)(((struct utlb_1k_entry *)ent) - &mmu_utlb_1k_pages[0])) < UTLB_ENTRY_COUNT )
40 /* Primary address space (used directly by SH4 cores) */
41 mem_region_fn_t *sh4_address_space;
42 mem_region_fn_t *sh4_user_address_space;
44 /* Accessed from the UTLB accessor methods */
47 static gboolean mmu_urc_overflow; /* If true, urc was set >= urb */
50 static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT];
51 static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT];
52 static struct utlb_page_entry mmu_utlb_pages[UTLB_ENTRY_COUNT];
53 static uint32_t mmu_lrui;
54 static uint32_t mmu_asid; // current asid
55 static struct utlb_default_regions *mmu_user_storequeue_regions;
57 /* Structures for 1K page handling */
58 static struct utlb_1k_entry mmu_utlb_1k_pages[UTLB_ENTRY_COUNT];
59 static int mmu_utlb_1k_free_list[UTLB_ENTRY_COUNT];
60 static int mmu_utlb_1k_free_index;
63 /* Function prototypes */
64 static void mmu_invalidate_tlb();
65 static void mmu_utlb_register_all();
66 static void mmu_utlb_remove_entry(int);
67 static void mmu_utlb_insert_entry(int);
68 static void mmu_register_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn );
69 static void mmu_register_user_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn );
70 static void mmu_set_tlb_enabled( int tlb_on );
71 static void mmu_set_tlb_asid( uint32_t asid );
72 static void mmu_set_storequeue_protected( int protected, int tlb_on );
73 static gboolean mmu_utlb_map_pages( mem_region_fn_t priv_page, mem_region_fn_t user_page, sh4addr_t start_addr, int npages );
74 static void mmu_utlb_remap_pages( gboolean remap_priv, gboolean remap_user, int entryNo );
75 static gboolean mmu_utlb_unmap_pages( gboolean unmap_priv, gboolean unmap_user, sh4addr_t start_addr, int npages );
76 static gboolean mmu_ext_page_remapped( sh4addr_t page, mem_region_fn_t fn, void *user_data );
77 static void mmu_utlb_1k_init();
78 static struct utlb_1k_entry *mmu_utlb_1k_alloc();
79 static void mmu_utlb_1k_free( struct utlb_1k_entry *entry );
80 static int mmu_read_urc();
82 static void FASTCALL tlb_miss_read( sh4addr_t addr, void *exc );
83 static int32_t FASTCALL tlb_protected_read( sh4addr_t addr, void *exc );
84 static void FASTCALL tlb_protected_write( sh4addr_t addr, uint32_t val, void *exc );
85 static int32_t FASTCALL tlb_protected_read_for_write( sh4addr_t addr, void *exc );
86 static void FASTCALL tlb_initial_write( sh4addr_t addr, uint32_t val, void *exc );
87 static int32_t FASTCALL tlb_initial_read_for_write( sh4addr_t addr, void *exc );
88 static uint32_t get_tlb_size_mask( uint32_t flags );
89 static uint32_t get_tlb_size_pages( uint32_t flags );
91 #define DEFAULT_REGIONS 0
92 #define DEFAULT_STOREQUEUE_REGIONS 1
93 #define DEFAULT_STOREQUEUE_SQMD_REGIONS 2
95 static struct utlb_default_regions mmu_default_regions[3] = {
96 { &mem_region_tlb_miss, &mem_region_tlb_protected, &mem_region_tlb_multihit },
97 { &p4_region_storequeue_miss, &p4_region_storequeue_protected, &p4_region_storequeue_multihit },
98 { &p4_region_storequeue_sqmd_miss, &p4_region_storequeue_sqmd_protected, &p4_region_storequeue_sqmd_multihit } };
100 #define IS_STOREQUEUE_PROTECTED() (mmu_user_storequeue_regions == &mmu_default_regions[DEFAULT_STOREQUEUE_SQMD_REGIONS])
102 /*********************** Module public functions ****************************/
105 * Allocate memory for the address space maps, and initialize them according
106 * to the default (reset) values. (TLB is disabled by default)
111 sh4_address_space = mem_alloc_pages( sizeof(mem_region_fn_t) * 256 );
112 sh4_user_address_space = mem_alloc_pages( sizeof(mem_region_fn_t) * 256 );
113 mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
115 mmu_set_tlb_enabled(0);
116 mmu_register_user_mem_region( 0x80000000, 0x00000000, &mem_region_address_error );
117 mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
119 /* Setup P4 tlb/cache access regions */
120 mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
121 mmu_register_mem_region( 0xE4000000, 0xF0000000, &mem_region_unmapped );
122 mmu_register_mem_region( 0xF0000000, 0xF1000000, &p4_region_icache_addr );
123 mmu_register_mem_region( 0xF1000000, 0xF2000000, &p4_region_icache_data );
124 mmu_register_mem_region( 0xF2000000, 0xF3000000, &p4_region_itlb_addr );
125 mmu_register_mem_region( 0xF3000000, 0xF4000000, &p4_region_itlb_data );
126 mmu_register_mem_region( 0xF4000000, 0xF5000000, &p4_region_ocache_addr );
127 mmu_register_mem_region( 0xF5000000, 0xF6000000, &p4_region_ocache_data );
128 mmu_register_mem_region( 0xF6000000, 0xF7000000, &p4_region_utlb_addr );
129 mmu_register_mem_region( 0xF7000000, 0xF8000000, &p4_region_utlb_data );
130 mmu_register_mem_region( 0xF8000000, 0x00000000, &mem_region_unmapped );
132 /* Setup P4 control region */
133 mmu_register_mem_region( 0xFF000000, 0xFF001000, &mmio_region_MMU.fn );
134 mmu_register_mem_region( 0xFF100000, 0xFF101000, &mmio_region_PMM.fn );
135 mmu_register_mem_region( 0xFF200000, 0xFF201000, &mmio_region_UBC.fn );
136 mmu_register_mem_region( 0xFF800000, 0xFF801000, &mmio_region_BSC.fn );
137 mmu_register_mem_region( 0xFF900000, 0xFFA00000, &mem_region_unmapped ); // SDMR2 + SDMR3
138 mmu_register_mem_region( 0xFFA00000, 0xFFA01000, &mmio_region_DMAC.fn );
139 mmu_register_mem_region( 0xFFC00000, 0xFFC01000, &mmio_region_CPG.fn );
140 mmu_register_mem_region( 0xFFC80000, 0xFFC81000, &mmio_region_RTC.fn );
141 mmu_register_mem_region( 0xFFD00000, 0xFFD01000, &mmio_region_INTC.fn );
142 mmu_register_mem_region( 0xFFD80000, 0xFFD81000, &mmio_region_TMU.fn );
143 mmu_register_mem_region( 0xFFE00000, 0xFFE01000, &mmio_region_SCI.fn );
144 mmu_register_mem_region( 0xFFE80000, 0xFFE81000, &mmio_region_SCIF.fn );
145 mmu_register_mem_region( 0xFFF00000, 0xFFF01000, &mem_region_unmapped ); // H-UDI
147 register_mem_page_remapped_hook( mmu_ext_page_remapped, NULL );
150 /* Ensure the code regions are executable (64-bit only). Although it might
151 * be more portable to mmap these at runtime rather than using static decls
153 #if SIZEOF_VOID_P == 8
154 mem_unprotect( mmu_utlb_pages, sizeof(mmu_utlb_pages) );
155 mem_unprotect( mmu_utlb_1k_pages, sizeof(mmu_utlb_1k_pages) );
161 mmio_region_MMU_write( CCR, 0 );
162 mmio_region_MMU_write( MMUCR, 0 );
165 void MMU_save_state( FILE *f )
168 fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f );
169 fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f );
170 fwrite( &mmu_urc, sizeof(mmu_urc), 1, f );
171 fwrite( &mmu_urb, sizeof(mmu_urb), 1, f );
172 fwrite( &mmu_lrui, sizeof(mmu_lrui), 1, f );
173 fwrite( &mmu_asid, sizeof(mmu_asid), 1, f );
176 int MMU_load_state( FILE *f )
178 if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) {
181 if( fread( &mmu_utlb, sizeof(mmu_utlb), 1, f ) != 1 ) {
184 if( fread( &mmu_urc, sizeof(mmu_urc), 1, f ) != 1 ) {
187 if( fread( &mmu_urc, sizeof(mmu_urb), 1, f ) != 1 ) {
190 if( fread( &mmu_lrui, sizeof(mmu_lrui), 1, f ) != 1 ) {
193 if( fread( &mmu_asid, sizeof(mmu_asid), 1, f ) != 1 ) {
197 uint32_t mmucr = MMIO_READ(MMU,MMUCR);
198 mmu_urc_overflow = mmu_urc >= mmu_urb;
199 mmu_set_tlb_enabled(mmucr&MMUCR_AT);
200 mmu_set_storequeue_protected(mmucr&MMUCR_SQMD, mmucr&MMUCR_AT);
205 * LDTLB instruction implementation. Copies PTEH, PTEL and PTEA into the UTLB
206 * entry identified by MMUCR.URC. Does not modify MMUCR or the ITLB.
210 int urc = mmu_read_urc();
211 if( mmu_utlb[urc].flags & TLB_VALID )
212 mmu_utlb_remove_entry( urc );
213 mmu_utlb[urc].vpn = MMIO_READ(MMU, PTEH) & 0xFFFFFC00;
214 mmu_utlb[urc].asid = MMIO_READ(MMU, PTEH) & 0x000000FF;
215 mmu_utlb[urc].ppn = MMIO_READ(MMU, PTEL) & 0x1FFFFC00;
216 mmu_utlb[urc].flags = MMIO_READ(MMU, PTEL) & 0x00001FF;
217 mmu_utlb[urc].pcmcia = MMIO_READ(MMU, PTEA);
218 mmu_utlb[urc].mask = get_tlb_size_mask(mmu_utlb[urc].flags);
219 if( mmu_utlb[urc].flags & TLB_VALID )
220 mmu_utlb_insert_entry( urc );
224 MMIO_REGION_READ_FN( MMU, reg )
229 return MMIO_READ( MMU, MMUCR) | (mmu_read_urc()<<10) | ((mmu_urb&0x3F)<<18) | (mmu_lrui<<26);
231 return MMIO_READ( MMU, reg );
235 MMIO_REGION_READ_DEFSUBFNS(MMU)
237 MMIO_REGION_WRITE_FN( MMU, reg, val )
246 if( (val & 0xFF) != mmu_asid ) {
247 mmu_set_tlb_asid( val&0xFF );
248 sh4_icache.page_vma = -1; // invalidate icache as asid has changed
265 if( val & MMUCR_TI ) {
266 mmu_invalidate_tlb();
268 mmu_urc = (val >> 10) & 0x3F;
269 mmu_urb = (val >> 18) & 0x3F;
272 } else if( mmu_urc >= mmu_urb ) {
273 mmu_urc_overflow = TRUE;
275 mmu_lrui = (val >> 26) & 0x3F;
277 tmp = MMIO_READ( MMU, MMUCR );
278 if( (val ^ tmp) & (MMUCR_SQMD) ) {
279 mmu_set_storequeue_protected( val & MMUCR_SQMD, val&MMUCR_AT );
281 if( (val ^ tmp) & (MMUCR_AT) ) {
282 // AT flag has changed state - flush the xlt cache as all bets
283 // are off now. We also need to force an immediate exit from the
285 mmu_set_tlb_enabled( val & MMUCR_AT );
286 MMIO_WRITE( MMU, MMUCR, val );
287 sh4_core_exit( CORE_EXIT_FLUSH_ICACHE );
288 xlat_flush_cache(); // If we're not running, flush the cache anyway
292 CCN_set_cache_control( val );
296 /* Note that if the high bit is set, this appears to reset the machine.
297 * Not emulating this behaviour yet until we know why...
306 PMM_write_control(0, val);
310 PMM_write_control(1, val);
316 MMIO_WRITE( MMU, reg, val );
319 /********************** 1K Page handling ***********************/
320 /* Since we use 4K pages as our native page size, 1K pages need a bit of extra
321 * effort to manage - we justify this on the basis that most programs won't
322 * actually use 1K pages, so we may as well optimize for the common case.
324 * Implementation uses an intermediate page entry (the utlb_1k_entry) that
325 * redirects requests to the 'real' page entry. These are allocated on an
326 * as-needed basis, and returned to the pool when all subpages are empty.
328 static void mmu_utlb_1k_init()
331 for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
332 mmu_utlb_1k_free_list[i] = i;
333 mmu_utlb_1k_init_vtable( &mmu_utlb_1k_pages[i] );
335 mmu_utlb_1k_free_index = 0;
338 static struct utlb_1k_entry *mmu_utlb_1k_alloc()
340 assert( mmu_utlb_1k_free_index < UTLB_ENTRY_COUNT );
341 struct utlb_1k_entry *entry = &mmu_utlb_1k_pages[mmu_utlb_1k_free_list[mmu_utlb_1k_free_index++]];
345 static void mmu_utlb_1k_free( struct utlb_1k_entry *ent )
347 unsigned int entryNo = ent - &mmu_utlb_1k_pages[0];
348 assert( entryNo < UTLB_ENTRY_COUNT );
349 assert( mmu_utlb_1k_free_index > 0 );
350 mmu_utlb_1k_free_list[--mmu_utlb_1k_free_index] = entryNo;
354 /********************** Address space maintenance *************************/
357 * MMU accessor functions just increment URC - fixup here if necessary
359 static int mmu_read_urc()
361 if( mmu_urc_overflow ) {
362 if( mmu_urc >= 0x40 ) {
363 mmu_urc_overflow = FALSE;
373 static void mmu_register_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn )
375 int count = (end - start) >> 12;
376 mem_region_fn_t *ptr = &sh4_address_space[start>>12];
377 while( count-- > 0 ) {
381 static void mmu_register_user_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn )
383 int count = (end - start) >> 12;
384 mem_region_fn_t *ptr = &sh4_user_address_space[start>>12];
385 while( count-- > 0 ) {
390 static gboolean mmu_ext_page_remapped( sh4addr_t page, mem_region_fn_t fn, void *user_data )
393 if( (MMIO_READ(MMU,MMUCR)) & MMUCR_AT ) {
395 sh4_address_space[(page|0x80000000)>>12] = fn; /* Direct map to P1 and P2 */
396 sh4_address_space[(page|0xA0000000)>>12] = fn;
397 /* Scan UTLB and update any direct-referencing entries */
399 /* Direct map to U0, P0, P1, P2, P3 */
400 for( i=0; i<= 0xC0000000; i+= 0x20000000 ) {
401 sh4_address_space[(page|i)>>12] = fn;
403 for( i=0; i < 0x80000000; i+= 0x20000000 ) {
404 sh4_user_address_space[(page|i)>>12] = fn;
410 static void mmu_set_tlb_enabled( int tlb_on )
412 mem_region_fn_t *ptr, *uptr;
415 /* Reset the storequeue area */
418 mmu_register_mem_region(0x00000000, 0x80000000, &mem_region_tlb_miss );
419 mmu_register_mem_region(0xC0000000, 0xE0000000, &mem_region_tlb_miss );
420 mmu_register_user_mem_region(0x00000000, 0x80000000, &mem_region_tlb_miss );
422 /* Default SQ prefetch goes to TLB miss (?) */
423 mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue_miss );
424 mmu_register_user_mem_region( 0xE0000000, 0xE4000000, mmu_user_storequeue_regions->tlb_miss );
425 mmu_utlb_register_all();
427 for( i=0, ptr = sh4_address_space; i<7; i++, ptr += LXDREAM_PAGE_TABLE_ENTRIES ) {
428 memcpy( ptr, ext_address_space, sizeof(mem_region_fn_t) * LXDREAM_PAGE_TABLE_ENTRIES );
430 for( i=0, ptr = sh4_user_address_space; i<4; i++, ptr += LXDREAM_PAGE_TABLE_ENTRIES ) {
431 memcpy( ptr, ext_address_space, sizeof(mem_region_fn_t) * LXDREAM_PAGE_TABLE_ENTRIES );
434 mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
435 if( IS_STOREQUEUE_PROTECTED() ) {
436 mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue_sqmd );
438 mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
445 * Flip the SQMD switch - this is rather expensive, so will need to be changed if
446 * anything expects to do this frequently.
448 static void mmu_set_storequeue_protected( int protected, int tlb_on )
450 mem_region_fn_t nontlb_region;
454 mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_SQMD_REGIONS];
455 nontlb_region = &p4_region_storequeue_sqmd;
457 mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
458 nontlb_region = &p4_region_storequeue;
462 mmu_register_user_mem_region( 0xE0000000, 0xE4000000, mmu_user_storequeue_regions->tlb_miss );
463 for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
464 if( (mmu_utlb[i].vpn & 0xFC000000) == 0xE0000000 ) {
465 mmu_utlb_insert_entry(i);
469 mmu_register_user_mem_region( 0xE0000000, 0xE4000000, nontlb_region );
474 static void mmu_set_tlb_asid( uint32_t asid )
476 /* Scan for pages that need to be remapped */
478 if( IS_SV_ENABLED() ) {
479 for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
480 if( mmu_utlb[i].asid == mmu_asid &&
481 (mmu_utlb[i].flags & (TLB_VALID|TLB_SHARE)) == (TLB_VALID) ) {
482 // Matches old ASID - unmap out
483 if( !mmu_utlb_unmap_pages( FALSE, TRUE, mmu_utlb[i].vpn&mmu_utlb[i].mask,
484 get_tlb_size_pages(mmu_utlb[i].flags) ) )
485 mmu_utlb_remap_pages( FALSE, TRUE, i );
488 for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
489 if( mmu_utlb[i].asid == asid &&
490 (mmu_utlb[i].flags & (TLB_VALID|TLB_SHARE)) == (TLB_VALID) ) {
491 // Matches new ASID - map in
492 mmu_utlb_map_pages( NULL, mmu_utlb_pages[i].user_fn,
493 mmu_utlb[i].vpn&mmu_utlb[i].mask,
494 get_tlb_size_pages(mmu_utlb[i].flags) );
498 // Remap both Priv+user pages
499 for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
500 if( mmu_utlb[i].asid == mmu_asid &&
501 (mmu_utlb[i].flags & (TLB_VALID|TLB_SHARE)) == (TLB_VALID) ) {
502 if( !mmu_utlb_unmap_pages( TRUE, TRUE, mmu_utlb[i].vpn&mmu_utlb[i].mask,
503 get_tlb_size_pages(mmu_utlb[i].flags) ) )
504 mmu_utlb_remap_pages( TRUE, TRUE, i );
507 for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
508 if( mmu_utlb[i].asid == asid &&
509 (mmu_utlb[i].flags & (TLB_VALID|TLB_SHARE)) == (TLB_VALID) ) {
510 mmu_utlb_map_pages( &mmu_utlb_pages[i].fn, mmu_utlb_pages[i].user_fn,
511 mmu_utlb[i].vpn&mmu_utlb[i].mask,
512 get_tlb_size_pages(mmu_utlb[i].flags) );
520 static uint32_t get_tlb_size_mask( uint32_t flags )
522 switch( flags & TLB_SIZE_MASK ) {
523 case TLB_SIZE_1K: return MASK_1K;
524 case TLB_SIZE_4K: return MASK_4K;
525 case TLB_SIZE_64K: return MASK_64K;
526 case TLB_SIZE_1M: return MASK_1M;
527 default: return 0; /* Unreachable */
530 static uint32_t get_tlb_size_pages( uint32_t flags )
532 switch( flags & TLB_SIZE_MASK ) {
533 case TLB_SIZE_1K: return 0;
534 case TLB_SIZE_4K: return 1;
535 case TLB_SIZE_64K: return 16;
536 case TLB_SIZE_1M: return 256;
537 default: return 0; /* Unreachable */
542 * Add a new TLB entry mapping to the address space table. If any of the pages
543 * are already mapped, they are mapped to the TLB multi-hit page instead.
544 * @return FALSE if a TLB multihit situation was detected, otherwise TRUE.
546 static gboolean mmu_utlb_map_pages( mem_region_fn_t priv_page, mem_region_fn_t user_page, sh4addr_t start_addr, int npages )
548 mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
549 mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
550 struct utlb_default_regions *privdefs = &mmu_default_regions[DEFAULT_REGIONS];
551 struct utlb_default_regions *userdefs = privdefs;
553 gboolean mapping_ok = TRUE;
556 if( (start_addr & 0xFC000000) == 0xE0000000 ) {
557 /* Storequeue mapping */
558 privdefs = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
559 userdefs = mmu_user_storequeue_regions;
560 } else if( (start_addr & 0xE0000000) == 0xC0000000 ) {
561 user_page = NULL; /* No user access to P3 region */
562 } else if( start_addr >= 0x80000000 ) {
563 return TRUE; // No mapping - legal but meaningless
567 struct utlb_1k_entry *ent;
568 int i, idx = (start_addr >> 10) & 0x03;
569 if( IS_1K_PAGE_ENTRY(*ptr) ) {
570 ent = (struct utlb_1k_entry *)*ptr;
572 ent = mmu_utlb_1k_alloc();
573 /* New 1K struct - init to previous contents of region */
574 for( i=0; i<4; i++ ) {
575 ent->subpages[i] = *ptr;
576 ent->user_subpages[i] = *uptr;
579 *uptr = &ent->user_fn;
582 if( priv_page != NULL ) {
583 if( ent->subpages[idx] == privdefs->tlb_miss ) {
584 ent->subpages[idx] = priv_page;
587 ent->subpages[idx] = privdefs->tlb_multihit;
590 if( user_page != NULL ) {
591 if( ent->user_subpages[idx] == userdefs->tlb_miss ) {
592 ent->user_subpages[idx] = user_page;
595 ent->user_subpages[idx] = userdefs->tlb_multihit;
600 if( priv_page != NULL ) {
601 /* Privileged mapping only */
602 for( i=0; i<npages; i++ ) {
603 if( *ptr == privdefs->tlb_miss ) {
607 *ptr++ = privdefs->tlb_multihit;
611 if( user_page != NULL ) {
612 /* User mapping only (eg ASID change remap w/ SV=1) */
613 for( i=0; i<npages; i++ ) {
614 if( *uptr == userdefs->tlb_miss ) {
618 *uptr++ = userdefs->tlb_multihit;
628 * Remap any pages within the region covered by entryNo, but not including
629 * entryNo itself. This is used to reestablish pages that were previously
630 * covered by a multi-hit exception region when one of the pages is removed.
632 static void mmu_utlb_remap_pages( gboolean remap_priv, gboolean remap_user, int entryNo )
634 int mask = mmu_utlb[entryNo].mask;
635 uint32_t remap_addr = mmu_utlb[entryNo].vpn & mask;
638 for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
639 if( i != entryNo && (mmu_utlb[i].vpn & mask) == remap_addr && (mmu_utlb[i].flags & TLB_VALID) ) {
640 /* Overlapping region */
641 mem_region_fn_t priv_page = (remap_priv ? &mmu_utlb_pages[i].fn : NULL);
642 mem_region_fn_t user_page = (remap_priv ? mmu_utlb_pages[i].user_fn : NULL);
646 if( mmu_utlb[i].mask >= mask ) {
647 /* entry is no larger than the area we're replacing - map completely */
648 start_addr = mmu_utlb[i].vpn & mmu_utlb[i].mask;
649 npages = get_tlb_size_pages( mmu_utlb[i].flags );
651 /* Otherwise map subset - region covered by removed page */
652 start_addr = remap_addr;
653 npages = get_tlb_size_pages( mmu_utlb[entryNo].flags );
656 if( (mmu_utlb[i].flags & TLB_SHARE) || mmu_utlb[i].asid == mmu_asid ) {
657 mmu_utlb_map_pages( priv_page, user_page, start_addr, npages );
658 } else if( IS_SV_ENABLED() ) {
659 mmu_utlb_map_pages( priv_page, NULL, start_addr, npages );
667 * Remove a previous TLB mapping (replacing them with the TLB miss region).
668 * @return FALSE if any pages were previously mapped to the TLB multihit page,
669 * otherwise TRUE. In either case, all pages in the region are cleared to TLB miss.
671 static gboolean mmu_utlb_unmap_pages( gboolean unmap_priv, gboolean unmap_user, sh4addr_t start_addr, int npages )
673 mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
674 mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
675 struct utlb_default_regions *privdefs = &mmu_default_regions[DEFAULT_REGIONS];
676 struct utlb_default_regions *userdefs = privdefs;
678 gboolean unmapping_ok = TRUE;
681 if( (start_addr & 0xFC000000) == 0xE0000000 ) {
682 /* Storequeue mapping */
683 privdefs = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
684 userdefs = mmu_user_storequeue_regions;
685 } else if( (start_addr & 0xE0000000) == 0xC0000000 ) {
687 } else if( start_addr >= 0x80000000 ) {
688 return TRUE; // No mapping - legal but meaningless
691 if( npages == 0 ) { // 1K page
692 assert( IS_1K_PAGE_ENTRY( *ptr ) );
693 struct utlb_1k_entry *ent = (struct utlb_1k_entry *)*ptr;
694 int i, idx = (start_addr >> 10) & 0x03, mergeable=1;
695 if( ent->subpages[idx] == privdefs->tlb_multihit ) {
696 unmapping_ok = FALSE;
699 ent->subpages[idx] = privdefs->tlb_miss;
701 ent->user_subpages[idx] = userdefs->tlb_miss;
703 /* If all 4 subpages have the same content, merge them together and
704 * release the 1K entry
706 mem_region_fn_t priv_page = ent->subpages[0];
707 mem_region_fn_t user_page = ent->user_subpages[0];
708 for( i=1; i<4; i++ ) {
709 if( priv_page != ent->subpages[i] || user_page != ent->user_subpages[i] ) {
715 mmu_utlb_1k_free(ent);
721 /* Privileged (un)mapping */
722 for( i=0; i<npages; i++ ) {
723 if( *ptr == privdefs->tlb_multihit ) {
724 unmapping_ok = FALSE;
726 *ptr++ = privdefs->tlb_miss;
730 /* User (un)mapping */
731 for( i=0; i<npages; i++ ) {
732 if( *uptr == userdefs->tlb_multihit ) {
733 unmapping_ok = FALSE;
735 *uptr++ = userdefs->tlb_miss;
743 static void mmu_utlb_insert_entry( int entry )
745 struct utlb_entry *ent = &mmu_utlb[entry];
746 mem_region_fn_t page = &mmu_utlb_pages[entry].fn;
747 mem_region_fn_t upage;
748 sh4addr_t start_addr = ent->vpn & ent->mask;
749 int npages = get_tlb_size_pages(ent->flags);
751 if( (start_addr & 0xFC000000) == 0xE0000000 ) {
752 /* Store queue mappings are a bit different - normal access is fixed to
753 * the store queue register block, and we only map prefetches through
756 mmu_utlb_init_storequeue_vtable( ent, &mmu_utlb_pages[entry] );
758 if( (ent->flags & TLB_USERMODE) == 0 ) {
759 upage = mmu_user_storequeue_regions->tlb_prot;
760 } else if( IS_STOREQUEUE_PROTECTED() ) {
761 upage = &p4_region_storequeue_sqmd;
768 if( (ent->flags & TLB_USERMODE) == 0 ) {
769 upage = &mem_region_tlb_protected;
774 if( (ent->flags & TLB_WRITABLE) == 0 ) {
775 page->write_long = (mem_write_fn_t)tlb_protected_write;
776 page->write_word = (mem_write_fn_t)tlb_protected_write;
777 page->write_byte = (mem_write_fn_t)tlb_protected_write;
778 page->write_burst = (mem_write_burst_fn_t)tlb_protected_write;
779 page->read_byte_for_write = (mem_read_fn_t)tlb_protected_read_for_write;
780 mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], FALSE );
781 } else if( (ent->flags & TLB_DIRTY) == 0 ) {
782 page->write_long = (mem_write_fn_t)tlb_initial_write;
783 page->write_word = (mem_write_fn_t)tlb_initial_write;
784 page->write_byte = (mem_write_fn_t)tlb_initial_write;
785 page->write_burst = (mem_write_burst_fn_t)tlb_initial_write;
786 page->read_byte_for_write = (mem_read_fn_t)tlb_initial_read_for_write;
787 mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], FALSE );
789 mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], TRUE );
793 mmu_utlb_pages[entry].user_fn = upage;
795 /* Is page visible? */
796 if( (ent->flags & TLB_SHARE) || ent->asid == mmu_asid ) {
797 mmu_utlb_map_pages( page, upage, start_addr, npages );
798 } else if( IS_SV_ENABLED() ) {
799 mmu_utlb_map_pages( page, NULL, start_addr, npages );
803 static void mmu_utlb_remove_entry( int entry )
806 struct utlb_entry *ent = &mmu_utlb[entry];
807 sh4addr_t start_addr = ent->vpn&ent->mask;
808 mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
809 mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
811 int npages = get_tlb_size_pages(ent->flags);
813 if( (ent->flags & TLB_SHARE) || ent->asid == mmu_asid ) {
815 } else if( IS_SV_ENABLED() ) {
818 return; // Not mapped
821 gboolean clean_unmap = mmu_utlb_unmap_pages( TRUE, unmap_user, start_addr, npages );
824 mmu_utlb_remap_pages( TRUE, unmap_user, entry );
828 static void mmu_utlb_register_all()
831 for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
832 if( mmu_utlb[i].flags & TLB_VALID )
833 mmu_utlb_insert_entry( i );
837 static void mmu_invalidate_tlb()
840 for( i=0; i<ITLB_ENTRY_COUNT; i++ ) {
841 mmu_itlb[i].flags &= (~TLB_VALID);
843 if( IS_TLB_ENABLED() ) {
844 for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
845 if( mmu_utlb[i].flags & TLB_VALID ) {
846 mmu_utlb_remove_entry( i );
850 for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
851 mmu_utlb[i].flags &= (~TLB_VALID);
855 /******************************************************************************/
856 /* MMU TLB address translation */
857 /******************************************************************************/
860 * Translate a 32-bit address into a UTLB entry number. Does not check for
861 * page protection etc.
862 * @return the entryNo if found, -1 if not found, and -2 for a multi-hit.
864 int mmu_utlb_entry_for_vpn( uint32_t vpn )
867 mem_region_fn_t fn = sh4_address_space[vpn>>12];
868 if( fn >= &mmu_utlb_pages[0].fn && fn < &mmu_utlb_pages[UTLB_ENTRY_COUNT].fn ) {
869 return ((struct utlb_page_entry *)fn) - &mmu_utlb_pages[0];
870 } else if( fn >= &mmu_utlb_1k_pages[0].fn && fn < &mmu_utlb_1k_pages[UTLB_ENTRY_COUNT].fn ) {
871 struct utlb_1k_entry *ent = (struct utlb_1k_entry *)fn;
872 fn = ent->subpages[(vpn>>10)&0x03];
873 if( fn >= &mmu_utlb_pages[0].fn && fn < &mmu_utlb_pages[UTLB_ENTRY_COUNT].fn ) {
874 return ((struct utlb_page_entry *)fn) - &mmu_utlb_pages[0];
877 if( fn == &mem_region_tlb_multihit ) {
886 * Perform the actual utlb lookup w/ asid matching.
887 * Possible utcomes are:
888 * 0..63 Single match - good, return entry found
889 * -1 No match - raise a tlb data miss exception
890 * -2 Multiple matches - raise a multi-hit exception (reset)
891 * @param vpn virtual address to resolve
892 * @return the resultant UTLB entry, or an error.
894 static inline int mmu_utlb_lookup_vpn_asid( uint32_t vpn )
900 if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
904 for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
905 if( (mmu_utlb[i].flags & TLB_VALID) &&
906 ((mmu_utlb[i].flags & TLB_SHARE) || mmu_asid == mmu_utlb[i].asid) &&
907 ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
918 * Perform the actual utlb lookup matching on vpn only
919 * Possible utcomes are:
920 * 0..63 Single match - good, return entry found
921 * -1 No match - raise a tlb data miss exception
922 * -2 Multiple matches - raise a multi-hit exception (reset)
923 * @param vpn virtual address to resolve
924 * @return the resultant UTLB entry, or an error.
926 static inline int mmu_utlb_lookup_vpn( uint32_t vpn )
932 if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
936 for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
937 if( (mmu_utlb[i].flags & TLB_VALID) &&
938 ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
950 * Update the ITLB by replacing the LRU entry with the specified UTLB entry.
951 * @return the number (0-3) of the replaced entry.
953 static int inline mmu_itlb_update_from_utlb( int entryNo )
956 /* Determine entry to replace based on lrui */
957 if( (mmu_lrui & 0x38) == 0x38 ) {
959 mmu_lrui = mmu_lrui & 0x07;
960 } else if( (mmu_lrui & 0x26) == 0x06 ) {
962 mmu_lrui = (mmu_lrui & 0x19) | 0x20;
963 } else if( (mmu_lrui & 0x15) == 0x01 ) {
965 mmu_lrui = (mmu_lrui & 0x3E) | 0x14;
966 } else { // Note - gets invalid entries too
968 mmu_lrui = (mmu_lrui | 0x0B);
971 mmu_itlb[replace].vpn = mmu_utlb[entryNo].vpn;
972 mmu_itlb[replace].mask = mmu_utlb[entryNo].mask;
973 mmu_itlb[replace].ppn = mmu_utlb[entryNo].ppn;
974 mmu_itlb[replace].asid = mmu_utlb[entryNo].asid;
975 mmu_itlb[replace].flags = mmu_utlb[entryNo].flags & 0x01DA;
980 * Perform the actual itlb lookup w/ asid protection
981 * Possible utcomes are:
982 * 0..63 Single match - good, return entry found
983 * -1 No match - raise a tlb data miss exception
984 * -2 Multiple matches - raise a multi-hit exception (reset)
985 * @param vpn virtual address to resolve
986 * @return the resultant ITLB entry, or an error.
988 static inline int mmu_itlb_lookup_vpn_asid( uint32_t vpn )
993 for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
994 if( (mmu_itlb[i].flags & TLB_VALID) &&
995 ((mmu_itlb[i].flags & TLB_SHARE) || mmu_asid == mmu_itlb[i].asid) &&
996 ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
1004 if( result == -1 ) {
1005 int utlbEntry = mmu_utlb_entry_for_vpn( vpn );
1006 if( utlbEntry < 0 ) {
1009 return mmu_itlb_update_from_utlb( utlbEntry );
1014 case 0: mmu_lrui = (mmu_lrui & 0x07); break;
1015 case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
1016 case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
1017 case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
1024 * Perform the actual itlb lookup on vpn only
1025 * Possible utcomes are:
1026 * 0..63 Single match - good, return entry found
1027 * -1 No match - raise a tlb data miss exception
1028 * -2 Multiple matches - raise a multi-hit exception (reset)
1029 * @param vpn virtual address to resolve
1030 * @return the resultant ITLB entry, or an error.
1032 static inline int mmu_itlb_lookup_vpn( uint32_t vpn )
1037 for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
1038 if( (mmu_itlb[i].flags & TLB_VALID) &&
1039 ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
1040 if( result != -1 ) {
1047 if( result == -1 ) {
1048 int utlbEntry = mmu_utlb_lookup_vpn( vpn );
1049 if( utlbEntry < 0 ) {
1052 return mmu_itlb_update_from_utlb( utlbEntry );
1057 case 0: mmu_lrui = (mmu_lrui & 0x07); break;
1058 case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
1059 case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
1060 case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
1067 * Update the icache for an untranslated address
1069 static inline void mmu_update_icache_phys( sh4addr_t addr )
1071 if( (addr & 0x1C000000) == 0x0C000000 ) {
1073 sh4_icache.page_vma = addr & 0xFF000000;
1074 sh4_icache.page_ppa = 0x0C000000;
1075 sh4_icache.mask = 0xFF000000;
1076 sh4_icache.page = dc_main_ram;
1077 } else if( (addr & 0x1FE00000) == 0 ) {
1079 sh4_icache.page_vma = addr & 0xFFE00000;
1080 sh4_icache.page_ppa = 0;
1081 sh4_icache.mask = 0xFFE00000;
1082 sh4_icache.page = dc_boot_rom;
1085 sh4_icache.page_vma = -1;
1090 * Update the sh4_icache structure to describe the page(s) containing the
1091 * given vma. If the address does not reference a RAM/ROM region, the icache
1092 * will be invalidated instead.
1093 * If AT is on, this method will raise TLB exceptions normally
1094 * (hence this method should only be used immediately prior to execution of
1095 * code), and otherwise will set the icache according to the matching TLB entry.
1096 * If AT is off, this method will set the entire referenced RAM/ROM region in
1098 * @return TRUE if the update completed (successfully or otherwise), FALSE
1099 * if an exception was raised.
1101 gboolean FASTCALL mmu_update_icache( sh4vma_t addr )
1104 if( IS_SH4_PRIVMODE() ) {
1105 if( addr & 0x80000000 ) {
1106 if( addr < 0xC0000000 ) {
1107 /* P1, P2 and P4 regions are pass-through (no translation) */
1108 mmu_update_icache_phys(addr);
1110 } else if( addr >= 0xE0000000 && addr < 0xFFFFFF00 ) {
1111 RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
1116 uint32_t mmucr = MMIO_READ(MMU,MMUCR);
1117 if( (mmucr & MMUCR_AT) == 0 ) {
1118 mmu_update_icache_phys(addr);
1122 if( (mmucr & MMUCR_SV) == 0 )
1123 entryNo = mmu_itlb_lookup_vpn_asid( addr );
1125 entryNo = mmu_itlb_lookup_vpn( addr );
1127 if( addr & 0x80000000 ) {
1128 RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
1132 uint32_t mmucr = MMIO_READ(MMU,MMUCR);
1133 if( (mmucr & MMUCR_AT) == 0 ) {
1134 mmu_update_icache_phys(addr);
1138 entryNo = mmu_itlb_lookup_vpn_asid( addr );
1140 if( entryNo != -1 && (mmu_itlb[entryNo].flags & TLB_USERMODE) == 0 ) {
1141 RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
1148 RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
1151 RAISE_TLB_MULTIHIT_ERROR(addr);
1154 sh4_icache.page_ppa = mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask;
1155 sh4_icache.page = mem_get_region( sh4_icache.page_ppa );
1156 if( sh4_icache.page == NULL ) {
1157 sh4_icache.page_vma = -1;
1159 sh4_icache.page_vma = mmu_itlb[entryNo].vpn & mmu_itlb[entryNo].mask;
1160 sh4_icache.mask = mmu_itlb[entryNo].mask;
1167 * Translate address for disassembly purposes (ie performs an instruction
1168 * lookup) - does not raise exceptions or modify any state, and ignores
1169 * protection bits. Returns the translated address, or MMU_VMA_ERROR
1170 * on translation failure.
1172 sh4addr_t FASTCALL mmu_vma_to_phys_disasm( sh4vma_t vma )
1174 if( vma & 0x80000000 ) {
1175 if( vma < 0xC0000000 ) {
1176 /* P1, P2 and P4 regions are pass-through (no translation) */
1177 return VMA_TO_EXT_ADDR(vma);
1178 } else if( vma >= 0xE0000000 && vma < 0xFFFFFF00 ) {
1179 /* Not translatable */
1180 return MMU_VMA_ERROR;
1184 uint32_t mmucr = MMIO_READ(MMU,MMUCR);
1185 if( (mmucr & MMUCR_AT) == 0 ) {
1186 return VMA_TO_EXT_ADDR(vma);
1189 int entryNo = mmu_itlb_lookup_vpn( vma );
1190 if( entryNo == -2 ) {
1191 entryNo = mmu_itlb_lookup_vpn_asid( vma );
1194 return MMU_VMA_ERROR;
1196 return (mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask) |
1197 (vma & (~mmu_itlb[entryNo].mask));
1201 /********************** TLB Direct-Access Regions ***************************/
1202 #ifdef HAVE_FRAME_ADDRESS
1203 #define EXCEPTION_EXIT() do{ *(((void **)__builtin_frame_address(0))+1) = exc; } while(0)
1205 #define EXCEPTION_EXIT() sh4_core_exit(CORE_EXIT_EXCEPTION)
1209 #define ITLB_ENTRY(addr) ((addr>>7)&0x03)
1211 int32_t FASTCALL mmu_itlb_addr_read( sh4addr_t addr )
1213 struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
1214 return ent->vpn | ent->asid | (ent->flags & TLB_VALID);
1217 void FASTCALL mmu_itlb_addr_write( sh4addr_t addr, uint32_t val )
1219 struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
1220 ent->vpn = val & 0xFFFFFC00;
1221 ent->asid = val & 0x000000FF;
1222 ent->flags = (ent->flags & ~(TLB_VALID)) | (val&TLB_VALID);
1225 int32_t FASTCALL mmu_itlb_data_read( sh4addr_t addr )
1227 struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
1228 return (ent->ppn & 0x1FFFFC00) | ent->flags;
1231 void FASTCALL mmu_itlb_data_write( sh4addr_t addr, uint32_t val )
1233 struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
1234 ent->ppn = val & 0x1FFFFC00;
1235 ent->flags = val & 0x00001DA;
1236 ent->mask = get_tlb_size_mask(val);
1237 if( ent->ppn >= 0x1C000000 )
1238 ent->ppn |= 0xE0000000;
1241 #define UTLB_ENTRY(addr) ((addr>>8)&0x3F)
1242 #define UTLB_ASSOC(addr) (addr&0x80)
1243 #define UTLB_DATA2(addr) (addr&0x00800000)
1245 int32_t FASTCALL mmu_utlb_addr_read( sh4addr_t addr )
1247 struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
1248 return ent->vpn | ent->asid | (ent->flags & TLB_VALID) |
1249 ((ent->flags & TLB_DIRTY)<<7);
1251 int32_t FASTCALL mmu_utlb_data_read( sh4addr_t addr )
1253 struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
1254 if( UTLB_DATA2(addr) ) {
1257 return (ent->ppn&0x1FFFFC00) | ent->flags;
1262 * Find a UTLB entry for the associative TLB write - same as the normal
1263 * lookup but ignores the valid bit.
1265 static inline int mmu_utlb_lookup_assoc( uint32_t vpn, uint32_t asid )
1269 for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
1270 if( (mmu_utlb[i].flags & TLB_VALID) &&
1271 ((mmu_utlb[i].flags & TLB_SHARE) || asid == mmu_utlb[i].asid) &&
1272 ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
1273 if( result != -1 ) {
1274 fprintf( stderr, "TLB Multi hit: %d %d\n", result, i );
1284 * Find a ITLB entry for the associative TLB write - same as the normal
1285 * lookup but ignores the valid bit.
1287 static inline int mmu_itlb_lookup_assoc( uint32_t vpn, uint32_t asid )
1291 for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
1292 if( (mmu_itlb[i].flags & TLB_VALID) &&
1293 ((mmu_itlb[i].flags & TLB_SHARE) || asid == mmu_itlb[i].asid) &&
1294 ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
1295 if( result != -1 ) {
1304 void FASTCALL mmu_utlb_addr_write( sh4addr_t addr, uint32_t val, void *exc )
1306 if( UTLB_ASSOC(addr) ) {
1307 int utlb = mmu_utlb_lookup_assoc( val, mmu_asid );
1309 struct utlb_entry *ent = &mmu_utlb[utlb];
1310 uint32_t old_flags = ent->flags;
1311 ent->flags = ent->flags & ~(TLB_DIRTY|TLB_VALID);
1312 ent->flags |= (val & TLB_VALID);
1313 ent->flags |= ((val & 0x200)>>7);
1314 if( ((old_flags^ent->flags) & (TLB_VALID|TLB_DIRTY)) != 0 ) {
1315 if( old_flags & TLB_VALID )
1316 mmu_utlb_remove_entry( utlb );
1317 if( ent->flags & TLB_VALID )
1318 mmu_utlb_insert_entry( utlb );
1322 int itlb = mmu_itlb_lookup_assoc( val, mmu_asid );
1324 struct itlb_entry *ent = &mmu_itlb[itlb];
1325 ent->flags = (ent->flags & (~TLB_VALID)) | (val & TLB_VALID);
1328 if( itlb == -2 || utlb == -2 ) {
1329 RAISE_TLB_MULTIHIT_ERROR(addr);
1334 struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
1335 if( ent->flags & TLB_VALID )
1336 mmu_utlb_remove_entry( UTLB_ENTRY(addr) );
1337 ent->vpn = (val & 0xFFFFFC00);
1338 ent->asid = (val & 0xFF);
1339 ent->flags = (ent->flags & ~(TLB_DIRTY|TLB_VALID));
1340 ent->flags |= (val & TLB_VALID);
1341 ent->flags |= ((val & 0x200)>>7);
1342 if( ent->flags & TLB_VALID )
1343 mmu_utlb_insert_entry( UTLB_ENTRY(addr) );
1347 void FASTCALL mmu_utlb_data_write( sh4addr_t addr, uint32_t val )
1349 struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
1350 if( UTLB_DATA2(addr) ) {
1351 ent->pcmcia = val & 0x0000000F;
1353 if( ent->flags & TLB_VALID )
1354 mmu_utlb_remove_entry( UTLB_ENTRY(addr) );
1355 ent->ppn = (val & 0x1FFFFC00);
1356 ent->flags = (val & 0x000001FF);
1357 ent->mask = get_tlb_size_mask(val);
1358 if( ent->flags & TLB_VALID )
1359 mmu_utlb_insert_entry( UTLB_ENTRY(addr) );
1363 struct mem_region_fn p4_region_itlb_addr = {
1364 mmu_itlb_addr_read, mmu_itlb_addr_write,
1365 mmu_itlb_addr_read, mmu_itlb_addr_write,
1366 mmu_itlb_addr_read, mmu_itlb_addr_write,
1367 unmapped_read_burst, unmapped_write_burst,
1368 unmapped_prefetch, mmu_itlb_addr_read };
1369 struct mem_region_fn p4_region_itlb_data = {
1370 mmu_itlb_data_read, mmu_itlb_data_write,
1371 mmu_itlb_data_read, mmu_itlb_data_write,
1372 mmu_itlb_data_read, mmu_itlb_data_write,
1373 unmapped_read_burst, unmapped_write_burst,
1374 unmapped_prefetch, mmu_itlb_data_read };
1375 struct mem_region_fn p4_region_utlb_addr = {
1376 mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
1377 mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
1378 mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
1379 unmapped_read_burst, unmapped_write_burst,
1380 unmapped_prefetch, mmu_utlb_addr_read };
1381 struct mem_region_fn p4_region_utlb_data = {
1382 mmu_utlb_data_read, mmu_utlb_data_write,
1383 mmu_utlb_data_read, mmu_utlb_data_write,
1384 mmu_utlb_data_read, mmu_utlb_data_write,
1385 unmapped_read_burst, unmapped_write_burst,
1386 unmapped_prefetch, mmu_utlb_data_read };
1388 /********************** Error regions **************************/
1390 static void FASTCALL address_error_read( sh4addr_t addr, void *exc )
1392 RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
1396 static void FASTCALL address_error_read_for_write( sh4addr_t addr, void *exc )
1398 RAISE_MEM_ERROR(EXC_DATA_ADDR_WRITE, addr);
1402 static void FASTCALL address_error_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
1404 RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
1408 static void FASTCALL address_error_write( sh4addr_t addr, uint32_t val, void *exc )
1410 RAISE_MEM_ERROR(EXC_DATA_ADDR_WRITE, addr);
1414 static void FASTCALL tlb_miss_read( sh4addr_t addr, void *exc )
1417 RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
1421 static void FASTCALL tlb_miss_read_for_write( sh4addr_t addr, void *exc )
1424 RAISE_TLB_ERROR(EXC_TLB_MISS_WRITE, addr);
1428 static void FASTCALL tlb_miss_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
1431 RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
1435 static void FASTCALL tlb_miss_write( sh4addr_t addr, uint32_t val, void *exc )
1438 RAISE_TLB_ERROR(EXC_TLB_MISS_WRITE, addr);
1442 static int32_t FASTCALL tlb_protected_read( sh4addr_t addr, void *exc )
1445 RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
1450 static int32_t FASTCALL tlb_protected_read_for_write( sh4addr_t addr, void *exc )
1453 RAISE_MEM_ERROR(EXC_TLB_PROT_WRITE, addr);
1458 static int32_t FASTCALL tlb_protected_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
1461 RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
1466 static void FASTCALL tlb_protected_write( sh4addr_t addr, uint32_t val, void *exc )
1469 RAISE_MEM_ERROR(EXC_TLB_PROT_WRITE, addr);
1473 static void FASTCALL tlb_initial_write( sh4addr_t addr, uint32_t val, void *exc )
1476 RAISE_MEM_ERROR(EXC_INIT_PAGE_WRITE, addr);
1480 static int32_t FASTCALL tlb_initial_read_for_write( sh4addr_t addr, void *exc )
1483 RAISE_MEM_ERROR(EXC_INIT_PAGE_WRITE, addr);
1488 static int32_t FASTCALL tlb_multi_hit_read( sh4addr_t addr, void *exc )
1490 sh4_raise_tlb_multihit(addr);
1495 static int32_t FASTCALL tlb_multi_hit_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
1497 sh4_raise_tlb_multihit(addr);
1501 static void FASTCALL tlb_multi_hit_write( sh4addr_t addr, uint32_t val, void *exc )
1503 sh4_raise_tlb_multihit(addr);
1508 * Note: Per sec 4.6.4 of the SH7750 manual, SQ
1510 struct mem_region_fn mem_region_address_error = {
1511 (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
1512 (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
1513 (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
1514 (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
1515 unmapped_prefetch, (mem_read_fn_t)address_error_read_for_write };
1517 struct mem_region_fn mem_region_tlb_miss = {
1518 (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
1519 (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
1520 (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
1521 (mem_read_burst_fn_t)tlb_miss_read_burst, (mem_write_burst_fn_t)tlb_miss_write,
1522 unmapped_prefetch, (mem_read_fn_t)tlb_miss_read_for_write };
1524 struct mem_region_fn mem_region_tlb_protected = {
1525 (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
1526 (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
1527 (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
1528 (mem_read_burst_fn_t)tlb_protected_read_burst, (mem_write_burst_fn_t)tlb_protected_write,
1529 unmapped_prefetch, (mem_read_fn_t)tlb_protected_read_for_write };
1531 struct mem_region_fn mem_region_tlb_multihit = {
1532 (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
1533 (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
1534 (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
1535 (mem_read_burst_fn_t)tlb_multi_hit_read_burst, (mem_write_burst_fn_t)tlb_multi_hit_write,
1536 (mem_prefetch_fn_t)tlb_multi_hit_read, (mem_read_fn_t)tlb_multi_hit_read };
1539 /* Store-queue regions */
1540 /* These are a bit of a pain - the first 8 fields are controlled by SQMD, while
1541 * the final (prefetch) is controlled by the actual TLB settings (plus SQMD in
1542 * some cases), in contrast to the ordinary fields above.
1544 * There is probably a simpler way to do this.
1547 struct mem_region_fn p4_region_storequeue = {
1548 ccn_storequeue_read_long, ccn_storequeue_write_long,
1549 unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
1550 unmapped_read_long, unmapped_write_long,
1551 unmapped_read_burst, unmapped_write_burst,
1552 ccn_storequeue_prefetch, unmapped_read_long };
1554 struct mem_region_fn p4_region_storequeue_miss = {
1555 ccn_storequeue_read_long, ccn_storequeue_write_long,
1556 unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
1557 unmapped_read_long, unmapped_write_long,
1558 unmapped_read_burst, unmapped_write_burst,
1559 (mem_prefetch_fn_t)tlb_miss_read, unmapped_read_long };
1561 struct mem_region_fn p4_region_storequeue_multihit = {
1562 ccn_storequeue_read_long, ccn_storequeue_write_long,
1563 unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
1564 unmapped_read_long, unmapped_write_long,
1565 unmapped_read_burst, unmapped_write_burst,
1566 (mem_prefetch_fn_t)tlb_multi_hit_read, unmapped_read_long };
1568 struct mem_region_fn p4_region_storequeue_protected = {
1569 ccn_storequeue_read_long, ccn_storequeue_write_long,
1570 unmapped_read_long, unmapped_write_long,
1571 unmapped_read_long, unmapped_write_long,
1572 unmapped_read_burst, unmapped_write_burst,
1573 (mem_prefetch_fn_t)tlb_protected_read, unmapped_read_long };
1575 struct mem_region_fn p4_region_storequeue_sqmd = {
1576 (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
1577 (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
1578 (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
1579 (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
1580 (mem_prefetch_fn_t)address_error_read, (mem_read_fn_t)address_error_read_for_write };
1582 struct mem_region_fn p4_region_storequeue_sqmd_miss = {
1583 (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
1584 (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
1585 (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
1586 (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
1587 (mem_prefetch_fn_t)tlb_miss_read, (mem_read_fn_t)address_error_read_for_write };
1589 struct mem_region_fn p4_region_storequeue_sqmd_multihit = {
1590 (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
1591 (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
1592 (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
1593 (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
1594 (mem_prefetch_fn_t)tlb_multi_hit_read, (mem_read_fn_t)address_error_read_for_write };
1596 struct mem_region_fn p4_region_storequeue_sqmd_protected = {
1597 (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
1598 (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
1599 (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
1600 (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
1601 (mem_prefetch_fn_t)tlb_protected_read, (mem_read_fn_t)address_error_read_for_write };
.