/**

  * $Id: sh4core.in,v 1.7 2007-09-18 09:14:20 nkeynes Exp $

  * 

  * SH4 emulation core, and parent module for all the SH4 peripheral

  * modules.

  *

  * Copyright (c) 2005 Nathan Keynes.

  *

  * This program is free software; you can redistribute it and/or modify

  * it under the terms of the GNU General Public License as published by

  * the Free Software Foundation; either version 2 of the License, or

  * (at your option) any later version.

  *

  * This program is distributed in the hope that it will be useful,

  * but WITHOUT ANY WARRANTY; without even the implied warranty of

  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

  * GNU General Public License for more details.

  */

 #define MODULE sh4_module

 #include <math.h>

 #include "dream.h"

 #include "sh4/sh4core.h"

 #include "sh4/sh4mmio.h"

 #include "sh4/intc.h"

 #include "mem.h"

 #include "clock.h"

 #include "syscall.h"

 #define SH4_CALLTRACE 1

 #define MAX_INT 0x7FFFFFFF

 #define MIN_INT 0x80000000

 #define MAX_INTF 2147483647.0

 #define MIN_INTF -2147483648.0

 #define EXV_EXCEPTION    0x100  /* General exception vector */

 #define EXV_TLBMISS      0x400  /* TLB-miss exception vector */

 #define EXV_INTERRUPT    0x600  /* External interrupt vector */

 /********************** SH4 Module Definition ****************************/

 uint32_t sh4_run_slice( uint32_t );

 uint16_t *sh4_icache = NULL;

 uint32_t sh4_icache_addr = 0;

 uint32_t sh4_run_slice( uint32_t nanosecs ) 

 {

     int i;

     sh4r.slice_cycle = 0;

     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {

 	if( sh4r.event_pending < nanosecs ) {

 	    sh4r.sh4_state = SH4_STATE_RUNNING;

 	    sh4r.slice_cycle = sh4r.event_pending;

 	}

     }

     if( sh4_breakpoint_count == 0 ) {

 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {

 	    if( SH4_EVENT_PENDING() ) {

 		if( sh4r.event_types & PENDING_EVENT ) {

 		    event_execute();

 		}

 		/* Eventq execute may (quite likely) deliver an immediate IRQ */

 		if( sh4r.event_types & PENDING_IRQ ) {

 		    sh4_accept_interrupt();

 		}

 	    }

 	    //	    sh4_stats_add( sh4r.pc );

 	    if( !sh4_execute_instruction() ) {

 		break;

 	    }

 	}

     } else {

 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {

 	    if( SH4_EVENT_PENDING() ) {

 		if( sh4r.event_types & PENDING_EVENT ) {

 		    event_execute();

 		}

 		/* Eventq execute may (quite likely) deliver an immediate IRQ */

 		if( sh4r.event_types & PENDING_IRQ ) {

 		    sh4_accept_interrupt();

 		}

 	    }

 	    if( !sh4_execute_instruction() )

 		break;

 #ifdef ENABLE_DEBUG_MODE

 	    for( i=0; i<sh4_breakpoint_count; i++ ) {

 		if( sh4_breakpoints[i].address == sh4r.pc ) {

 		    break;

 		}

 	    }

 	    if( i != sh4_breakpoint_count ) {

 		dreamcast_stop();

 		if( sh4_breakpoints[i].type == BREAK_ONESHOT )

 		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );

 		break;

 	    }

 #endif	

 	}

     }

     /* If we aborted early, but the cpu is still technically running,

      * we're doing a hard abort - cut the timeslice back to what we

      * actually executed

      */

     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {

 	nanosecs = sh4r.slice_cycle;

     }

     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {

 	TMU_run_slice( nanosecs );

 	SCIF_run_slice( nanosecs );

     }

     return nanosecs;

 }

 /********************** SH4 emulation core  ****************************/

 void sh4_set_pc( int pc )

 {

     sh4r.pc = pc;

     sh4r.new_pc = pc+2;

 }

 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)

 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)

 #if(SH4_CALLTRACE == 1)

 #define MAX_CALLSTACK 32

 static struct call_stack {

     sh4addr_t call_addr;

     sh4addr_t target_addr;

     sh4addr_t stack_pointer;

 } call_stack[MAX_CALLSTACK];

 static int call_stack_depth = 0;

 int sh4_call_trace_on = 0;

 static inline trace_call( sh4addr_t source, sh4addr_t dest ) 

 {

     if( call_stack_depth < MAX_CALLSTACK ) {

 	call_stack[call_stack_depth].call_addr = source;

 	call_stack[call_stack_depth].target_addr = dest;

 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];

     }

     call_stack_depth++;

 }

 static inline trace_return( sh4addr_t source, sh4addr_t dest )

 {

     if( call_stack_depth > 0 ) {

 	call_stack_depth--;

     }

 }

 void fprint_stack_trace( FILE *f )

 {

     int i = call_stack_depth -1;

     if( i >= MAX_CALLSTACK )

 	i = MAX_CALLSTACK - 1;

     for( ; i >= 0; i-- ) {

 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 

 		 (call_stack_depth - i), call_stack[i].call_addr,

 		 call_stack[i].target_addr, call_stack[i].stack_pointer );

     }

 }

 #define TRACE_CALL( source, dest ) trace_call(source, dest)

 #define TRACE_RETURN( source, dest ) trace_return(source, dest)

 #else

 #define TRACE_CALL( dest, rts ) 

 #define TRACE_RETURN( source, dest )

 #endif

 #define RAISE( x, v ) do{			\

     if( sh4r.vbr == 0 ) { \

         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \

         dreamcast_stop(); return FALSE;	\

     } else { \

         sh4r.spc = sh4r.pc;	\

         sh4r.ssr = sh4_read_sr(); \

         sh4r.sgr = sh4r.r[15]; \

         MMIO_WRITE(MMU,EXPEVT,x); \

         sh4r.pc = sh4r.vbr + v; \

         sh4r.new_pc = sh4r.pc + 2; \

         sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \

 	if( sh4r.in_delay_slot ) { \

 	    sh4r.in_delay_slot = 0; \

 	    sh4r.spc -= 2; \

 	} \

     } \

     return TRUE; } while(0)

 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)

 #define MEM_READ_WORD( addr ) sh4_read_word(addr)

 #define MEM_READ_LONG( addr ) sh4_read_long(addr)

 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)

 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)

 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)

 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)

 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );

 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );

 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )

 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )

 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )

 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )

 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )

 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }

 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }

 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)

 static void sh4_switch_banks( )

 {

     uint32_t tmp[8];

     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );

     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );

     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );

 }

 void sh4_write_sr( uint32_t newval )

 {

     if( (newval ^ sh4r.sr) & SR_RB )

         sh4_switch_banks();

     sh4r.sr = newval;

     sh4r.t = (newval&SR_T) ? 1 : 0;

     sh4r.s = (newval&SR_S) ? 1 : 0;

     sh4r.m = (newval&SR_M) ? 1 : 0;

     sh4r.q = (newval&SR_Q) ? 1 : 0;

     intc_mask_changed();

 }

 static void sh4_write_float( uint32_t addr, int reg )

 {

     if( IS_FPU_DOUBLESIZE() ) {

 	if( reg & 1 ) {

 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );

 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );

 	} else {

 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 

 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );

 	}

     } else {

 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );

     }

 }

 static void sh4_read_float( uint32_t addr, int reg )

 {

     if( IS_FPU_DOUBLESIZE() ) {

 	if( reg & 1 ) {

 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);

 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);

 	} else {

 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);

 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);

 	}

     } else {

 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);

     }

 }

 uint32_t sh4_read_sr( void )

 {

     /* synchronize sh4r.sr with the various bitflags */

     sh4r.sr &= SR_MQSTMASK;

     if( sh4r.t ) sh4r.sr |= SR_T;

     if( sh4r.s ) sh4r.sr |= SR_S;

     if( sh4r.m ) sh4r.sr |= SR_M;

     if( sh4r.q ) sh4r.sr |= SR_Q;

     return sh4r.sr;

 }

 /**

  * Raise a general CPU exception for the specified exception code.

  * (NOT for TRAPA or TLB exceptions)

  */

 gboolean sh4_raise_exception( int code )

 {

     RAISE( code, EXV_EXCEPTION );

 }

 gboolean sh4_raise_trap( int trap )

 {

     MMIO_WRITE( MMU, TRA, trap<<2 );

     return sh4_raise_exception( EXC_TRAP );

 }

 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {

     if( sh4r.in_delay_slot ) {

 	return sh4_raise_exception(slot_code);

     } else {

 	return sh4_raise_exception(normal_code);

     }

 }

 gboolean sh4_raise_tlb_exception( int code )

 {

     RAISE( code, EXV_TLBMISS );

 }

 void sh4_accept_interrupt( void )

 {

     uint32_t code = intc_accept_interrupt();

     sh4r.ssr = sh4_read_sr();

     sh4r.spc = sh4r.pc;

     sh4r.sgr = sh4r.r[15];

     sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );

     MMIO_WRITE( MMU, INTEVT, code );

     sh4r.pc = sh4r.vbr + 0x600;

     sh4r.new_pc = sh4r.pc + 2;

     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );

 }

 gboolean sh4_execute_instruction( void )

 {

     uint32_t pc;

     unsigned short ir;

     uint32_t tmp;

     float ftmp;

     double dtmp;

 #define R0 sh4r.r[0]

     pc = sh4r.pc;

     if( pc > 0xFFFFFF00 ) {

 	/* SYSCALL Magic */

 	syscall_invoke( pc );

 	sh4r.in_delay_slot = 0;

 	pc = sh4r.pc = sh4r.pr;

 	sh4r.new_pc = sh4r.pc + 2;

     }

     CHECKRALIGN16(pc);

     /* Read instruction */

     uint32_t pageaddr = pc >> 12;

     if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {

 	ir = sh4_icache[(pc&0xFFF)>>1];

     } else {

 	sh4_icache = (uint16_t *)mem_get_page(pc);

 	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {

 	    /* If someone's actually been so daft as to try to execute out of an IO

 	     * region, fallback on the full-blown memory read

 	     */

 	    sh4_icache = NULL;

 	    ir = MEM_READ_WORD(pc);

 	} else {

 	    sh4_icache_addr = pageaddr;

 	    ir = sh4_icache[(pc&0xFFF)>>1];

 	}

     }

 %%

 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}

 AND #imm, R0 {: R0 &= imm; :}

 AND.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & MEM_READ_BYTE(R0 + sh4r.gbr) ); :}

 NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}

 OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}

 OR #imm, R0  {: R0 |= imm; :}

 OR.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | MEM_READ_BYTE(R0 + sh4r.gbr) ); :}

 TAS.B @Rn {:

     tmp = MEM_READ_BYTE( sh4r.r[Rn] );

     sh4r.t = ( tmp == 0 ? 1 : 0 );

     MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );

 :}

 TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}

 TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}

 TST.B #imm, @(R0, GBR) {: sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & imm ? 0 : 1 ); :}

 XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}

 XOR #imm, R0 {: R0 ^= imm; :}

 XOR.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ MEM_READ_BYTE(R0 + sh4r.gbr) ); :}

 XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}

 ROTL Rn {:

     sh4r.t = sh4r.r[Rn] >> 31;

     sh4r.r[Rn] <<= 1;

     sh4r.r[Rn] |= sh4r.t;

 :}

 ROTR Rn {:

     sh4r.t = sh4r.r[Rn] & 0x00000001;

     sh4r.r[Rn] >>= 1;

     sh4r.r[Rn] |= (sh4r.t << 31);

 :}

 ROTCL Rn {:

     tmp = sh4r.r[Rn] >> 31;

     sh4r.r[Rn] <<= 1;

     sh4r.r[Rn] |= sh4r.t;

     sh4r.t = tmp;

 :}

 ROTCR Rn {:

     tmp = sh4r.r[Rn] & 0x00000001;

     sh4r.r[Rn] >>= 1;

     sh4r.r[Rn] |= (sh4r.t << 31 );

     sh4r.t = tmp;

 :}

 SHAD Rm, Rn {:

     tmp = sh4r.r[Rm];

     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);

     else if( (tmp & 0x1F) == 0 )  

         sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;

     else 

 	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);

 :}

 SHLD Rm, Rn {:

     tmp = sh4r.r[Rm];

     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);

     else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;

     else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);

 :}

 SHAL Rn {:

     sh4r.t = sh4r.r[Rn] >> 31;

     sh4r.r[Rn] <<= 1;

 :}

 SHAR Rn {:

     sh4r.t = sh4r.r[Rn] & 0x00000001;

     sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;

 :}

 SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}

 SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}

 SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}

 SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}

 SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}

 SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}

 SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}

 SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}

 EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}

 EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}

 EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}

 EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}

 SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}

 SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}

 CLRT {: sh4r.t = 0; :}

 SETT {: sh4r.t = 1; :}

 CLRMAC {: sh4r.mac = 0; :}

 LDTLB {: /* TODO */ :}

 CLRS {: sh4r.s = 0; :}

 SETS {: sh4r.s = 1; :}

 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}

 NOP {: /* NOP */ :}

 PREF @Rn {:

      tmp = sh4r.r[Rn];

      if( (tmp & 0xFC000000) == 0xE0000000 ) {

 	 sh4_flush_store_queue(tmp);

      }

 :}

 OCBI @Rn {: :}

 OCBP @Rn {: :}

 OCBWB @Rn {: :}

 MOVCA.L R0, @Rn {:

     tmp = sh4r.r[Rn];

     CHECKWALIGN32(tmp);

     MEM_WRITE_LONG( tmp, R0 );

 :}

 MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}

 MOV.W Rm, @(R0, Rn) {: 

     CHECKWALIGN16( R0 + sh4r.r[Rn] );

     MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );

 :}

 MOV.L Rm, @(R0, Rn) {:

     CHECKWALIGN32( R0 + sh4r.r[Rn] );

     MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );

 :}

 MOV.B @(R0, Rm), Rn {: sh4r.r[Rn] = MEM_READ_BYTE( R0 + sh4r.r[Rm] ); :}

 MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );

                     sh4r.r[Rn] = MEM_READ_WORD( R0 + sh4r.r[Rm] );

 :}

 MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );

                     sh4r.r[Rn] = MEM_READ_LONG( R0 + sh4r.r[Rm] );

 :}

 MOV.L Rm, @(disp, Rn) {:

     tmp = sh4r.r[Rn] + disp;

     CHECKWALIGN32( tmp );

     MEM_WRITE_LONG( tmp, sh4r.r[Rm] );

 :}

 MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}

 MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}

 MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}

 MOV.B Rm, @-Rn {: sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}

 MOV.W Rm, @-Rn {: sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}

 MOV.L Rm, @-Rn {: sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}

 MOV.L @(disp, Rm), Rn {:

     tmp = sh4r.r[Rm] + disp;

     CHECKRALIGN32( tmp );

     sh4r.r[Rn] = MEM_READ_LONG( tmp );

 :}

 MOV.B @Rm, Rn {: sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); :}

 MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); :}

 MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); :}

 MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}

 MOV.B @Rm+, Rn {: sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); sh4r.r[Rm] ++; :}

 MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); sh4r.r[Rm] += 2; :}

 MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); sh4r.r[Rm] += 4; :}

 MOV.L @(disp, PC), Rn {:

     CHECKSLOTILLEGAL();

     tmp = (pc&0xFFFFFFFC) + disp + 4;

     sh4r.r[Rn] = MEM_READ_LONG( tmp );

 :}

 MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}

 MOV.W R0, @(disp, GBR) {:

     tmp = sh4r.gbr + disp;

     CHECKWALIGN16( tmp );

     MEM_WRITE_WORD( tmp, R0 );

 :}

 MOV.L R0, @(disp, GBR) {:

     tmp = sh4r.gbr + disp;

     CHECKWALIGN32( tmp );

     MEM_WRITE_LONG( tmp, R0 );

 :}

 MOV.B @(disp, GBR), R0 {: R0 = MEM_READ_BYTE( sh4r.gbr + disp ); :}

 MOV.W @(disp, GBR), R0 {: 

     tmp = sh4r.gbr + disp;

     CHECKRALIGN16( tmp );

     R0 = MEM_READ_WORD( tmp );

 :}

 MOV.L @(disp, GBR), R0 {:

     tmp = sh4r.gbr + disp;

     CHECKRALIGN32( tmp );

     R0 = MEM_READ_LONG( tmp );

 :}

 MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}

 MOV.W R0, @(disp, Rn) {: 

     tmp = sh4r.r[Rn] + disp;

     CHECKWALIGN16( tmp );

     MEM_WRITE_WORD( tmp, R0 );

 :}

 MOV.B @(disp, Rm), R0 {: R0 = MEM_READ_BYTE( sh4r.r[Rm] + disp ); :}

 MOV.W @(disp, Rm), R0 {: 

     tmp = sh4r.r[Rm] + disp;

     CHECKRALIGN16( tmp );

     R0 = MEM_READ_WORD( tmp );

 :}

 MOV.W @(disp, PC), Rn {:

     CHECKSLOTILLEGAL();

     tmp = pc + 4 + disp;

     sh4r.r[Rn] = MEM_READ_WORD( tmp );

 :}

 MOVA @(disp, PC), R0 {:

     CHECKSLOTILLEGAL();

     R0 = (pc&0xFFFFFFFC) + disp + 4;

 :}

 MOV #imm, Rn {:  sh4r.r[Rn] = imm; :}

 CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}

 CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}

 CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}

 CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}

 CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}

 CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}

 CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}

 CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}

 CMP/STR Rm, Rn {: 

     /* set T = 1 if any byte in RM & RN is the same */

     tmp = sh4r.r[Rm] ^ sh4r.r[Rn];

     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||

              (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;

 :}

 ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}

 ADD #imm, Rn {: sh4r.r[Rn] += imm; :}

 ADDC Rm, Rn {:

     tmp = sh4r.r[Rn];

     sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;

     sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );

 :}

 ADDV Rm, Rn {:

     tmp = sh4r.r[Rn] + sh4r.r[Rm];

     sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );

     sh4r.r[Rn] = tmp;

 :}

 DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}

 DIV0S Rm, Rn {: 

     sh4r.q = sh4r.r[Rn]>>31;

     sh4r.m = sh4r.r[Rm]>>31;

     sh4r.t = sh4r.q ^ sh4r.m;

 :}

 DIV1 Rm, Rn {:

     /* This is derived from the sh4 manual with some simplifications */

     uint32_t tmp0, tmp1, tmp2, dir;

     dir = sh4r.q ^ sh4r.m;

     sh4r.q = (sh4r.r[Rn] >> 31);

     tmp2 = sh4r.r[Rm];

     sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;

     tmp0 = sh4r.r[Rn];

     if( dir ) {

          sh4r.r[Rn] += tmp2;

          tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );

     } else {

          sh4r.r[Rn] -= tmp2;

          tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );

     }

     sh4r.q ^= sh4r.m ^ tmp1;

     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );

 :}

 DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}

 DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}

 DT Rn {:

     sh4r.r[Rn] --;

     sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );

 :}

 MAC.W @Rm+, @Rn+ {:

     CHECKRALIGN16( sh4r.r[Rn] );

     CHECKRALIGN16( sh4r.r[Rm] );

     int32_t stmp = SIGNEXT16(MEM_READ_WORD(sh4r.r[Rn]));

     sh4r.r[Rn] += 2;

     stmp = stmp * SIGNEXT16(MEM_READ_WORD(sh4r.r[Rm]));

     sh4r.r[Rm] += 2;

     if( sh4r.s ) {

 	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;

 	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {

 	    sh4r.mac = 0x000000017FFFFFFFLL;

 	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {

 	    sh4r.mac = 0x0000000180000000LL;

 	} else {

 	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |

 		((uint32_t)(sh4r.mac + stmp));

 	}

     } else {

 	sh4r.mac += SIGNEXT32(stmp);

     }

 :}

 MAC.L @Rm+, @Rn+ {:

     CHECKRALIGN32( sh4r.r[Rm] );

     CHECKRALIGN32( sh4r.r[Rn] );

     int64_t tmpl = SIGNEXT32(MEM_READ_LONG(sh4r.r[Rn]));

     sh4r.r[Rn] += 4;

     tmpl = tmpl * SIGNEXT32(MEM_READ_LONG(sh4r.r[Rm])) + sh4r.mac;

     sh4r.r[Rm] += 4;

     if( sh4r.s ) {

         /* 48-bit Saturation. Yuch */

         if( tmpl < (int64_t)0xFFFF800000000000LL )

             tmpl = 0xFFFF800000000000LL;

         else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )

             tmpl = 0x00007FFFFFFFFFFFLL;

     }

     sh4r.mac = tmpl;

 :}

 MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

                         (sh4r.r[Rm] * sh4r.r[Rn]); :}

 MULU.W Rm, Rn {:

     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

                (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));

 :}

 MULS.W Rm, Rn {:

     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

                (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));

 :}

 NEGC Rm, Rn {:

     tmp = 0 - sh4r.r[Rm];

     sh4r.r[Rn] = tmp - sh4r.t;

     sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );

 :}

 NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}

 SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}

 SUBC Rm, Rn {: 

     tmp = sh4r.r[Rn];

     sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;

     sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));

 :}

 BRAF Rn {:

      CHECKSLOTILLEGAL();

      CHECKDEST( pc + 4 + sh4r.r[Rn] );

      sh4r.in_delay_slot = 1;

      sh4r.pc = sh4r.new_pc;

      sh4r.new_pc = pc + 4 + sh4r.r[Rn];

      return TRUE;

 :}

 BSRF Rn {:

      CHECKSLOTILLEGAL();

      CHECKDEST( pc + 4 + sh4r.r[Rn] );

      sh4r.in_delay_slot = 1;

      sh4r.pr = sh4r.pc + 4;

      sh4r.pc = sh4r.new_pc;

      sh4r.new_pc = pc + 4 + sh4r.r[Rn];

      TRACE_CALL( pc, sh4r.new_pc );

      return TRUE;

 :}

 BT disp {:

     CHECKSLOTILLEGAL();

     if( sh4r.t ) {

         CHECKDEST( sh4r.pc + disp + 4 )

         sh4r.pc += disp + 4;

         sh4r.new_pc = sh4r.pc + 2;

         return TRUE;

     }

 :}

 BF disp {:

     CHECKSLOTILLEGAL();

     if( !sh4r.t ) {

         CHECKDEST( sh4r.pc + disp + 4 )

         sh4r.pc += disp + 4;

         sh4r.new_pc = sh4r.pc + 2;

         return TRUE;

     }

 :}

 BT/S disp {:

     CHECKSLOTILLEGAL();

     if( sh4r.t ) {

         CHECKDEST( sh4r.pc + disp + 4 )

         sh4r.in_delay_slot = 1;

         sh4r.pc = sh4r.new_pc;

         sh4r.new_pc = pc + disp + 4;

         sh4r.in_delay_slot = 1;

         return TRUE;

     }

 :}

 BF/S disp {:

     CHECKSLOTILLEGAL();

     if( !sh4r.t ) {

         CHECKDEST( sh4r.pc + disp + 4 )

         sh4r.in_delay_slot = 1;

         sh4r.pc = sh4r.new_pc;

         sh4r.new_pc = pc + disp + 4;

         return TRUE;

     }

 :}

 BRA disp {:

     CHECKSLOTILLEGAL();

     CHECKDEST( sh4r.pc + disp + 4 );

     sh4r.in_delay_slot = 1;

     sh4r.pc = sh4r.new_pc;

     sh4r.new_pc = pc + 4 + disp;

     return TRUE;

 :}

 BSR disp {:

     CHECKDEST( sh4r.pc + disp + 4 );

     CHECKSLOTILLEGAL();

     sh4r.in_delay_slot = 1;

     sh4r.pr = pc + 4;

     sh4r.pc = sh4r.new_pc;

     sh4r.new_pc = pc + 4 + disp;

     TRACE_CALL( pc, sh4r.new_pc );

     return TRUE;

 :}

 TRAPA #imm {:

     CHECKSLOTILLEGAL();

     MMIO_WRITE( MMU, TRA, imm<<2 );

     sh4r.pc += 2;

     sh4_raise_exception( EXC_TRAP );

 :}

 RTS {: 

     CHECKSLOTILLEGAL();

     CHECKDEST( sh4r.pr );

     sh4r.in_delay_slot = 1;

     sh4r.pc = sh4r.new_pc;

     sh4r.new_pc = sh4r.pr;

     TRACE_RETURN( pc, sh4r.new_pc );

     return TRUE;

 :}

 SLEEP {:

     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {

 	sh4r.sh4_state = SH4_STATE_STANDBY;

     } else {

 	sh4r.sh4_state = SH4_STATE_SLEEP;

     }

     return FALSE; /* Halt CPU */

 :}

 RTE {:

     CHECKPRIV();

     CHECKDEST( sh4r.spc );

     CHECKSLOTILLEGAL();

     sh4r.in_delay_slot = 1;

     sh4r.pc = sh4r.new_pc;

     sh4r.new_pc = sh4r.spc;

     sh4_write_sr( sh4r.ssr );

     return TRUE;

 :}

 JMP @Rn {:

     CHECKDEST( sh4r.r[Rn] );

     CHECKSLOTILLEGAL();

     sh4r.in_delay_slot = 1;

     sh4r.pc = sh4r.new_pc;

     sh4r.new_pc = sh4r.r[Rn];

     return TRUE;

 :}

 JSR @Rn {:

     CHECKDEST( sh4r.r[Rn] );

     CHECKSLOTILLEGAL();

     sh4r.in_delay_slot = 1;

     sh4r.pc = sh4r.new_pc;

     sh4r.new_pc = sh4r.r[Rn];

     sh4r.pr = pc + 4;

     TRACE_CALL( pc, sh4r.new_pc );

     return TRUE;

 :}

 STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}

 STS.L MACH, @-Rn {:

     sh4r.r[Rn] -= 4;

     CHECKWALIGN32( sh4r.r[Rn] );

     MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );

 :}

 STC.L SR, @-Rn {:

     CHECKPRIV();

     sh4r.r[Rn] -= 4;

     CHECKWALIGN32( sh4r.r[Rn] );

     MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );

 :}

 LDS.L @Rm+, MACH {:

     CHECKRALIGN32( sh4r.r[Rm] );

     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |

                (((uint64_t)MEM_READ_LONG(sh4r.r[Rm]))<<32);

     sh4r.r[Rm] += 4;

 :}

 LDC.L @Rm+, SR {:

     CHECKSLOTILLEGAL();

     CHECKPRIV();

     CHECKWALIGN32( sh4r.r[Rm] );

     sh4_write_sr( MEM_READ_LONG(sh4r.r[Rm]) );

     sh4r.r[Rm] +=4;

 :}

 LDS Rm, MACH {:

     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |

                (((uint64_t)sh4r.r[Rm])<<32);

 :}

 LDC Rm, SR {:

     CHECKSLOTILLEGAL();

     CHECKPRIV();

     sh4_write_sr( sh4r.r[Rm] );

 :}

 LDC Rm, SGR {:

     CHECKPRIV();

     sh4r.sgr = sh4r.r[Rm];

 :}

 LDC.L @Rm+, SGR {:

     CHECKPRIV();

     CHECKRALIGN32( sh4r.r[Rm] );

     sh4r.sgr = MEM_READ_LONG(sh4r.r[Rm]);

     sh4r.r[Rm] +=4;

 :}

 STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}

 STS.L MACL, @-Rn {:

     sh4r.r[Rn] -= 4;

     CHECKWALIGN32( sh4r.r[Rn] );

     MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );

 :}

 STC.L GBR, @-Rn {:

     sh4r.r[Rn] -= 4;

     CHECKWALIGN32( sh4r.r[Rn] );

     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );

 :}

 LDS.L @Rm+, MACL {:

     CHECKRALIGN32( sh4r.r[Rm] );

     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |

                (uint64_t)((uint32_t)MEM_READ_LONG(sh4r.r[Rm]));

     sh4r.r[Rm] += 4;

 :}

 LDC.L @Rm+, GBR {:

     CHECKRALIGN32( sh4r.r[Rm] );

     sh4r.gbr = MEM_READ_LONG(sh4r.r[Rm]);

     sh4r.r[Rm] +=4;

 :}

 LDS Rm, MACL {:

     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |

                (uint64_t)((uint32_t)(sh4r.r[Rm]));

 :}

 LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}

 STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}

 STS.L PR, @-Rn {:

     sh4r.r[Rn] -= 4;

     CHECKWALIGN32( sh4r.r[Rn] );

     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );

 :}

 STC.L VBR, @-Rn {:

     CHECKPRIV();

     sh4r.r[Rn] -= 4;

     CHECKWALIGN32( sh4r.r[Rn] );

     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );

 :}

 LDS.L @Rm+, PR {:

     CHECKRALIGN32( sh4r.r[Rm] );

     sh4r.pr = MEM_READ_LONG( sh4r.r[Rm] );

     sh4r.r[Rm] += 4;

 :}

 LDC.L @Rm+, VBR {:

     CHECKPRIV();

     CHECKRALIGN32( sh4r.r[Rm] );

     sh4r.vbr = MEM_READ_LONG(sh4r.r[Rm]);

     sh4r.r[Rm] +=4;

 :}

 LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}

 LDC Rm, VBR {:

     CHECKPRIV();

     sh4r.vbr = sh4r.r[Rm];

 :}

 STC SGR, Rn {:

     CHECKPRIV();

     sh4r.r[Rn] = sh4r.sgr;

 :}

 STC.L SGR, @-Rn {:

     CHECKPRIV();

     sh4r.r[Rn] -= 4;

     CHECKWALIGN32( sh4r.r[Rn] );

     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );

 :}

 STC.L SSR, @-Rn {:

     CHECKPRIV();

     sh4r.r[Rn] -= 4;

     CHECKWALIGN32( sh4r.r[Rn] );

     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );

 :}

 LDC.L @Rm+, SSR {:

     CHECKPRIV();

     CHECKRALIGN32( sh4r.r[Rm] );

     sh4r.ssr = MEM_READ_LONG(sh4r.r[Rm]);

     sh4r.r[Rm] +=4;

 :}

 LDC Rm, SSR {:

     CHECKPRIV();

     sh4r.ssr = sh4r.r[Rm];

 :}

 STC.L SPC, @-Rn {:

     CHECKPRIV();

     sh4r.r[Rn] -= 4;

     CHECKWALIGN32( sh4r.r[Rn] );

     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );

 :}

 LDC.L @Rm+, SPC {:

     CHECKPRIV();

     CHECKRALIGN32( sh4r.r[Rm] );

     sh4r.spc = MEM_READ_LONG(sh4r.r[Rm]);

     sh4r.r[Rm] +=4;

 :}

 LDC Rm, SPC {:

     CHECKPRIV();

     sh4r.spc = sh4r.r[Rm];

 :}

 STS FPUL, Rn {: sh4r.r[Rn] = sh4r.fpul; :}

 STS.L FPUL, @-Rn {:

     sh4r.r[Rn] -= 4;

     CHECKWALIGN32( sh4r.r[Rn] );

     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );

 :}

 LDS.L @Rm+, FPUL {:

     CHECKRALIGN32( sh4r.r[Rm] );

     sh4r.fpul = MEM_READ_LONG(sh4r.r[Rm]);

     sh4r.r[Rm] +=4;

 :}

 LDS Rm, FPUL {: sh4r.fpul = sh4r.r[Rm]; :}

 STS FPSCR, Rn {: sh4r.r[Rn] = sh4r.fpscr; :}

 STS.L FPSCR, @-Rn {:

     sh4r.r[Rn] -= 4;

     CHECKWALIGN32( sh4r.r[Rn] );

     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );

 :}

 LDS.L @Rm+, FPSCR {:

     CHECKRALIGN32( sh4r.r[Rm] );

     sh4r.fpscr = MEM_READ_LONG(sh4r.r[Rm]);

     sh4r.r[Rm] +=4;

     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];

 :}

 LDS Rm, FPSCR {: 

     sh4r.fpscr = sh4r.r[Rm]; 

     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];

 :}

 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}

 STC.L DBR, @-Rn {:

     CHECKPRIV();

     sh4r.r[Rn] -= 4;

     CHECKWALIGN32( sh4r.r[Rn] );

     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );

 :}

 LDC.L @Rm+, DBR {:

     CHECKPRIV();

     CHECKRALIGN32( sh4r.r[Rm] );

     sh4r.dbr = MEM_READ_LONG(sh4r.r[Rm]);

     sh4r.r[Rm] +=4;

 :}

 LDC Rm, DBR {:

     CHECKPRIV();

     sh4r.dbr = sh4r.r[Rm];

 :}

 STC.L Rm_BANK, @-Rn {:

     CHECKPRIV();

     sh4r.r[Rn] -= 4;

     CHECKWALIGN32( sh4r.r[Rn] );

     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );

 :}

 LDC.L @Rm+, Rn_BANK {:

     CHECKPRIV();

     CHECKRALIGN32( sh4r.r[Rm] );

     sh4r.r_bank[Rn_BANK] = MEM_READ_LONG( sh4r.r[Rm] );

     sh4r.r[Rm] += 4;

 :}

 LDC Rm, Rn_BANK {:

     CHECKPRIV();

     sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];

 :}

 STC SR, Rn {: 

     CHECKPRIV();

     sh4r.r[Rn] = sh4_read_sr();

 :}

 STC GBR, Rn {:

     CHECKPRIV();

     sh4r.r[Rn] = sh4r.gbr;

 :}

 STC VBR, Rn {:

     CHECKPRIV();

     sh4r.r[Rn] = sh4r.vbr;

 :}

 STC SSR, Rn {:

     CHECKPRIV();

     sh4r.r[Rn] = sh4r.ssr;

 :}

 STC SPC, Rn {:

     CHECKPRIV();

     sh4r.r[Rn] = sh4r.spc;

 :}

 STC Rm_BANK, Rn {:

     CHECKPRIV();

     sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];

 :}

 FADD FRm, FRn {:

     CHECKFPUEN();

     if( IS_FPU_DOUBLEPREC() ) {

 	DR(FRn) += DR(FRm);

     } else {

 	FR(FRn) += FR(FRm);

     }

 :}

 FSUB FRm, FRn {:

     CHECKFPUEN();

     if( IS_FPU_DOUBLEPREC() ) {

 	DR(FRn) -= DR(FRm);

     } else {

 	FR(FRn) -= FR(FRm);

     }

 :}

 FMUL FRm, FRn {:

     CHECKFPUEN();

     if( IS_FPU_DOUBLEPREC() ) {

 	DR(FRn) *= DR(FRm);

     } else {

 	FR(FRn) *= FR(FRm);

     }

 :}

 FDIV FRm, FRn {:

     CHECKFPUEN();

     if( IS_FPU_DOUBLEPREC() ) {

 	DR(FRn) /= DR(FRm);

     } else {

 	FR(FRn) /= FR(FRm);

     }

 :}

 FCMP/EQ FRm, FRn {:

     CHECKFPUEN();

     if( IS_FPU_DOUBLEPREC() ) {

 	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );

     } else {

 	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );

     }

 :}

 FCMP/GT FRm, FRn {:

     CHECKFPUEN();

     if( IS_FPU_DOUBLEPREC() ) {

 	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );

     } else {

 	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );

     }

 :}

 FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}

 FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}

 FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}

 FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}

 FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}

 FMOV FRm, @-Rn {: sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}

 FMOV FRm, FRn {: 

     if( IS_FPU_DOUBLESIZE() )

 	DR(FRn) = DR(FRm);

     else

 	FR(FRn) = FR(FRm);

 :}

 FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}

 FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}

 FLOAT FPUL, FRn {: 

     CHECKFPUEN();

     if( IS_FPU_DOUBLEPREC() ) {

 	if( FRn&1 ) { // No, really...

 	    dtmp = (double)FPULi;

 	    FR(FRn) = *(((float *)&dtmp)+1);

 	} else {

 	    DRF(FRn>>1) = (double)FPULi;

 	}

     } else {

 	FR(FRn) = (float)FPULi;

     }

 :}

 FTRC FRm, FPUL {:

     CHECKFPUEN();

     if( IS_FPU_DOUBLEPREC() ) {

 	if( FRm&1 ) {

 	    dtmp = 0;

 	    *(((float *)&dtmp)+1) = FR(FRm);

 	} else {

 	    dtmp = DRF(FRm>>1);

 	}

         if( dtmp >= MAX_INTF )

             FPULi = MAX_INT;

         else if( dtmp <= MIN_INTF )

             FPULi = MIN_INT;

         else 

             FPULi = (int32_t)dtmp;

     } else {

 	ftmp = FR(FRm);

 	if( ftmp >= MAX_INTF )

 	    FPULi = MAX_INT;

 	else if( ftmp <= MIN_INTF )

 	    FPULi = MIN_INT;

 	else

 	    FPULi = (int32_t)ftmp;

     }

 :}

 FNEG FRn {:

     CHECKFPUEN();

     if( IS_FPU_DOUBLEPREC() ) {

 	DR(FRn) = -DR(FRn);

     } else {

         FR(FRn) = -FR(FRn);

     }

 :}

 FABS FRn {:

     CHECKFPUEN();

     if( IS_FPU_DOUBLEPREC() ) {

 	DR(FRn) = fabs(DR(FRn));

     } else {

         FR(FRn) = fabsf(FR(FRn));

     }

 :}

 FSQRT FRn {:

     CHECKFPUEN();

     if( IS_FPU_DOUBLEPREC() ) {

 	DR(FRn) = sqrt(DR(FRn));

     } else {

         FR(FRn) = sqrtf(FR(FRn));

     }

 :}

 FLDI0 FRn {:

     CHECKFPUEN();

     if( IS_FPU_DOUBLEPREC() ) {

 	DR(FRn) = 0.0;

     } else {

         FR(FRn) = 0.0;

     }

 :}

 FLDI1 FRn {:

     CHECKFPUEN();

     if( IS_FPU_DOUBLEPREC() ) {

 	DR(FRn) = 1.0;

     } else {

         FR(FRn) = 1.0;

     }

 :}

 FMAC FR0, FRm, FRn {:

     CHECKFPUEN();

     if( IS_FPU_DOUBLEPREC() ) {

         DR(FRn) += DR(FRm)*DR(0);

     } else {

 	FR(FRn) += FR(FRm)*FR(0);

     }

 :}

 FRCHG {: 

     CHECKFPUEN(); 

     sh4r.fpscr ^= FPSCR_FR; 

     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];

 :}

 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}

 FCNVSD FPUL, FRn {:

     CHECKFPUEN();

     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {

 	DR(FRn) = (double)FPULf;

     }

 :}

 FCNVDS FRm, FPUL {:

     CHECKFPUEN();

     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {

 	FPULf = (float)DR(FRm);

     }

 :}

 FSRRA FRn {:

     CHECKFPUEN();

     if( !IS_FPU_DOUBLEPREC() ) {

 	FR(FRn) = 1.0/sqrtf(FR(FRn));

     }

 :}

 FIPR FVm, FVn {:

     CHECKFPUEN();

     if( !IS_FPU_DOUBLEPREC() ) {

         int tmp2 = FVn<<2;

         tmp = FVm<<2;

         FR(tmp2+3) = FR(tmp)*FR(tmp2) +

             FR(tmp+1)*FR(tmp2+1) +

             FR(tmp+2)*FR(tmp2+2) +

             FR(tmp+3)*FR(tmp2+3);

     }

 :}

 FSCA FPUL, FRn {:

     CHECKFPUEN();

     if( !IS_FPU_DOUBLEPREC() ) {

 	sh4_fsca( FPULi, &(DRF(FRn>>1)) );

 	/*

         float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;

         FR(FRn) = sinf(angle);

         FR((FRn)+1) = cosf(angle);

 	*/

     }

 :}

 FTRV XMTRX, FVn {:

     CHECKFPUEN();

     if( !IS_FPU_DOUBLEPREC() ) {

 	sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);

 	/*

         tmp = FVn<<2;

 	float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];

         float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };

         FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +

 	    xf[9]*fv[2] + xf[13]*fv[3];

         FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +

 	    xf[8]*fv[2] + xf[12]*fv[3];

         FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +

 	    xf[11]*fv[2] + xf[15]*fv[3];

         FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +

 	    xf[10]*fv[2] + xf[14]*fv[3];

 	*/

     }

 :}

 UNDEF {:

     UNDEF(ir);

 :}

 %%

     sh4r.pc = sh4r.new_pc;

     sh4r.new_pc += 2;

     sh4r.in_delay_slot = 0;

     return TRUE;

 }