lxdream 0.9.1| filename | src/pvr2/pvr2.c |
| changeset | 337:cdd757aa8e8c |
| prev | 335:fb890e1814c0 |
| next | 352:f0df7a6d4703 |
| author | nkeynes |
| date | Mon Feb 05 08:52:59 2007 +0000 (17 years ago) |
| permissions | -rw-r--r-- |
| last change | Fix compressed mipmap textures (byte count was wrong) Change internal gl format to the simple versions - let the implementation use whatever's most efficient |
| view | annotate | diff | log | raw |
1 /**
2 * $Id: pvr2.c,v 1.43 2007-01-28 11:36:00 nkeynes Exp $
3 *
4 * PVR2 (Video) Core module implementation and MMIO registers.
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18 #define MODULE pvr2_module
20 #include "dream.h"
21 #include "eventq.h"
22 #include "display.h"
23 #include "mem.h"
24 #include "asic.h"
25 #include "clock.h"
26 #include "pvr2/pvr2.h"
27 #include "sh4/sh4core.h"
28 #define MMIO_IMPL
29 #include "pvr2/pvr2mmio.h"
31 char *video_base;
33 #define HPOS_PER_FRAME 0
34 #define HPOS_PER_LINECOUNT 1
36 static void pvr2_init( void );
37 static void pvr2_reset( void );
38 static uint32_t pvr2_run_slice( uint32_t );
39 static void pvr2_save_state( FILE *f );
40 static int pvr2_load_state( FILE *f );
41 static void pvr2_update_raster_posn( uint32_t nanosecs );
42 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
43 uint32_t pvr2_get_sync_status();
45 void pvr2_display_frame( void );
47 int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 };
49 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,
50 pvr2_run_slice, NULL,
51 pvr2_save_state, pvr2_load_state };
54 display_driver_t display_driver = NULL;
56 struct video_timing {
57 int fields_per_second;
58 int total_lines;
59 int retrace_lines;
60 int line_time_ns;
61 };
63 struct video_timing pal_timing = { 50, 625, 65, 31945 };
64 struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
66 struct pvr2_state {
67 uint32_t frame_count;
68 uint32_t line_count;
69 uint32_t line_remainder;
70 uint32_t cycles_run; /* Cycles already executed prior to main time slice */
71 uint32_t irq_hpos_line;
72 uint32_t irq_hpos_line_count;
73 uint32_t irq_hpos_mode;
74 uint32_t irq_hpos_time_ns; /* Time within the line */
75 uint32_t irq_vpos1;
76 uint32_t irq_vpos2;
77 uint32_t odd_even_field; /* 1 = odd, 0 = even */
78 gboolean palette_changed; /* TRUE if palette has changed since last render */
79 gchar *save_next_render_filename;
80 /* timing */
81 uint32_t dot_clock;
82 uint32_t total_lines;
83 uint32_t line_size;
84 uint32_t line_time_ns;
85 uint32_t vsync_lines;
86 uint32_t hsync_width_ns;
87 uint32_t front_porch_ns;
88 uint32_t back_porch_ns;
89 uint32_t retrace_start_line;
90 uint32_t retrace_end_line;
91 gboolean interlaced;
92 struct video_timing timing;
93 } pvr2_state;
95 struct video_buffer video_buffer[2];
96 int video_buffer_idx = 0;
98 /**
99 * Event handler for the hpos callback
100 */
101 static void pvr2_hpos_callback( int eventid ) {
102 asic_event( eventid );
103 pvr2_update_raster_posn(sh4r.slice_cycle);
104 if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
105 pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
106 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
107 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
108 }
109 }
110 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1,
111 pvr2_state.irq_hpos_time_ns );
112 }
114 /**
115 * Event handler for the scanline callbacks. Fires the corresponding
116 * ASIC event, and resets the timer for the next field.
117 */
118 static void pvr2_scanline_callback( int eventid ) {
119 asic_event( eventid );
120 pvr2_update_raster_posn(sh4r.slice_cycle);
121 if( eventid == EVENT_SCANLINE1 ) {
122 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
123 } else {
124 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
125 }
126 }
128 static void pvr2_init( void )
129 {
130 register_io_region( &mmio_region_PVR2 );
131 register_io_region( &mmio_region_PVR2PAL );
132 register_io_region( &mmio_region_PVR2TA );
133 register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
134 register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
135 register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
136 video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
137 texcache_init();
138 pvr2_reset();
139 pvr2_ta_reset();
140 pvr2_state.save_next_render_filename = NULL;
141 }
143 static void pvr2_reset( void )
144 {
145 pvr2_state.line_count = 0;
146 pvr2_state.line_remainder = 0;
147 pvr2_state.cycles_run = 0;
148 pvr2_state.irq_vpos1 = 0;
149 pvr2_state.irq_vpos2 = 0;
150 pvr2_state.timing = ntsc_timing;
151 pvr2_state.dot_clock = PVR2_DOT_CLOCK;
152 pvr2_state.back_porch_ns = 4000;
153 pvr2_state.palette_changed = FALSE;
154 mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
155 mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
156 mmio_region_PVR2_write( YUV_ADDR, 0 );
157 mmio_region_PVR2_write( YUV_CFG, 0 );
158 video_buffer_idx = 0;
160 pvr2_ta_init();
161 pvr2_render_init();
162 texcache_flush();
163 }
165 static void pvr2_save_state( FILE *f )
166 {
167 fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
168 pvr2_ta_save_state( f );
169 pvr2_yuv_save_state( f );
170 }
172 static int pvr2_load_state( FILE *f )
173 {
174 if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
175 return 1;
176 if( pvr2_ta_load_state(f) ) {
177 return 1;
178 }
179 return pvr2_yuv_load_state(f);
180 }
182 /**
183 * Update the current raster position to the given number of nanoseconds,
184 * relative to the last time slice. (ie the raster will be adjusted forward
185 * by nanosecs - nanosecs_already_run_this_timeslice)
186 */
187 static void pvr2_update_raster_posn( uint32_t nanosecs )
188 {
189 uint32_t old_line_count = pvr2_state.line_count;
190 if( pvr2_state.line_time_ns == 0 ) {
191 return; /* do nothing */
192 }
193 pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
194 pvr2_state.cycles_run = nanosecs;
195 while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
196 pvr2_state.line_count ++;
197 pvr2_state.line_remainder -= pvr2_state.line_time_ns;
198 }
200 if( pvr2_state.line_count >= pvr2_state.total_lines ) {
201 pvr2_state.line_count -= pvr2_state.total_lines;
202 if( pvr2_state.interlaced ) {
203 pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
204 }
205 }
206 if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
207 (old_line_count < pvr2_state.retrace_end_line ||
208 old_line_count > pvr2_state.line_count) ) {
209 pvr2_state.frame_count++;
210 pvr2_display_frame();
211 }
212 }
214 static uint32_t pvr2_run_slice( uint32_t nanosecs )
215 {
216 pvr2_update_raster_posn( nanosecs );
217 pvr2_state.cycles_run = 0;
218 return nanosecs;
219 }
221 int pvr2_get_frame_count()
222 {
223 return pvr2_state.frame_count;
224 }
226 gboolean pvr2_save_next_scene( const gchar *filename )
227 {
228 if( pvr2_state.save_next_render_filename != NULL ) {
229 g_free( pvr2_state.save_next_render_filename );
230 }
231 pvr2_state.save_next_render_filename = g_strdup(filename);
232 return TRUE;
233 }
237 /**
238 * Display the next frame, copying the current contents of video ram to
239 * the window. If the video configuration has changed, first recompute the
240 * new frame size/depth.
241 */
242 void pvr2_display_frame( void )
243 {
244 uint32_t display_addr;
245 int dispsize = MMIO_READ( PVR2, DISP_SIZE );
246 int dispmode = MMIO_READ( PVR2, DISP_MODE );
247 int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
248 int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
249 int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
250 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
251 gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
252 gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
253 video_buffer_t buffer = &video_buffer[video_buffer_idx];
254 video_buffer_idx = !video_buffer_idx;
255 video_buffer_t last = &video_buffer[video_buffer_idx];
256 buffer->rowstride = (vid_ppl + vid_stride) << 2;
257 buffer->data = video_base + MMIO_READ( PVR2, DISP_ADDR1 );
258 buffer->line_double = (dispmode & DISPMODE_LINEDOUBLE) ? TRUE : FALSE;
259 buffer->vres = vid_lpf;
260 if( interlaced ) {
261 if( vid_ppl == vid_stride ) { /* Magic deinterlace */
262 buffer->vres <<= 1;
263 buffer->rowstride = vid_ppl << 2;
264 display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
265 } else {
266 /* Just display the field as is, folks. This is slightly tricky -
267 * we pick the field based on which frame is about to come through,
268 * which may not be the same as the odd_even_field.
269 */
270 gboolean oddfield = pvr2_state.odd_even_field;
271 if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
272 oddfield = !oddfield;
273 }
274 if( oddfield ) {
275 display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
276 } else {
277 display_addr = MMIO_READ( PVR2, DISP_ADDR2 );
278 }
279 }
280 } else {
281 display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
282 }
283 switch( (dispmode & DISPMODE_COLFMT) >> 2 ) {
284 case 0:
285 buffer->colour_format = COLFMT_ARGB1555;
286 buffer->hres = vid_ppl << 1;
287 break;
288 case 1:
289 buffer->colour_format = COLFMT_RGB565;
290 buffer->hres = vid_ppl << 1;
291 break;
292 case 2:
293 buffer->colour_format = COLFMT_RGB888;
294 buffer->hres = (vid_ppl << 2) / 3;
295 break;
296 case 3:
297 buffer->colour_format = COLFMT_ARGB8888;
298 buffer->hres = vid_ppl;
299 break;
300 }
302 if( buffer->hres <=8 )
303 buffer->hres = 640;
304 if( buffer->vres <=8 )
305 buffer->vres = 480;
306 if( display_driver != NULL ) {
307 if( buffer->hres != last->hres ||
308 buffer->vres != last->vres ||
309 buffer->colour_format != last->colour_format) {
310 display_driver->set_display_format( buffer->hres, buffer->vres,
311 buffer->colour_format );
312 }
313 if( !bEnabled ) {
314 display_driver->display_blank_frame( 0 );
315 } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { /* Blanked */
316 uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
317 display_driver->display_blank_frame( colour );
318 } else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
319 display_driver->display_frame( buffer );
320 }
321 }
322 }
324 /**
325 * This has to handle every single register individually as they all get masked
326 * off differently (and its easier to do it at write time)
327 */
328 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
329 {
330 if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
331 MMIO_WRITE( PVR2, reg, val );
332 return;
333 }
335 switch(reg) {
336 case PVRID:
337 case PVRVER:
338 case GUNPOS: /* Read only registers */
339 break;
340 case PVRRESET:
341 val &= 0x00000007; /* Do stuff? */
342 MMIO_WRITE( PVR2, reg, val );
343 break;
344 case RENDER_START: /* Don't really care what value */
345 if( pvr2_state.save_next_render_filename != NULL ) {
346 if( pvr2_render_save_scene(pvr2_state.save_next_render_filename) == 0 ) {
347 INFO( "Saved scene to %s", pvr2_state.save_next_render_filename);
348 }
349 g_free( pvr2_state.save_next_render_filename );
350 pvr2_state.save_next_render_filename = NULL;
351 }
352 pvr2_render_scene();
353 break;
354 case RENDER_POLYBASE:
355 MMIO_WRITE( PVR2, reg, val&0x00F00000 );
356 break;
357 case RENDER_TSPCFG:
358 MMIO_WRITE( PVR2, reg, val&0x00010101 );
359 break;
360 case DISP_BORDER:
361 MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
362 break;
363 case DISP_MODE:
364 MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
365 break;
366 case RENDER_MODE:
367 MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
368 break;
369 case RENDER_SIZE:
370 MMIO_WRITE( PVR2, reg, val&0x000001FF );
371 break;
372 case DISP_ADDR1:
373 val &= 0x00FFFFFC;
374 MMIO_WRITE( PVR2, reg, val );
375 /*
376 pvr2_update_raster_posn(sh4r.slice_cycle);
377 fprintf( stderr, "Set Field 1 addr: %08X\n", val );
378 if( (pvr2_state.line_count >= pvr2_state.retrace_start_line && !pvr2_state.odd_even_field) ||
379 (pvr2_state.line_count < pvr2_state.retrace_end_line && pvr2_state.odd_even_field) ) {
380 pvr2_display_frame();
381 }
382 */
383 break;
384 case DISP_ADDR2:
385 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
386 pvr2_update_raster_posn(sh4r.slice_cycle);
387 /*
388 if( (pvr2_state.line_count >= pvr2_state.retrace_start_line && pvr2_state.odd_even_field) ||
389 (pvr2_state.line_count < pvr2_state.retrace_end_line && !pvr2_state.odd_even_field) ) {
390 pvr2_display_frame();
391 }*/
392 break;
393 case DISP_SIZE:
394 MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
395 break;
396 case RENDER_ADDR1:
397 case RENDER_ADDR2:
398 MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
399 break;
400 case RENDER_HCLIP:
401 MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
402 break;
403 case RENDER_VCLIP:
404 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
405 break;
406 case DISP_HPOSIRQ:
407 MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
408 pvr2_state.irq_hpos_line = val & 0x03FF;
409 pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
410 pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
411 switch( pvr2_state.irq_hpos_mode ) {
412 case 3: /* Reserved - treat as 0 */
413 case 0: /* Once per frame at specified line */
414 pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
415 break;
416 case 2: /* Once per line - as per-line-count */
417 pvr2_state.irq_hpos_line = 1;
418 pvr2_state.irq_hpos_mode = 1;
419 case 1: /* Once per N lines */
420 pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
421 pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) +
422 pvr2_state.irq_hpos_line_count;
423 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
424 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
425 }
426 pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
427 }
428 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
429 pvr2_state.irq_hpos_time_ns );
430 break;
431 case DISP_VPOSIRQ:
432 val = val & 0x03FF03FF;
433 pvr2_state.irq_vpos1 = (val >> 16);
434 pvr2_state.irq_vpos2 = val & 0x03FF;
435 pvr2_update_raster_posn(sh4r.slice_cycle);
436 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
437 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
438 MMIO_WRITE( PVR2, reg, val );
439 break;
440 case RENDER_NEARCLIP:
441 MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
442 break;
443 case RENDER_SHADOW:
444 MMIO_WRITE( PVR2, reg, val&0x000001FF );
445 break;
446 case RENDER_OBJCFG:
447 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
448 break;
449 case RENDER_TSPCLIP:
450 MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
451 break;
452 case RENDER_FARCLIP:
453 MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
454 break;
455 case RENDER_BGPLANE:
456 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
457 break;
458 case RENDER_ISPCFG:
459 MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
460 break;
461 case VRAM_CFG1:
462 MMIO_WRITE( PVR2, reg, val&0x000000FF );
463 break;
464 case VRAM_CFG2:
465 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
466 break;
467 case VRAM_CFG3:
468 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
469 break;
470 case RENDER_FOGTBLCOL:
471 case RENDER_FOGVRTCOL:
472 MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
473 break;
474 case RENDER_FOGCOEFF:
475 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
476 break;
477 case RENDER_CLAMPHI:
478 case RENDER_CLAMPLO:
479 MMIO_WRITE( PVR2, reg, val );
480 break;
481 case RENDER_TEXSIZE:
482 MMIO_WRITE( PVR2, reg, val&0x00031F1F );
483 break;
484 case RENDER_PALETTE:
485 MMIO_WRITE( PVR2, reg, val&0x00000003 );
486 break;
488 /********** CRTC registers *************/
489 case DISP_HBORDER:
490 case DISP_VBORDER:
491 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
492 break;
493 case DISP_TOTAL:
494 val = val & 0x03FF03FF;
495 MMIO_WRITE( PVR2, reg, val );
496 pvr2_update_raster_posn(sh4r.slice_cycle);
497 pvr2_state.total_lines = (val >> 16) + 1;
498 pvr2_state.line_size = (val & 0x03FF) + 1;
499 pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
500 pvr2_state.retrace_end_line = 0x2A;
501 pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
502 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
503 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
504 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
505 pvr2_state.irq_hpos_time_ns );
506 break;
507 case DISP_SYNCCFG:
508 MMIO_WRITE( PVR2, reg, val&0x000003FF );
509 pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
510 break;
511 case DISP_SYNCTIME:
512 pvr2_state.vsync_lines = (val >> 8) & 0x0F;
513 pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
514 MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
515 break;
516 case DISP_CFG2:
517 MMIO_WRITE( PVR2, reg, val&0x003F01FF );
518 break;
519 case DISP_HPOS:
520 val = val & 0x03FF;
521 pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
522 MMIO_WRITE( PVR2, reg, val );
523 break;
524 case DISP_VPOS:
525 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
526 break;
528 /*********** Tile accelerator registers ***********/
529 case TA_POLYPOS:
530 case TA_LISTPOS:
531 /* Readonly registers */
532 break;
533 case TA_TILEBASE:
534 case TA_LISTEND:
535 case TA_LISTBASE:
536 MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
537 break;
538 case RENDER_TILEBASE:
539 case TA_POLYBASE:
540 case TA_POLYEND:
541 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
542 break;
543 case TA_TILESIZE:
544 MMIO_WRITE( PVR2, reg, val&0x000F003F );
545 break;
546 case TA_TILECFG:
547 MMIO_WRITE( PVR2, reg, val&0x00133333 );
548 break;
549 case TA_INIT:
550 if( val & 0x80000000 )
551 pvr2_ta_init();
552 break;
553 case TA_REINIT:
554 break;
555 /**************** Scaler registers? ****************/
556 case RENDER_SCALER:
557 MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
558 break;
560 case YUV_ADDR:
561 val = val & 0x00FFFFF8;
562 MMIO_WRITE( PVR2, reg, val );
563 pvr2_yuv_init( val );
564 break;
565 case YUV_CFG:
566 MMIO_WRITE( PVR2, reg, val&0x01013F3F );
567 pvr2_yuv_set_config(val);
568 break;
570 /**************** Unknowns ***************/
571 case PVRUNK1:
572 MMIO_WRITE( PVR2, reg, val&0x000007FF );
573 break;
574 case PVRUNK2:
575 MMIO_WRITE( PVR2, reg, val&0x00000007 );
576 break;
577 case PVRUNK3:
578 MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
579 break;
580 case PVRUNK5:
581 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
582 break;
583 case PVRUNK6:
584 MMIO_WRITE( PVR2, reg, val&0x000000FF );
585 break;
586 case PVRUNK7:
587 MMIO_WRITE( PVR2, reg, val&0x00000001 );
588 break;
589 }
590 }
592 /**
593 * Calculate the current read value of the syncstat register, using
594 * the current SH4 clock time as an offset from the last timeslice.
595 * The register reads (LSB to MSB) as:
596 * 0..9 Current scan line
597 * 10 Odd/even field (1 = odd, 0 = even)
598 * 11 Display active (including border and overscan)
599 * 12 Horizontal sync off
600 * 13 Vertical sync off
601 * Note this method is probably incorrect for anything other than straight
602 * interlaced PAL/NTSC, and needs further testing.
603 */
604 uint32_t pvr2_get_sync_status()
605 {
606 pvr2_update_raster_posn(sh4r.slice_cycle);
607 uint32_t result = pvr2_state.line_count;
609 if( pvr2_state.odd_even_field ) {
610 result |= 0x0400;
611 }
612 if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
613 if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
614 result |= 0x1000; /* !HSYNC */
615 }
616 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
617 if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
618 result |= 0x2800; /* Display active */
619 } else {
620 result |= 0x2000; /* Front porch */
621 }
622 }
623 } else {
624 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
625 if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
626 result |= 0x3800; /* Display active */
627 } else {
628 result |= 0x3000;
629 }
630 } else {
631 result |= 0x1000; /* Back porch */
632 }
633 }
634 return result;
635 }
637 /**
638 * Schedule a "scanline" event. This actually goes off at
639 * 2 * line in even fields and 2 * line + 1 in odd fields.
640 * Otherwise this behaves as per pvr2_schedule_line_event().
641 * The raster position should be updated before calling this
642 * method.
643 * @param eventid Event to fire at the specified time
644 * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
645 * displays).
646 * @param hpos_ns Nanoseconds into the line at which to fire.
647 */
648 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
649 {
650 uint32_t field = pvr2_state.odd_even_field;
651 if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
652 field = !field;
653 }
654 if( hpos_ns > pvr2_state.line_time_ns ) {
655 hpos_ns = pvr2_state.line_time_ns;
656 }
658 line <<= 1;
659 if( field ) {
660 line += 1;
661 }
663 if( line < pvr2_state.total_lines ) {
664 uint32_t lines;
665 uint32_t time;
666 if( line <= pvr2_state.line_count ) {
667 lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
668 } else {
669 lines = (line - pvr2_state.line_count);
670 }
671 if( lines <= minimum_lines ) {
672 lines += pvr2_state.total_lines;
673 }
674 time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
675 event_schedule( eventid, time );
676 } else {
677 event_cancel( eventid );
678 }
679 }
681 MMIO_REGION_READ_FN( PVR2, reg )
682 {
683 switch( reg ) {
684 case DISP_SYNCSTAT:
685 return pvr2_get_sync_status();
686 default:
687 return MMIO_READ( PVR2, reg );
688 }
689 }
691 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
692 {
693 MMIO_WRITE( PVR2PAL, reg, val );
694 pvr2_state.palette_changed = TRUE;
695 }
697 void pvr2_check_palette_changed()
698 {
699 if( pvr2_state.palette_changed ) {
700 texcache_invalidate_palette();
701 pvr2_state.palette_changed = FALSE;
702 }
703 }
705 MMIO_REGION_READ_DEFFN( PVR2PAL );
707 void pvr2_set_base_address( uint32_t base )
708 {
709 mmio_region_PVR2_write( DISP_ADDR1, base );
710 }
715 int32_t mmio_region_PVR2TA_read( uint32_t reg )
716 {
717 return 0xFFFFFFFF;
718 }
720 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
721 {
722 pvr2_ta_write( (char *)&val, sizeof(uint32_t) );
723 }
.