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lxdream.org :: lxdream/src/sh4/sh4.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4.c
changeset 559:06714bc64271
prev526:ba3da45b5754
next561:533f6b478071
author nkeynes
date Tue Jan 01 04:58:57 2008 +0000 (13 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Commit first pass at full TLB support - still needs a lot more work
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     1 /**
     2  * $Id: sh4.c,v 1.7 2007-11-08 11:54:16 nkeynes Exp $
     3  * 
     4  * SH4 parent module for all CPU modes and SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "dreamcast.h"
    24 #include "sh4/sh4core.h"
    25 #include "sh4/sh4mmio.h"
    26 #include "sh4/intc.h"
    27 #include "sh4/xltcache.h"
    28 #include "sh4/sh4stat.h"
    29 #include "mem.h"
    30 #include "clock.h"
    31 #include "syscall.h"
    33 void sh4_init( void );
    34 void sh4_xlat_init( void );
    35 void sh4_reset( void );
    36 void sh4_start( void );
    37 void sh4_stop( void );
    38 void sh4_save_state( FILE *f );
    39 int sh4_load_state( FILE *f );
    41 uint32_t sh4_run_slice( uint32_t );
    42 uint32_t sh4_xlat_run_slice( uint32_t );
    44 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    45 				       NULL, sh4_run_slice, sh4_stop,
    46 				       sh4_save_state, sh4_load_state };
    48 struct sh4_registers sh4r;
    49 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    50 int sh4_breakpoint_count = 0;
    51 extern sh4ptr_t sh4_main_ram;
    52 static gboolean sh4_use_translator = FALSE;
    54 void sh4_set_use_xlat( gboolean use )
    55 {
    56 // No-op if the translator was not built
    57 #ifdef SH4_TRANSLATOR
    58     if( use ) {
    59 	xlat_cache_init();
    60 	sh4_x86_init();
    61 	sh4_module.run_time_slice = sh4_xlat_run_slice;
    62     } else {
    63 	sh4_module.run_time_slice = sh4_run_slice;
    64     }
    65     sh4_use_translator = use;
    66 #endif
    67 }
    69 void sh4_init(void)
    70 {
    71     register_io_regions( mmio_list_sh4mmio );
    72     sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
    73     MMU_init();
    74     sh4_reset();
    75 }
    77 void sh4_reset(void)
    78 {
    79     if(	sh4_use_translator ) {
    80 	xlat_flush_cache();
    81     }
    83     /* zero everything out, for the sake of having a consistent state. */
    84     memset( &sh4r, 0, sizeof(sh4r) );
    86     /* Resume running if we were halted */
    87     sh4r.sh4_state = SH4_STATE_RUNNING;
    89     sh4r.pc    = 0xA0000000;
    90     sh4r.new_pc= 0xA0000002;
    91     sh4r.vbr   = 0x00000000;
    92     sh4r.fpscr = 0x00040001;
    93     sh4r.sr    = 0x700000F0;
    94     sh4r.fr_bank = &sh4r.fr[0][0];
    96     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
    97     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
    99     /* Peripheral modules */
   100     CPG_reset();
   101     INTC_reset();
   102     MMU_reset();
   103     TMU_reset();
   104     SCIF_reset();
   105     sh4_stats_reset();
   106 }
   108 void sh4_stop(void)
   109 {
   110     if(	sh4_use_translator ) {
   111 	/* If we were running with the translator, update new_pc and in_delay_slot */
   112 	sh4r.new_pc = sh4r.pc+2;
   113 	sh4r.in_delay_slot = FALSE;
   114     }
   116 }
   118 void sh4_save_state( FILE *f )
   119 {
   120     if(	sh4_use_translator ) {
   121 	/* If we were running with the translator, update new_pc and in_delay_slot */
   122 	sh4r.new_pc = sh4r.pc+2;
   123 	sh4r.in_delay_slot = FALSE;
   124     }
   126     fwrite( &sh4r, sizeof(sh4r), 1, f );
   127     MMU_save_state( f );
   128     INTC_save_state( f );
   129     TMU_save_state( f );
   130     SCIF_save_state( f );
   131 }
   133 int sh4_load_state( FILE * f )
   134 {
   135     if(	sh4_use_translator ) {
   136 	xlat_flush_cache();
   137     }
   138     fread( &sh4r, sizeof(sh4r), 1, f );
   139     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0]; // Fixup internal FR pointer
   140     MMU_load_state( f );
   141     INTC_load_state( f );
   142     TMU_load_state( f );
   143     return SCIF_load_state( f );
   144 }
   147 void sh4_set_breakpoint( uint32_t pc, int type )
   148 {
   149     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   150     sh4_breakpoints[sh4_breakpoint_count].type = type;
   151     sh4_breakpoint_count++;
   152 }
   154 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
   155 {
   156     int i;
   158     for( i=0; i<sh4_breakpoint_count; i++ ) {
   159 	if( sh4_breakpoints[i].address == pc && 
   160 	    sh4_breakpoints[i].type == type ) {
   161 	    while( ++i < sh4_breakpoint_count ) {
   162 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   163 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   164 	    }
   165 	    sh4_breakpoint_count--;
   166 	    return TRUE;
   167 	}
   168     }
   169     return FALSE;
   170 }
   172 int sh4_get_breakpoint( uint32_t pc )
   173 {
   174     int i;
   175     for( i=0; i<sh4_breakpoint_count; i++ ) {
   176 	if( sh4_breakpoints[i].address == pc )
   177 	    return sh4_breakpoints[i].type;
   178     }
   179     return 0;
   180 }
   182 void sh4_set_pc( int pc )
   183 {
   184     sh4r.pc = pc;
   185     sh4r.new_pc = pc+2;
   186 }
   189 /******************************* Support methods ***************************/
   191 static void sh4_switch_banks( )
   192 {
   193     uint32_t tmp[8];
   195     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   196     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   197     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   198 }
   200 void sh4_write_sr( uint32_t newval )
   201 {
   202     if( (newval ^ sh4r.sr) & SR_RB )
   203         sh4_switch_banks();
   204     sh4r.sr = newval;
   205     sh4r.t = (newval&SR_T) ? 1 : 0;
   206     sh4r.s = (newval&SR_S) ? 1 : 0;
   207     sh4r.m = (newval&SR_M) ? 1 : 0;
   208     sh4r.q = (newval&SR_Q) ? 1 : 0;
   209     intc_mask_changed();
   210 }
   212 uint32_t sh4_read_sr( void )
   213 {
   214     /* synchronize sh4r.sr with the various bitflags */
   215     sh4r.sr &= SR_MQSTMASK;
   216     if( sh4r.t ) sh4r.sr |= SR_T;
   217     if( sh4r.s ) sh4r.sr |= SR_S;
   218     if( sh4r.m ) sh4r.sr |= SR_M;
   219     if( sh4r.q ) sh4r.sr |= SR_Q;
   220     return sh4r.sr;
   221 }
   225 #define RAISE( x, v ) do{			\
   226     if( sh4r.vbr == 0 ) { \
   227         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   228         dreamcast_stop(); return FALSE;	\
   229     } else { \
   230         sh4r.spc = sh4r.pc;	\
   231         sh4r.ssr = sh4_read_sr(); \
   232         sh4r.sgr = sh4r.r[15]; \
   233         MMIO_WRITE(MMU,EXPEVT,x); \
   234         sh4r.pc = sh4r.vbr + v; \
   235         sh4r.new_pc = sh4r.pc + 2; \
   236         sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   237 	if( sh4r.in_delay_slot ) { \
   238 	    sh4r.in_delay_slot = 0; \
   239 	    sh4r.spc -= 2; \
   240 	} \
   241     } \
   242     return TRUE; } while(0)
   244 /**
   245  * Raise a general CPU exception for the specified exception code.
   246  * (NOT for TRAPA or TLB exceptions)
   247  */
   248 gboolean sh4_raise_exception( int code )
   249 {
   250     RAISE( code, EXV_EXCEPTION );
   251 }
   253 /**
   254  * Raise a CPU reset exception with the specified exception code.
   255  */
   256 gboolean sh4_raise_reset( int code )
   257 {
   258     // FIXME: reset modules as per "manual reset"
   259     sh4_reset();
   260     MMIO_WRITE(MMU,EXPEVT,code);
   261     sh4r.vbr = 0;
   262     sh4r.pc = 0xA0000000;
   263     sh4r.new_pc = sh4r.pc + 2;
   264     sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
   265 		  &(~SR_FD) );
   266 }
   268 gboolean sh4_raise_trap( int trap )
   269 {
   270     MMIO_WRITE( MMU, TRA, trap<<2 );
   271     return sh4_raise_exception( EXC_TRAP );
   272 }
   274 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
   275     if( sh4r.in_delay_slot ) {
   276 	return sh4_raise_exception(slot_code);
   277     } else {
   278 	return sh4_raise_exception(normal_code);
   279     }
   280 }
   282 gboolean sh4_raise_tlb_exception( int code )
   283 {
   284     RAISE( code, EXV_TLBMISS );
   285 }
   287 void sh4_accept_interrupt( void )
   288 {
   289     uint32_t code = intc_accept_interrupt();
   290     sh4r.ssr = sh4_read_sr();
   291     sh4r.spc = sh4r.pc;
   292     sh4r.sgr = sh4r.r[15];
   293     sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   294     MMIO_WRITE( MMU, INTEVT, code );
   295     sh4r.pc = sh4r.vbr + 0x600;
   296     sh4r.new_pc = sh4r.pc + 2;
   297     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   298 }
   300 void signsat48( void )
   301 {
   302     if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
   303 	sh4r.mac = 0xFFFF800000000000LL;
   304     else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
   305 	sh4r.mac = 0x00007FFFFFFFFFFFLL;
   306 }
   308 void sh4_fsca( uint32_t anglei, float *fr )
   309 {
   310     float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
   311     *fr++ = cosf(angle);
   312     *fr = sinf(angle);
   313 }
   315 void sh4_sleep(void)
   316 {
   317     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   318 	sh4r.sh4_state = SH4_STATE_STANDBY;
   319     } else {
   320 	sh4r.sh4_state = SH4_STATE_SLEEP;
   321     }
   322 }
   324 /**
   325  * Compute the matrix tranform of fv given the matrix xf.
   326  * Both fv and xf are word-swapped as per the sh4r.fr banks
   327  */
   328 void sh4_ftrv( float *target, float *xf )
   329 {
   330     float fv[4] = { target[1], target[0], target[3], target[2] };
   331     target[1] = xf[1] * fv[0] + xf[5]*fv[1] +
   332 	xf[9]*fv[2] + xf[13]*fv[3];
   333     target[0] = xf[0] * fv[0] + xf[4]*fv[1] +
   334 	xf[8]*fv[2] + xf[12]*fv[3];
   335     target[3] = xf[3] * fv[0] + xf[7]*fv[1] +
   336 	xf[11]*fv[2] + xf[15]*fv[3];
   337     target[2] = xf[2] * fv[0] + xf[6]*fv[1] +
   338 	xf[10]*fv[2] + xf[14]*fv[3];
   339 }
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