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lxdream.org :: lxdream/src/sh4/sh4.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4.c
changeset 930:07e5b11419db
prev929:fd8cb0c82f5f
next931:430048ea8b71
author nkeynes
date Mon Dec 22 09:51:11 2008 +0000 (13 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change Remove pointer cache and add full address-space map. Much better
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 parent module for all CPU modes and SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include <setjmp.h>
    23 #include <assert.h>
    24 #include "lxdream.h"
    25 #include "dreamcast.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "eventq.h"
    29 #include "syscall.h"
    30 #include "sh4/intc.h"
    31 #include "sh4/sh4core.h"
    32 #include "sh4/sh4mmio.h"
    33 #include "sh4/sh4stat.h"
    34 #include "sh4/sh4trans.h"
    35 #include "sh4/xltcache.h"
    37 void sh4_init( void );
    38 void sh4_xlat_init( void );
    39 void sh4_reset( void );
    40 void sh4_start( void );
    41 void sh4_stop( void );
    42 void sh4_save_state( FILE *f );
    43 int sh4_load_state( FILE *f );
    45 uint32_t sh4_run_slice( uint32_t );
    46 uint32_t sh4_xlat_run_slice( uint32_t );
    48 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    49         sh4_start, sh4_run_slice, sh4_stop,
    50         sh4_save_state, sh4_load_state };
    52 struct sh4_registers sh4r __attribute__((aligned(16)));
    53 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    54 int sh4_breakpoint_count = 0;
    55 sh4ptr_t sh4_main_ram;
    56 sh4ptr_t dc_boot_rom;
    57 sh4ptr_t dc_flash_ram;
    58 sh4ptr_t dc_audio_ram;
    60 gboolean sh4_starting = FALSE;
    61 static gboolean sh4_use_translator = FALSE;
    62 static jmp_buf sh4_exit_jmp_buf;
    63 static gboolean sh4_running = FALSE;
    64 struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 };
    66 void sh4_translate_set_enabled( gboolean use )
    67 {
    68     // No-op if the translator was not built
    69 #ifdef SH4_TRANSLATOR
    70     xlat_cache_init();
    71     if( use ) {
    72         sh4_translate_init();
    73     }
    74     sh4_use_translator = use;
    75 #endif
    76 }
    78 gboolean sh4_translate_is_enabled()
    79 {
    80     return sh4_use_translator;
    81 }
    83 void sh4_init(void)
    84 {
    85     register_io_regions( mmio_list_sh4mmio );
    86     sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
    87     dc_boot_rom = mem_get_region_by_name(MEM_REGION_BIOS);
    88     dc_flash_ram = mem_get_region_by_name(MEM_REGION_FLASH);
    89     dc_audio_ram = mem_get_region_by_name(MEM_REGION_AUDIO);
    90     MMU_init();
    91     TMU_init();
    92     sh4_reset();
    93 #ifdef ENABLE_SH4STATS
    94     sh4_stats_reset();
    95 #endif
    96 }
    98 void sh4_start(void)
    99 {
   100     sh4_starting = TRUE;
   101 }
   103 void sh4_reset(void)
   104 {
   105     if(	sh4_use_translator ) {
   106         xlat_flush_cache();
   107     }
   109     /* zero everything out, for the sake of having a consistent state. */
   110     memset( &sh4r, 0, sizeof(sh4r) );
   112     /* Resume running if we were halted */
   113     sh4r.sh4_state = SH4_STATE_RUNNING;
   115     sh4r.pc    = 0xA0000000;
   116     sh4r.new_pc= 0xA0000002;
   117     sh4r.vbr   = 0x00000000;
   118     sh4r.fpscr = 0x00040001;
   119     sh4r.sr    = 0x700000F0;
   121     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
   122     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
   124     /* Peripheral modules */
   125     CPG_reset();
   126     INTC_reset();
   127     MMU_reset();
   128     PMM_reset();
   129     TMU_reset();
   130     SCIF_reset();
   132 #ifdef ENABLE_SH4STATS
   133     sh4_stats_reset();
   134 #endif
   135 }
   137 void sh4_stop(void)
   138 {
   139     if(	sh4_use_translator ) {
   140         /* If we were running with the translator, update new_pc and in_delay_slot */
   141         sh4r.new_pc = sh4r.pc+2;
   142         sh4r.in_delay_slot = FALSE;
   143     }
   145 }
   147 /**
   148  * Execute a timeslice using translated code only (ie translate/execute loop)
   149  */
   150 uint32_t sh4_run_slice( uint32_t nanosecs ) 
   151 {
   152     sh4r.slice_cycle = 0;
   154     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
   155         sh4_sleep_run_slice(nanosecs);
   156     }
   158     /* Setup for sudden vm exits */
   159     switch( setjmp(sh4_exit_jmp_buf) ) {
   160     case CORE_EXIT_BREAKPOINT:
   161         sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
   162         /* fallthrough */
   163     case CORE_EXIT_HALT:
   164         if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   165             TMU_run_slice( sh4r.slice_cycle );
   166             SCIF_run_slice( sh4r.slice_cycle );
   167             PMM_run_slice( sh4r.slice_cycle );
   168             dreamcast_stop();
   169             return sh4r.slice_cycle;
   170         }
   171     case CORE_EXIT_SYSRESET:
   172         dreamcast_reset();
   173         break;
   174     case CORE_EXIT_SLEEP:
   175         sh4_sleep_run_slice(nanosecs);
   176         break;  
   177     case CORE_EXIT_FLUSH_ICACHE:
   178 #ifdef SH4_TRANSLATOR
   179         xlat_flush_cache();
   180 #endif
   181         break;
   182     }
   184     sh4_running = TRUE;
   186     /* Execute the core's real slice */
   187 #ifdef SH4_TRANSLATOR
   188     if( sh4_use_translator ) {
   189         sh4_translate_run_slice(nanosecs);
   190     } else {
   191         sh4_emulate_run_slice(nanosecs);
   192     }
   193 #else
   194     sh4_emulate_run_slice(nanosecs);
   195 #endif
   197     /* And finish off the peripherals afterwards */
   199     sh4_running = FALSE;
   200     sh4_starting = FALSE;
   201     sh4r.slice_cycle = nanosecs;
   202     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   203         TMU_run_slice( nanosecs );
   204         SCIF_run_slice( nanosecs );
   205         PMM_run_slice( sh4r.slice_cycle );
   206     }
   207     return nanosecs;   
   208 }
   210 void sh4_core_exit( int exit_code )
   211 {
   212     if( sh4_running ) {
   213 #ifdef SH4_TRANSLATOR
   214         if( sh4_use_translator ) {
   215             sh4_translate_exit_recover();
   216         }
   217 #endif
   218         // longjmp back into sh4_run_slice
   219         sh4_running = FALSE;
   220         longjmp(sh4_exit_jmp_buf, exit_code);
   221     }
   222 }
   224 void sh4_flush_icache()
   225 {
   226 #ifdef SH4_TRANSLATOR
   227     // FIXME: Special case needs to be generalized
   228     if( sh4_use_translator ) {
   229         if( sh4_translate_flush_cache() ) {
   230             longjmp(sh4_exit_jmp_buf, CORE_EXIT_CONTINUE);
   231         }
   232     }
   233 #endif
   234 }
   236 void sh4_save_state( FILE *f )
   237 {
   238     if(	sh4_use_translator ) {
   239         /* If we were running with the translator, update new_pc and in_delay_slot */
   240         sh4r.new_pc = sh4r.pc+2;
   241         sh4r.in_delay_slot = FALSE;
   242     }
   244     fwrite( &sh4r, sizeof(sh4r), 1, f );
   245     MMU_save_state( f );
   246     PMM_save_state( f );
   247     INTC_save_state( f );
   248     TMU_save_state( f );
   249     SCIF_save_state( f );
   250 }
   252 int sh4_load_state( FILE * f )
   253 {
   254     if(	sh4_use_translator ) {
   255         xlat_flush_cache();
   256     }
   257     fread( &sh4r, sizeof(sh4r), 1, f );
   258     MMU_load_state( f );
   259     PMM_load_state( f );
   260     INTC_load_state( f );
   261     TMU_load_state( f );
   262     return SCIF_load_state( f );
   263 }
   265 void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
   266 {
   267     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   268     sh4_breakpoints[sh4_breakpoint_count].type = type;
   269     if( sh4_use_translator ) {
   270         xlat_invalidate_word( pc );
   271     }
   272     sh4_breakpoint_count++;
   273 }
   275 gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
   276 {
   277     int i;
   279     for( i=0; i<sh4_breakpoint_count; i++ ) {
   280         if( sh4_breakpoints[i].address == pc && 
   281                 sh4_breakpoints[i].type == type ) {
   282             while( ++i < sh4_breakpoint_count ) {
   283                 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   284                 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   285             }
   286             if( sh4_use_translator ) {
   287                 xlat_invalidate_word( pc );
   288             }
   289             sh4_breakpoint_count--;
   290             return TRUE;
   291         }
   292     }
   293     return FALSE;
   294 }
   296 int sh4_get_breakpoint( uint32_t pc )
   297 {
   298     int i;
   299     for( i=0; i<sh4_breakpoint_count; i++ ) {
   300         if( sh4_breakpoints[i].address == pc )
   301             return sh4_breakpoints[i].type;
   302     }
   303     return 0;
   304 }
   306 void sh4_set_pc( int pc )
   307 {
   308     sh4r.pc = pc;
   309     sh4r.new_pc = pc+2;
   310 }
   313 /******************************* Support methods ***************************/
   315 static void sh4_switch_banks( )
   316 {
   317     uint32_t tmp[8];
   319     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   320     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   321     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   322 }
   324 void FASTCALL sh4_switch_fr_banks()
   325 {
   326     int i;
   327     for( i=0; i<16; i++ ) {
   328         float tmp = sh4r.fr[0][i];
   329         sh4r.fr[0][i] = sh4r.fr[1][i];
   330         sh4r.fr[1][i] = tmp;
   331     }
   332 }
   334 void FASTCALL sh4_write_sr( uint32_t newval )
   335 {
   336     int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
   337     int newbank = (newval&SR_MDRB) == SR_MDRB;
   338     if( oldbank != newbank )
   339         sh4_switch_banks();
   340     sh4r.sr = newval & SR_MASK;
   341     sh4r.t = (newval&SR_T) ? 1 : 0;
   342     sh4r.s = (newval&SR_S) ? 1 : 0;
   343     sh4r.m = (newval&SR_M) ? 1 : 0;
   344     sh4r.q = (newval&SR_Q) ? 1 : 0;
   345     intc_mask_changed();
   346 }
   348 void FASTCALL sh4_write_fpscr( uint32_t newval )
   349 {
   350     if( (sh4r.fpscr ^ newval) & FPSCR_FR ) {
   351         sh4_switch_fr_banks();
   352     }
   353     sh4r.fpscr = newval & FPSCR_MASK;
   354 }
   356 uint32_t FASTCALL sh4_read_sr( void )
   357 {
   358     /* synchronize sh4r.sr with the various bitflags */
   359     sh4r.sr &= SR_MQSTMASK;
   360     if( sh4r.t ) sh4r.sr |= SR_T;
   361     if( sh4r.s ) sh4r.sr |= SR_S;
   362     if( sh4r.m ) sh4r.sr |= SR_M;
   363     if( sh4r.q ) sh4r.sr |= SR_Q;
   364     return sh4r.sr;
   365 }
   369 #define RAISE( x, v ) do{			\
   370     if( sh4r.vbr == 0 ) { \
   371         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   372         sh4_core_exit(CORE_EXIT_HALT); return FALSE;	\
   373     } else { \
   374         sh4r.spc = sh4r.pc;	\
   375         sh4r.ssr = sh4_read_sr(); \
   376         sh4r.sgr = sh4r.r[15]; \
   377         MMIO_WRITE(MMU,EXPEVT,x); \
   378         sh4r.pc = sh4r.vbr + v; \
   379         sh4r.new_pc = sh4r.pc + 2; \
   380         sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   381         if( sh4r.in_delay_slot ) { \
   382             sh4r.in_delay_slot = 0; \
   383             sh4r.spc -= 2; \
   384         } \
   385     } \
   386     return TRUE; } while(0)
   388 /**
   389  * Raise a general CPU exception for the specified exception code.
   390  * (NOT for TRAPA or TLB exceptions)
   391  */
   392 gboolean FASTCALL sh4_raise_exception( int code )
   393 {
   394     RAISE( code, EXV_EXCEPTION );
   395 }
   397 /**
   398  * Raise a CPU reset exception with the specified exception code.
   399  */
   400 gboolean FASTCALL sh4_raise_reset( int code )
   401 {
   402     // FIXME: reset modules as per "manual reset"
   403     sh4_reset();
   404     MMIO_WRITE(MMU,EXPEVT,code);
   405     sh4r.vbr = 0;
   406     sh4r.pc = 0xA0000000;
   407     sh4r.new_pc = sh4r.pc + 2;
   408     sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
   409                   &(~SR_FD) );
   410     return TRUE;
   411 }
   413 gboolean FASTCALL sh4_raise_trap( int trap )
   414 {
   415     MMIO_WRITE( MMU, TRA, trap<<2 );
   416     RAISE( EXC_TRAP, EXV_EXCEPTION );
   417 }
   419 gboolean FASTCALL sh4_raise_slot_exception( int normal_code, int slot_code ) {
   420     if( sh4r.in_delay_slot ) {
   421         return sh4_raise_exception(slot_code);
   422     } else {
   423         return sh4_raise_exception(normal_code);
   424     }
   425 }
   427 gboolean FASTCALL sh4_raise_tlb_exception( int code )
   428 {
   429     RAISE( code, EXV_TLBMISS );
   430 }
   432 void FASTCALL sh4_accept_interrupt( void )
   433 {
   434     uint32_t code = intc_accept_interrupt();
   435     sh4r.ssr = sh4_read_sr();
   436     sh4r.spc = sh4r.pc;
   437     sh4r.sgr = sh4r.r[15];
   438     sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   439     MMIO_WRITE( MMU, INTEVT, code );
   440     sh4r.pc = sh4r.vbr + 0x600;
   441     sh4r.new_pc = sh4r.pc + 2;
   442     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   443 }
   445 void FASTCALL signsat48( void )
   446 {
   447     if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
   448         sh4r.mac = 0xFFFF800000000000LL;
   449     else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
   450         sh4r.mac = 0x00007FFFFFFFFFFFLL;
   451 }
   453 void FASTCALL sh4_fsca( uint32_t anglei, float *fr )
   454 {
   455     float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
   456     *fr++ = cosf(angle);
   457     *fr = sinf(angle);
   458 }
   460 /**
   461  * Enter sleep mode (eg by executing a SLEEP instruction).
   462  * Sets sh4_state appropriately and ensures any stopping peripheral modules
   463  * are up to date.
   464  */
   465 void FASTCALL sh4_sleep(void)
   466 {
   467     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   468         sh4r.sh4_state = SH4_STATE_STANDBY;
   469         /* Bring all running peripheral modules up to date, and then halt them. */
   470         TMU_run_slice( sh4r.slice_cycle );
   471         SCIF_run_slice( sh4r.slice_cycle );
   472         PMM_run_slice( sh4r.slice_cycle );
   473     } else {
   474         if( MMIO_READ( CPG, STBCR2 ) & 0x80 ) {
   475             sh4r.sh4_state = SH4_STATE_DEEP_SLEEP;
   476             /* Halt DMAC but other peripherals still running */
   478         } else {
   479             sh4r.sh4_state = SH4_STATE_SLEEP;
   480         }
   481     }
   482     sh4_core_exit( CORE_EXIT_SLEEP );
   483 }
   485 /**
   486  * Wakeup following sleep mode (IRQ or reset). Sets state back to running,
   487  * and restarts any peripheral devices that were stopped.
   488  */
   489 void sh4_wakeup(void)
   490 {
   491     switch( sh4r.sh4_state ) {
   492     case SH4_STATE_STANDBY:
   493         break;
   494     case SH4_STATE_DEEP_SLEEP:
   495         break;
   496     case SH4_STATE_SLEEP:
   497         break;
   498     }
   499     sh4r.sh4_state = SH4_STATE_RUNNING;
   500 }
   502 /**
   503  * Run a time slice (or portion of a timeslice) while the SH4 is sleeping.
   504  * Returns when either the SH4 wakes up (interrupt received) or the end of
   505  * the slice is reached. Updates sh4.slice_cycle with the exit time and
   506  * returns the same value.
   507  */
   508 uint32_t sh4_sleep_run_slice( uint32_t nanosecs )
   509 {
   510     int sleep_state = sh4r.sh4_state;
   511     assert( sleep_state != SH4_STATE_RUNNING );
   513     while( sh4r.event_pending < nanosecs ) {
   514         sh4r.slice_cycle = sh4r.event_pending;
   515         if( sh4r.event_types & PENDING_EVENT ) {
   516             event_execute();
   517         }
   518         if( sh4r.event_types & PENDING_IRQ ) {
   519             sh4_wakeup();
   520             return sh4r.slice_cycle;
   521         }
   522     }
   523     sh4r.slice_cycle = nanosecs;
   524     return sh4r.slice_cycle;
   525 }
   528 /**
   529  * Compute the matrix tranform of fv given the matrix xf.
   530  * Both fv and xf are word-swapped as per the sh4r.fr banks
   531  */
   532 void FASTCALL sh4_ftrv( float *target )
   533 {
   534     float fv[4] = { target[1], target[0], target[3], target[2] };
   535     target[1] = sh4r.fr[1][1] * fv[0] + sh4r.fr[1][5]*fv[1] +
   536     sh4r.fr[1][9]*fv[2] + sh4r.fr[1][13]*fv[3];
   537     target[0] = sh4r.fr[1][0] * fv[0] + sh4r.fr[1][4]*fv[1] +
   538     sh4r.fr[1][8]*fv[2] + sh4r.fr[1][12]*fv[3];
   539     target[3] = sh4r.fr[1][3] * fv[0] + sh4r.fr[1][7]*fv[1] +
   540     sh4r.fr[1][11]*fv[2] + sh4r.fr[1][15]*fv[3];
   541     target[2] = sh4r.fr[1][2] * fv[0] + sh4r.fr[1][6]*fv[1] +
   542     sh4r.fr[1][10]*fv[2] + sh4r.fr[1][14]*fv[3];
   543 }
   545 gboolean sh4_has_page( sh4vma_t vma )
   546 {
   547     sh4addr_t addr = mmu_vma_to_phys_disasm(vma);
   548     return addr != MMU_VMA_ERROR && mem_has_page(addr);
   549 }
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