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lxdream.org :: lxdream/src/aica/armdasm.c
lxdream 0.9.1
released Jun 29
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filename src/aica/armdasm.c
changeset 11:0a82ef380c45
prev7:976a16e92aab
next13:28aea89fb9c6
author nkeynes
date Sun Dec 11 12:00:09 2005 +0000 (14 years ago)
permissions -rw-r--r--
last change Moved arm material under aica/
Hooked arm disasm up
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     1 /*
     2  * armdasm.c    21 Aug 2004  - ARM7tdmi (ARMv4) disassembler
     3  *
     4  * Copyright (c) 2004 Nathan Keynes. Distribution and modification permitted
     5  * under the terms of the GNU General Public License version 2 or later.
     6  */
     8 #include "aica/armcore.h"
     9 #include "aica/armdasm.h"
    10 #include <stdlib.h>
    12 #define COND(ir) (ir>>28)
    13 #define OPCODE(ir) ((ir>>20)&0x1F)
    14 #define GRP(ir) ((ir>>26)&0x03)
    15 #define IFLAG(ir) (ir&0x02000000)
    16 #define SFLAG(ir) (ir&0x00100000)
    17 #define PFLAG(ir) (ir&0x01000000)
    18 #define UFLAG(ir) (ir&0x00800000)
    19 #define BFLAG(ir) (ir&0x00400000)
    20 #define WFLAG(ir) (ir&0x00200000)
    21 #define LFLAG(ir) SFLAG(ir)
    22 #define RN(ir) ((ir>>16)&0x0F)
    23 #define RD(ir) ((ir>>12)&0x0F)
    24 #define RS(ir) ((ir>>8)&0x0F)
    25 #define RM(ir) (ir&0x0F)
    27 #define IMM8(ir) (ir&0xFF)
    28 #define IMM12(ir) (ir&0xFFF)
    29 #define SHIFTIMM(ir) ((ir>>7)&0x1F)
    30 #define IMMROT(ir) ((ir>>7)&0x1E)
    31 #define SHIFT(ir) ((ir>>4)&0x07)
    32 #define DISP24(ir) ((ir&0x00FFFFFF))
    33 #define FSXC(ir) msrFieldMask[RN(ir)]
    34 #define ROTIMM12(ir) ROTATE_RIGHT_LONG(IMM8(ir),IMMROT(ir))
    37 const struct reg_desc_struct arm_reg_map[] = 
    38   { {"R0", REG_INT, &armr.r[0]}, {"R1", REG_INT, &armr.r[1]},
    39     {"R2", REG_INT, &armr.r[2]}, {"R3", REG_INT, &armr.r[3]},
    40     {"R4", REG_INT, &armr.r[4]}, {"R5", REG_INT, &armr.r[5]},
    41     {"R6", REG_INT, &armr.r[6]}, {"R7", REG_INT, &armr.r[7]},
    42     {"R8", REG_INT, &armr.r[8]}, {"R9", REG_INT, &armr.r[9]},
    43     {"R10",REG_INT, &armr.r[10]}, {"R11",REG_INT, &armr.r[11]},
    44     {"R12",REG_INT, &armr.r[12]}, {"R13",REG_INT, &armr.r[13]},
    45     {"R14",REG_INT, &armr.r[14]}, {"R15",REG_INT, &armr.r[15]},
    46     {"CPSR", REG_INT, &armr.cpsr}, {"SPSR", REG_INT, &armr.spsr},
    47     {NULL, 0, NULL} };
    50 const struct cpu_desc_struct arm_cpu_desc = { "ARM7", arm_disasm_instruction, 4,
    51 					(char *)&armr, sizeof(armr), arm_reg_map,
    52 					&armr.r[15], &armr.icount };
    53 const struct cpu_desc_struct armt_cpu_desc = { "ARM7T", armt_disasm_instruction, 2,
    54 					 (char*)&armr, sizeof(armr), arm_reg_map,
    55 					 &armr.r[15], &armr.icount };
    60 char *conditionNames[] = { "EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", 
    61                            "HI", "LS", "GE", "LT", "GT", "LE", "  " /*AL*/, "NV" };
    63                          /* fsxc */
    64 char *msrFieldMask[] = { "", "c", "x", "xc", "s", "sc", "sx", "sxc",
    65 	                     "f", "fc", "fx", "fxc", "fs", "fsc", "fsx", "fsxc" };
    66 char *ldmModes[] = { "DA", "IA", "DB", "IB" };
    68 #define UNIMP(ir) snprintf( buf, len, "???     " )
    70 int arm_disasm_shift_operand( uint32_t ir, char *buf, int len )
    71 {
    72 	uint32_t operand, tmp;
    73 	if( IFLAG(ir) == 0 ) {
    74 		switch(SHIFT(ir)) {
    75 		case 0: /* (Rm << imm) */
    76 			return snprintf(buf, len, "R%d << %d", RM(ir), SHIFTIMM(ir) );
    77 		case 1: /* (Rm << Rs) */
    78 			return snprintf(buf, len, "R%d << R%d", RM(ir), RS(ir) );
    79 		case 2: /* (Rm >> imm) */
    80 			return snprintf(buf, len, "R%d >> %d", RM(ir), SHIFTIMM(ir) );
    81 		case 3: /* (Rm >> Rs) */
    82 			return snprintf(buf, len, "R%d >> R%d", RM(ir), RS(ir) );
    83 		case 4: /* (Rm >>> imm) */
    84 			return snprintf(buf, len, "R%d >>> %d", RM(ir), SHIFTIMM(ir) );
    85 		case 5: /* (Rm >>> Rs) */
    86 			return snprintf(buf, len, "R%d >>> R%d", RM(ir), RS(ir) );
    87 		case 6:
    88 			tmp = SHIFTIMM(ir);
    89 			if( tmp == 0 ) /* RRX aka rotate with carry */
    90 				return snprintf(buf, len, "R%d roc 1", RM(ir) );
    91 			else
    92 				return snprintf(buf, len, "R%d rot %d", RM(ir), SHIFTIMM(ir) );
    93 		case 7:
    94 			return snprintf(buf, len, "R%d rot R%d", RM(ir), RS(ir) );
    95 		}
    96 	} else {
    97 		operand = IMM8(ir);
    98 		tmp = IMMROT(ir);
    99 		operand = ROTATE_RIGHT_LONG(operand, tmp);
   100 		return snprintf(buf, len, "%08X", operand );
   101 	}
   102 }
   104 static int arm_disasm_address_index( uint32_t ir, char *buf, int len )
   105 {
   106 	uint32_t tmp;
   108 	switch(SHIFT(ir)) {
   109 	case 0: /* (Rm << imm) */
   110 		return snprintf( buf, len, "R%d << %d", RM(ir), SHIFTIMM(ir) );
   111 	case 2: /* (Rm >> imm) */
   112 		return snprintf( buf, len, "R%d >> %d", RM(ir), SHIFTIMM(ir) );
   113 	case 4: /* (Rm >>> imm) */
   114 		return snprintf( buf, len, "R%d >>> %d", RM(ir), SHIFTIMM(ir) );
   115 	case 6:
   116 		tmp = SHIFTIMM(ir);
   117 		if( tmp == 0 ) /* RRX aka rotate with carry */
   118 			return snprintf( buf, len, "R%d roc 1", RM(ir) );
   119 		else
   120 			return snprintf( buf, len, "R%d rot %d", RM(ir), tmp );
   121 	default: 
   122 		return UNIMP(ir);
   123 	}
   124 }
   126 static int arm_disasm_address_operand( uint32_t ir, char *buf, int len )
   127 {
   128     char  shift[32];
   130 	char sign = UFLAG(ir) ? '-' : '+';
   131 	/* I P U . W */
   132 	switch( (ir>>21)&0x19 ) {
   133 	case 0: /* Rn -= imm offset (post-indexed) [5.2.8 A5-28] */
   134 	case 1:
   135 		return snprintf( buf, len, "[R%d], R%d %c= %04X", RN(ir), RN(ir), sign, IMM12(ir) );
   136 	case 8: /* Rn - imm offset  [5.2.2 A5-20] */
   137 		return snprintf( buf, len, "[R%d %c %04X]", RN(ir), sign, IMM12(ir) );
   138 	case 9: /* Rn -= imm offset (pre-indexed)  [5.2.5 A5-24] */
   139 		return snprintf( buf, len, "[R%d %c= %04X]", RN(ir), sign, IMM12(ir) );
   140 	case 16: /* Rn -= Rm (post-indexed)  [5.2.10 A5-32 ] */
   141 	case 17:
   142 		arm_disasm_address_index( ir, shift, sizeof(shift) );
   143 		return snprintf( buf, len, "[R%d], R%d %c= %s", RN(ir), RN(ir), sign, shift );
   144 	case 24: /* Rn - Rm  [5.2.4 A5-23] */
   145 		arm_disasm_address_index( ir, shift, sizeof(shift) );
   146 		return snprintf( buf, len, "[R%d %c %s]", RN(ir), sign, shift );
   147 	case 25: /* RN -= Rm (pre-indexed)  [5.2.7 A5-26] */
   148 		arm_disasm_address_index( ir, shift, sizeof(shift) );
   149 		return snprintf( buf, len, "[R%d %c= %s]", RN(ir), sign, shift );
   150 	default:
   151 		return UNIMP(ir); /* Unreachable */
   152 	}
   153 }
   155 uint32_t arm_disasm_instruction( uint32_t pc, char *buf, int len, char *opcode )
   156 {
   157     char operand[32];
   158     uint32_t ir = arm_read_long(pc);
   159     int i,j;
   161     sprintf( opcode, "%02X %02X %02X %02X", ir&0xFF, (ir>>8) & 0xFF,
   162 	     (ir>>16)&0xFF, (ir>>24) );
   164     if( COND(ir) == 0x0F ) {
   165     	UNIMP(ir);
   166     	return pc+4;
   167     }
   168     char *cond = conditionNames[COND(ir)];
   170 	switch( GRP(ir) ) {
   171 	case 0:
   172 		if( (ir & 0x0D900000) == 0x01000000 ) {
   173 			/* Instructions that aren't actual data processing */
   174 			switch( ir & 0x0FF000F0 ) {
   175 			case 0x01200010: /* BXcc */
   176 				snprintf(buf, len, "BX%s     R%d", cond, RM(ir));
   177 				break;
   178 			case 0x01000000: /* MRS Rd, CPSR */
   179 				snprintf(buf, len, "MRS%s    R%d, CPSR", cond, RD(ir));
   180 				break;
   181 			case 0x01400000: /* MRS Rd, SPSR */
   182 				snprintf(buf, len, "MRS%s    R%d, SPSR", cond, RD(ir));
   183 				break;
   184 			case 0x01200000: /* MSR CPSR, Rm */
   185 				snprintf(buf, len, "MSR%s    CPSR_%s, R%d", cond, FSXC(ir), RM(ir));
   186 				break;
   187 			case 0x01600000: /* MSR SPSR, Rm */
   188 				snprintf(buf, len, "MSR%s    SPSR_%s, R%d", cond, FSXC(ir), RM(ir));
   189 				break;
   190 			case 0x03200000: /* MSR CPSR, imm */
   191 				snprintf(buf, len, "MSR%s    CPSR_%s, #%08X", cond, FSXC(ir), ROTIMM12(ir));
   192 				break;
   193 			case 0x03600000: /* MSR SPSR, imm */
   194 				snprintf(buf, len, "MSR%s    SPSR_%s, #%08X", cond, FSXC(ir), ROTIMM12(ir));
   195 				break;
   196 			default:
   197 				UNIMP();
   198 			}
   199 		} else if( (ir & 0x0E000090) == 0x00000090 ) {
   200 			/* Neither are these */
   201 			switch( (ir>>5)&0x03 ) {
   202 			case 0:
   203 				/* Arithmetic extension area */
   204 				switch(OPCODE(ir)) {
   205 				case 0: /* MUL */
   206 					snprintf(buf,len, "MUL%s    R%d, R%d, R%d", cond, RN(ir), RM(ir), RS(ir) );
   207 					break;
   208 				case 1: /* MULS */
   209 					break;
   210 				case 2: /* MLA */
   211 					snprintf(buf,len, "MLA%s    R%d, R%d, R%d, R%d", cond, RN(ir), RM(ir), RS(ir), RD(ir) );
   212 					break;
   213 				case 3: /* MLAS */
   214 					break;
   215 				case 8: /* UMULL */
   216 					snprintf(buf,len, "UMULL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
   217 					break;
   218 				case 9: /* UMULLS */
   219 					break;
   220 				case 10: /* UMLAL */
   221 					snprintf(buf,len, "UMLAL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
   222 					break;
   223 				case 11: /* UMLALS */
   224 					break;
   225 				case 12: /* SMULL */
   226 					snprintf(buf,len, "SMULL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
   227 					break;
   228 				case 13: /* SMULLS */
   229 					break;
   230 				case 14: /* SMLAL */
   231 					snprintf(buf,len, "SMLAL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
   232 					break;
   233 				case 15: /* SMLALS */
   235 					break;
   236 				case 16: /* SWP */
   237 					snprintf(buf,len, "SWP%s    R%d, R%d, [R%d]", cond, RD(ir), RN(ir), RM(ir) );
   238 					break;
   239 				case 20: /* SWPB */
   240 					snprintf(buf,len, "SWPB%s   R%d, R%d, [R%d]", cond, RD(ir), RN(ir), RM(ir) );
   241 					break;
   242 				default:
   243 					UNIMP(ir);
   244 				}
   245 				break;
   246 			case 1:
   247 				if( LFLAG(ir) ) {
   248 					/* LDRH */
   249 				} else {
   250 					/* STRH */
   251 				}
   252 				break;
   253 			case 2:
   254 				if( LFLAG(ir) ) {
   255 					/* LDRSB */
   256 				} else {
   257 					UNIMP(ir);
   258 				}
   259 				break;
   260 			case 3:
   261 				if( LFLAG(ir) ) {
   262 					/* LDRSH */
   263 				} else {
   264 					UNIMP(ir);
   265 				}
   266 				break;
   267 			}
   268 		} else {
   269 			/* Data processing */
   271 			switch(OPCODE(ir)) {
   272 			case 0: /* AND Rd, Rn, operand */
   273 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   274 				snprintf(buf, len, "AND%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   275 				break;
   276 			case 1: /* ANDS Rd, Rn, operand */
   277 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   278 				snprintf(buf, len, "ANDS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   279 				break;
   280 			case 2: /* EOR Rd, Rn, operand */
   281 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   282 				snprintf(buf, len, "EOR%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   283 				break;
   284 			case 3: /* EORS Rd, Rn, operand */
   285 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   286 				snprintf(buf, len, "EORS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   287 				break;
   288 			case 4: /* SUB Rd, Rn, operand */
   289 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   290 				snprintf(buf, len, "SUB%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   291 				break;
   292 			case 5: /* SUBS Rd, Rn, operand */
   293 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   294 				snprintf(buf, len, "SUBS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   295 				break;
   296 			case 6: /* RSB Rd, Rn, operand */
   297 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   298 				snprintf(buf, len, "RSB%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   299 				break;
   300 			case 7: /* RSBS Rd, Rn, operand */
   301 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   302 				snprintf(buf, len, "RSBS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   303 				break;
   304 			case 8: /* ADD Rd, Rn, operand */
   305 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   306 				snprintf(buf, len, "ADD%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   307 				break;
   308 			case 9: /* ADDS Rd, Rn, operand */
   309 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   310 				snprintf(buf, len, "ADDS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   311 				break;
   312 			case 10: /* ADC Rd, Rn, operand */
   313 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   314 				snprintf(buf, len, "ADC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   315 				break;
   316 			case 11: /* ADCS Rd, Rn, operand */
   317 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   318 				snprintf(buf, len, "ADCS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   319 				break;
   320 			case 12: /* SBC Rd, Rn, operand */
   321 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   322 				snprintf(buf, len, "SBC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   323 				break;
   324 			case 13: /* SBCS Rd, Rn, operand */
   325 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   326 				snprintf(buf, len, "SBCS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   327 				break;
   328 			case 14: /* RSC Rd, Rn, operand */
   329 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   330 				snprintf(buf, len, "RSC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   331 				break;
   332 			case 15: /* RSCS Rd, Rn, operand */
   333 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   334 				snprintf(buf, len, "RSCS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   335 				break;
   336 			case 16: /* TST Rd, Rn, operand */
   337 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   338 				snprintf(buf, len, "TST%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   339 				break;
   340 			case 18: /* TEQ Rd, Rn, operand */
   341 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   342 				snprintf(buf, len, "TEQ%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   343 				break;
   344 			case 20: /* CMP Rd, Rn, operand */
   345 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   346 				snprintf(buf, len, "CMP%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   347 				break;
   348 			case 22: /* CMN Rd, Rn, operand */
   349 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   350 				snprintf(buf, len, "CMN%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   351 				break;
   352 			case 24: /* ORR Rd, Rn, operand */
   353 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   354 				snprintf(buf, len, "ORR%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   355 				break;
   356 			case 25: /* ORRS Rd, Rn, operand */
   357 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   358 				snprintf(buf, len, "ORRS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   359 				break;
   360 			case 26: /* MOV Rd, Rn, operand */
   361 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   362 				snprintf(buf, len, "MOV%s    R%d, %s", cond, RD(ir), operand);
   363 				break;
   364 			case 27: /* MOVS Rd, Rn, operand */
   365 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   366 				snprintf(buf, len, "MOVS%s   R%d, %s", cond, RD(ir), operand);
   367 				break;
   368 			case 28: /* BIC Rd, Rn, operand */
   369 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   370 				snprintf(buf, len, "BIC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   371 				break;
   372 			case 29: /* BICS Rd, Rn, operand */
   373 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   374 				snprintf(buf, len, "BICS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   375 				break;
   376 			case 30: /* MVN Rd, Rn, operand */
   377 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   378 				snprintf(buf, len, "MVN%s    R%d, %s", cond, RD(ir), operand);
   379 				break;
   380 			case 31: /* MVNS Rd, Rn, operand */
   381 				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   382 				snprintf(buf, len, "MVNS%s   R%d, %s", cond, RD(ir), operand);
   383 				break;
   384 			default:
   385 				UNIMP(ir);
   386 			}
   387 		}
   388 		break;
   389 	case 1: /* Load/store */
   390 		arm_disasm_address_operand( ir, operand, sizeof(operand) );
   391 		switch( (ir>>20)&0x17 ) {
   392 			case 0:
   393 			case 16:
   394 			case 18:
   395 				snprintf(buf, len, "STR%s    R%d, %s", cond, RD(ir), operand );
   396 				break;
   397 			case 1:
   398 			case 17:
   399 			case 19:
   400 				snprintf(buf, len, "LDR%s    R%d, %s", cond, RD(ir), operand );
   401 				break;
   402 			case 2:
   403 				snprintf(buf, len, "STRT%s   R%d, %s", cond, RD(ir), operand );
   404 				break;
   405 			case 3:
   406 				snprintf(buf, len, "LDRT%s   R%d, %s", cond, RD(ir), operand );
   407 				break;
   408 			case 4:
   409 			case 20:
   410 			case 22:
   411 				snprintf(buf, len, "STRB%s   R%d, %s", cond, RD(ir), operand );
   412 				break;
   413 			case 5:
   414 			case 21:
   415 			case 23:
   416 				snprintf(buf, len, "LDRB%s   R%d, %s", cond, RD(ir), operand );
   417 				break;
   418 			case 6:
   419 				snprintf(buf, len, "STRBT%s  R%d, %s", cond, RD(ir), operand );
   420 				break;
   421 			case 7: 
   422 				snprintf(buf, len, "LDRBT%s  R%d, %s", cond, RD(ir), operand );
   423 				break;
   424 		}
   425 		break;
   426 	case 2: /* Load/store multiple, branch*/
   427 		j = snprintf( buf, len, LFLAG(ir) ? "LDM%s%s  R%d%c,":"STM%s%s  R%d%c,", 
   428 	              ldmModes[(ir>>23)&0x03], cond, RN(ir), WFLAG(ir)?'!':' ' );
   429 		buf += j;
   430 		len -= j;
   431 		for( i = 0; i<16 && len > 2; i++ ) {
   432 			if( (ir >> i)&1 ) {
   433 				j = snprintf( buf, len, "R%d", i );
   434 				buf+=j;
   435 				len-=j;
   436 			}
   437 		}
   438 		if( SFLAG(ir) && len > 0 ) {
   439 			buf[0] = '^';
   440 			buf[1] = '\0';
   441 		}
   442 		break;
   443 	case 3: /* Copro */
   444 		UNIMP(ir);
   445 		break;
   446 	}
   450 	return pc+4;
   451 }
   454 uint32_t armt_disasm_instruction( uint32_t pc, char *buf, int len, char *opcode )
   455 {
   456     uint32_t ir = arm_read_word(pc);
   457     sprintf( opcode, "%02X %02X", ir&0xFF, (ir>>8) );
   458     UNIMP(ir);
   459     return pc+2;
   460 }
.