Search
lxdream.org :: lxdream/src/sh4/sh4core.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/sh4core.c
changeset 43:0cf3e339cc59
prev38:9ccc7ac66a9d
next53:f2981805b929
author nkeynes
date Mon Dec 26 11:47:15 2005 +0000 (14 years ago)
permissions -rw-r--r--
last change Add sh4 + arm breakpoints
Hook up break button in GUI
Enable ARM slice in main loop
view annotate diff log raw
     1 /**
     2  * $Id: sh4core.c,v 1.16 2005-12-26 11:47:15 nkeynes Exp $
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "sh4core.h"
    24 #include "sh4mmio.h"
    25 #include "mem.h"
    26 #include "clock.h"
    27 #include "intc.h"
    29 /* CPU-generated exception code/vector pairs */
    30 #define EXC_POWER_RESET  0x000 /* vector special */
    31 #define EXC_MANUAL_RESET 0x020
    32 #define EXC_SLOT_ILLEGAL 0x1A0
    33 #define EXC_ILLEGAL      0x180
    34 #define EXV_ILLEGAL      0x100
    35 #define EXC_TRAP         0x160
    36 #define EXV_TRAP         0x100
    37 #define EXC_FPDISABLE    0x800
    38 #define EXV_FPDISABLE    0x100
    40 uint32_t sh4_freq = SH4_BASE_RATE;
    41 uint32_t sh4_bus_freq = SH4_BASE_RATE;
    42 uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 2;
    44 uint32_t sh4_cpu_period = 1000 / SH4_BASE_RATE; /* in nanoseconds */
    45 uint32_t sh4_bus_period = 1000 / SH4_BASE_RATE;
    46 uint32_t sh4_peripheral_period = 2000 / SH4_BASE_RATE;
    48 /********************** SH4 Module Definition ****************************/
    50 void sh4_init( void );
    51 void sh4_reset( void );
    52 uint32_t sh4_run_slice( uint32_t );
    53 void sh4_start( void );
    54 void sh4_stop( void );
    55 void sh4_save_state( FILE *f );
    56 int sh4_load_state( FILE *f );
    58 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    59 				       NULL, sh4_run_slice, sh4_stop,
    60 				       sh4_save_state, sh4_load_state };
    62 struct sh4_registers sh4r;
    64 void sh4_init(void)
    65 {
    66     register_io_regions( mmio_list_sh4mmio );
    67     mmu_init();
    68     sh4_reset();
    69 }
    71 void sh4_reset(void)
    72 {
    73     /* zero everything out, for the sake of having a consistent state. */
    74     memset( &sh4r, 0, sizeof(sh4r) );
    76     /* Resume running if we were halted */
    77     sh4r.sh4_state = SH4_STATE_RUNNING;
    79     sh4r.pc    = 0xA0000000;
    80     sh4r.new_pc= 0xA0000002;
    81     sh4r.vbr   = 0x00000000;
    82     sh4r.fpscr = 0x00040001;
    83     sh4r.sr    = 0x700000F0;
    85     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
    86     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
    88     /* Peripheral modules */
    89     intc_reset();
    90     SCIF_reset();
    91 }
    93 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    94 static int sh4_breakpoint_count = 0;
    96 void sh4_set_breakpoint( uint32_t pc, int type )
    97 {
    98     sh4_breakpoints[sh4_breakpoint_count].address = pc;
    99     sh4_breakpoints[sh4_breakpoint_count].type = type;
   100     sh4_breakpoint_count++;
   101 }
   103 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
   104 {
   105     int i;
   107     for( i=0; i<sh4_breakpoint_count; i++ ) {
   108 	if( sh4_breakpoints[i].address == pc && 
   109 	    sh4_breakpoints[i].type == type ) {
   110 	    while( ++i < sh4_breakpoint_count ) {
   111 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   112 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   113 	    }
   114 	    sh4_breakpoint_count--;
   115 	    return TRUE;
   116 	}
   117     }
   118     return FALSE;
   119 }
   121 int sh4_get_breakpoint( uint32_t pc )
   122 {
   123     int i;
   124     for( i=0; i<sh4_breakpoint_count; i++ ) {
   125 	if( sh4_breakpoints[i].address == pc )
   126 	    return sh4_breakpoints[i].type;
   127     }
   128     return 0;
   129 }
   131 uint32_t sh4_run_slice( uint32_t nanosecs ) 
   132 {
   133     int target = sh4r.icount + nanosecs / sh4_cpu_period;
   134     int start = sh4r.icount;
   135     int i;
   137     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
   138 	if( sh4r.int_pending != 0 )
   139 	    sh4r.sh4_state = SH4_STATE_RUNNING;;
   140     }
   142     while( sh4r.icount < target && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   143 	sh4r.icount++;
   144 	if( !sh4_execute_instruction() )
   145 	    break;
   146 #ifdef ENABLE_DEBUG_MODE
   147 	for( i=0; i<sh4_breakpoint_count; i++ ) {
   148 	    if( sh4_breakpoints[i].address == sh4r.pc ) {
   149 		break;
   150 	    }
   151 	}
   152 	if( i != sh4_breakpoint_count ) {
   153 	    dreamcast_stop();
   154 	    if( sh4_breakpoints[i].type == BREAK_ONESHOT )
   155 		sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
   156 	    break;
   157 	}
   158 #endif	
   159     }
   161     /* If we aborted early, but the cpu is still technically running,
   162      * we're doing a hard abort - cut the timeslice back to what we
   163      * actually executed
   164      */
   165     if( target != sh4r.icount && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   166 	/* Halted - compute time actually executed */
   167 	nanosecs = (sh4r.icount - start) * sh4_cpu_period;
   168     }
   169     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   170 	TMU_run_slice( nanosecs );
   171 	SCIF_run_slice( nanosecs );
   172     }
   173     return nanosecs;
   174 }
   176 void sh4_stop(void)
   177 {
   179 }
   181 void sh4_save_state( FILE *f )
   182 {
   183     fwrite( &sh4r, sizeof(sh4r), 1, f );
   184     SCIF_save_state( f );
   185 }
   187 int sh4_load_state( FILE * f )
   188 {
   189     fread( &sh4r, sizeof(sh4r), 1, f );
   190     return SCIF_load_state( f );
   191 }
   193 /********************** SH4 emulation core  ****************************/
   195 void sh4_set_pc( int pc )
   196 {
   197     sh4r.pc = pc;
   198     sh4r.new_pc = pc+2;
   199 }
   201 #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); RAISE( EXC_ILLEGAL, EXV_ILLEGAL ); }while(0)
   202 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
   204 #define RAISE( x, v ) do{ \
   205     if( sh4r.vbr == 0 ) { \
   206         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   207         sh4_stop(); \
   208     } else { \
   209         sh4r.spc = sh4r.pc + 2; \
   210         sh4r.ssr = sh4_read_sr(); \
   211         sh4r.sgr = sh4r.r[15]; \
   212         MMIO_WRITE(MMU,EXPEVT,x); \
   213         sh4r.pc = sh4r.vbr + v; \
   214         sh4r.new_pc = sh4r.pc + 2; \
   215         sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   216     } \
   217     return TRUE; } while(0)
   219 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
   220 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
   221 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
   222 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
   223 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
   224 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
   226 #define MEM_FP_READ( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
   227     ((uint32_t *)FR)[(reg)&0xE0] = sh4_read_long(addr); \
   228     ((uint32_t *)FR)[(reg)|1] = sh4_read_long(addr+4); \
   229 } else ((uint32_t *)FR)[reg] = sh4_read_long(addr)
   231 #define MEM_FP_WRITE( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
   232     sh4_write_long( addr, ((uint32_t *)FR)[(reg)&0xE0] ); \
   233     sh4_write_long( addr+4, ((uint32_t *)FR)[(reg)|1] ); \
   234 } else sh4_write_long( addr, ((uint32_t *)FR)[reg] )
   236 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   238 #define CHECK( x, c, v ) if( !x ) RAISE( c, v )
   239 #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
   240 #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
   241 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_stop(); return; }
   242 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }
   244 static void sh4_switch_banks( )
   245 {
   246     uint32_t tmp[8];
   248     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   249     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   250     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   251 }
   253 static void sh4_load_sr( uint32_t newval )
   254 {
   255     if( (newval ^ sh4r.sr) & SR_RB )
   256         sh4_switch_banks();
   257     sh4r.sr = newval;
   258     sh4r.t = (newval&SR_T) ? 1 : 0;
   259     sh4r.s = (newval&SR_S) ? 1 : 0;
   260     sh4r.m = (newval&SR_M) ? 1 : 0;
   261     sh4r.q = (newval&SR_Q) ? 1 : 0;
   262     intc_mask_changed();
   263 }
   265 static uint32_t sh4_read_sr( void )
   266 {
   267     /* synchronize sh4r.sr with the various bitflags */
   268     sh4r.sr &= SR_MQSTMASK;
   269     if( sh4r.t ) sh4r.sr |= SR_T;
   270     if( sh4r.s ) sh4r.sr |= SR_S;
   271     if( sh4r.m ) sh4r.sr |= SR_M;
   272     if( sh4r.q ) sh4r.sr |= SR_Q;
   273     return sh4r.sr;
   274 }
   275 /* function for external use */
   276 void sh4_raise_exception( int code, int vector )
   277 {
   278     RAISE(code, vector);
   279 }
   281 static void sh4_accept_interrupt( void )
   282 {
   283     uint32_t code = intc_accept_interrupt();
   284     sh4r.ssr = sh4_read_sr();
   285     sh4r.spc = sh4r.pc;
   286     sh4r.sgr = sh4r.r[15];
   287     sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   288     MMIO_WRITE( MMU, INTEVT, code );
   289     sh4r.pc = sh4r.vbr + 0x600;
   290     sh4r.new_pc = sh4r.pc + 2;
   291     WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   292 }
   294 gboolean sh4_execute_instruction( void )
   295 {
   296     int pc;
   297     unsigned short ir;
   298     uint32_t tmp;
   299     uint64_t tmpl;
   301 #define R0 sh4r.r[0]
   302 #define FR0 (FR[0])
   303 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
   304 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
   305 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
   306 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
   307 #define DISP8(ir) (ir&0x00FF)
   308 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
   309 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
   310 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
   311 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
   312 #define FVN(ir) ((ir&0x0C00)>>8)
   313 #define FVM(ir) ((ir&0x0300)>>6)
   314 #define FRN(ir) (FR[(ir&0x0F00)>>8])
   315 #define FRM(ir) (FR[(ir&0x00F0)>>4])
   316 #define FRNi(ir) (((uint32_t *)FR)[(ir&0x0F00)>>8])
   317 #define FRMi(ir) (((uint32_t *)FR)[(ir&0x00F0)>>4])
   318 #define DRN(ir) (((double *)FR)[(ir&0x0E00)>>9])
   319 #define DRM(ir) (((double *)FR)[(ir&0x00E0)>>5])
   320 #define DRNi(ir) (((uint64_t *)FR)[(ir&0x0E00)>>9])
   321 #define DRMi(ir) (((uint64_t *)FR)[(ir&0x00E0)>>5])
   322 #define FRNn(ir) ((ir&0x0F00)>>8)
   323 #define FRMn(ir) ((ir&0x00F0)>>4)
   324 #define FPULf   *((float *)&sh4r.fpul)
   325 #define FPULi    (sh4r.fpul)
   327     if( SH4_INT_PENDING() ) 
   328         sh4_accept_interrupt();
   330     pc = sh4r.pc;
   331     ir = MEM_READ_WORD(pc);
   332     sh4r.icount++;
   334     switch( (ir&0xF000)>>12 ) {
   335         case 0: /* 0000nnnnmmmmxxxx */
   336             switch( ir&0x000F ) {
   337                 case 2:
   338                     switch( (ir&0x00F0)>>4 ) {
   339                         case 0: /* STC     SR, Rn */
   340                             CHECKPRIV();
   341                             RN(ir) = sh4_read_sr();
   342                             break;
   343                         case 1: /* STC     GBR, Rn */
   344                             RN(ir) = sh4r.gbr;
   345                             break;
   346                         case 2: /* STC     VBR, Rn */
   347                             CHECKPRIV();
   348                             RN(ir) = sh4r.vbr;
   349                             break;
   350                         case 3: /* STC     SSR, Rn */
   351                             CHECKPRIV();
   352                             RN(ir) = sh4r.ssr;
   353                             break;
   354                         case 4: /* STC     SPC, Rn */
   355                             CHECKPRIV();
   356                             RN(ir) = sh4r.spc;
   357                             break;
   358                         case 8: case 9: case 10: case 11: case 12: case 13:
   359                         case 14: case 15:/* STC     Rm_bank, Rn */
   360                             CHECKPRIV();
   361                             RN(ir) = RN_BANK(ir);
   362                             break;
   363                         default: UNDEF(ir);
   364                     }
   365                     break;
   366                 case 3:
   367                     switch( (ir&0x00F0)>>4 ) {
   368                         case 0: /* BSRF    Rn */
   369                             CHECKDEST( pc + 4 + RN(ir) );
   370                             CHECKSLOTILLEGAL();
   371                             sh4r.in_delay_slot = 1;
   372                             sh4r.pr = sh4r.pc + 4;
   373                             sh4r.pc = sh4r.new_pc;
   374                             sh4r.new_pc = pc + 4 + RN(ir);
   375                             return TRUE;
   376                         case 2: /* BRAF    Rn */
   377                             CHECKDEST( pc + 4 + RN(ir) );
   378                             CHECKSLOTILLEGAL();
   379                             sh4r.in_delay_slot = 1;
   380                             sh4r.pc = sh4r.new_pc;
   381                             sh4r.new_pc = pc + 4 + RN(ir);
   382                             return TRUE;
   383                         case 8: /* PREF    [Rn] */
   384                             tmp = RN(ir);
   385                             if( (tmp & 0xFC000000) == 0xE0000000 ) {
   386                                 /* Store queue operation */
   387                                 int queue = (tmp&0x20)>>2;
   388                                 int32_t *src = &sh4r.store_queue[queue];
   389                                 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
   390                                 uint32_t target = tmp&0x03FFFFE0 | hi;
   391                                 mem_copy_to_sh4( target, src, 32 );
   392 				//                                WARN( "Executed SQ%c => %08X",
   393 				//                                      (queue == 0 ? '0' : '1'), target );
   394                             }
   395                             break;
   396                         case 9: /* OCBI    [Rn] */
   397                         case 10:/* OCBP    [Rn] */
   398                         case 11:/* OCBWB   [Rn] */
   399                             /* anything? */
   400                             break;
   401                         case 12:/* MOVCA.L R0, [Rn] */
   402                             UNIMP(ir);
   403                         default: UNDEF(ir);
   404                     }
   405                     break;
   406                 case 4: /* MOV.B   Rm, [R0 + Rn] */
   407                     MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
   408                     break;
   409                 case 5: /* MOV.W   Rm, [R0 + Rn] */
   410                     MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
   411                     break;
   412                 case 6: /* MOV.L   Rm, [R0 + Rn] */
   413                     MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
   414                     break;
   415                 case 7: /* MUL.L   Rm, Rn */
   416                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   417                         (RM(ir) * RN(ir));
   418                     break;
   419                 case 8: 
   420                     switch( (ir&0x0FF0)>>4 ) {
   421                         case 0: /* CLRT    */
   422                             sh4r.t = 0;
   423                             break;
   424                         case 1: /* SETT    */
   425                             sh4r.t = 1;
   426                             break;
   427                         case 2: /* CLRMAC  */
   428                             sh4r.mac = 0;
   429                             break;
   430                         case 3: /* LDTLB   */
   431                             break;
   432                         case 4: /* CLRS    */
   433                             sh4r.s = 0;
   434                             break;
   435                         case 5: /* SETS    */
   436                             sh4r.s = 1;
   437                             break;
   438                         default: UNDEF(ir);
   439                     }
   440                     break;
   441                 case 9: 
   442                     if( (ir&0x00F0) == 0x20 ) /* MOVT    Rn */
   443                         RN(ir) = sh4r.t;
   444                     else if( ir == 0x0019 ) /* DIV0U   */
   445                         sh4r.m = sh4r.q = sh4r.t = 0;
   446                     else if( ir == 0x0009 )
   447                         /* NOP     */;
   448                     else UNDEF(ir);
   449                     break;
   450                 case 10:
   451                     switch( (ir&0x00F0) >> 4 ) {
   452                         case 0: /* STS     MACH, Rn */
   453                             RN(ir) = sh4r.mac >> 32;
   454                             break;
   455                         case 1: /* STS     MACL, Rn */
   456                             RN(ir) = (uint32_t)sh4r.mac;
   457                             break;
   458                         case 2: /* STS     PR, Rn */
   459                             RN(ir) = sh4r.pr;
   460                             break;
   461                         case 3: /* STC     SGR, Rn */
   462                             CHECKPRIV();
   463                             RN(ir) = sh4r.sgr;
   464                             break;
   465                         case 5:/* STS      FPUL, Rn */
   466                             RN(ir) = sh4r.fpul;
   467                             break;
   468                         case 6: /* STS     FPSCR, Rn */
   469                             RN(ir) = sh4r.fpscr;
   470                             break;
   471                         case 15:/* STC     DBR, Rn */
   472                             CHECKPRIV();
   473                             RN(ir) = sh4r.dbr;
   474                             break;
   475                         default: UNDEF(ir);
   476                     }
   477                     break;
   478                 case 11:
   479                     switch( (ir&0x0FF0)>>4 ) {
   480                         case 0: /* RTS     */
   481                             CHECKDEST( sh4r.pr );
   482                             CHECKSLOTILLEGAL();
   483                             sh4r.in_delay_slot = 1;
   484                             sh4r.pc = sh4r.new_pc;
   485                             sh4r.new_pc = sh4r.pr;
   486                             return TRUE;
   487                         case 1: /* SLEEP   */
   488 			    if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   489 				sh4r.sh4_state = SH4_STATE_STANDBY;
   490 			    } else {
   491 				sh4r.sh4_state = SH4_STATE_SLEEP;
   492 			    }
   493 			    return FALSE; /* Halt CPU */
   494                         case 2: /* RTE     */
   495                             CHECKPRIV();
   496                             CHECKDEST( sh4r.spc );
   497                             CHECKSLOTILLEGAL();
   498                             sh4r.in_delay_slot = 1;
   499                             sh4r.pc = sh4r.new_pc;
   500                             sh4r.new_pc = sh4r.spc;
   501                             sh4_load_sr( sh4r.ssr );
   502                             return TRUE;
   503                         default:UNDEF(ir);
   504                     }
   505                     break;
   506                 case 12:/* MOV.B   [R0+R%d], R%d */
   507                     RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
   508                     break;
   509                 case 13:/* MOV.W   [R0+R%d], R%d */
   510                     RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
   511                     break;
   512                 case 14:/* MOV.L   [R0+R%d], R%d */
   513                     RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
   514                     break;
   515                 case 15:/* MAC.L   [Rm++], [Rn++] */
   516                     tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
   517                                   SIGNEXT32(MEM_READ_LONG(RN(ir))) );
   518                     if( sh4r.s ) {
   519                         /* 48-bit Saturation. Yuch */
   520                         tmpl += SIGNEXT48(sh4r.mac);
   521                         if( tmpl < 0xFFFF800000000000LL )
   522                             tmpl = 0xFFFF800000000000LL;
   523                         else if( tmpl > 0x00007FFFFFFFFFFFLL )
   524                             tmpl = 0x00007FFFFFFFFFFFLL;
   525                         sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
   526                             (tmpl&0x0000FFFFFFFFFFFFLL);
   527                     } else sh4r.mac = tmpl;
   529                     RM(ir) += 4;
   530                     RN(ir) += 4;
   532                     break;
   533                 default: UNDEF(ir);
   534             }
   535             break;
   536         case 1: /* 0001nnnnmmmmdddd */
   537             /* MOV.L   Rm, [Rn + disp4*4] */
   538             MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) );
   539             break;
   540         case 2: /* 0010nnnnmmmmxxxx */
   541             switch( ir&0x000F ) {
   542                 case 0: /* MOV.B   Rm, [Rn] */
   543                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   544                     break;
   545                 case 1: /* MOV.W   Rm, [Rn] */
   546                     MEM_WRITE_WORD( RN(ir), RM(ir) );
   547                     break;
   548                 case 2: /* MOV.L   Rm, [Rn] */
   549                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   550                     break;
   551                 case 3: UNDEF(ir);
   552                     break;
   553                 case 4: /* MOV.B   Rm, [--Rn] */
   554                     RN(ir) --;
   555                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   556                     break;
   557                 case 5: /* MOV.W   Rm, [--Rn] */
   558                     RN(ir) -= 2;
   559                     MEM_WRITE_WORD( RN(ir), RM(ir) );
   560                     break;
   561                 case 6: /* MOV.L   Rm, [--Rn] */
   562                     RN(ir) -= 4;
   563                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   564                     break;
   565                 case 7: /* DIV0S   Rm, Rn */
   566                     sh4r.q = RN(ir)>>31;
   567                     sh4r.m = RM(ir)>>31;
   568                     sh4r.t = sh4r.q ^ sh4r.m;
   569                     break;
   570                 case 8: /* TST     Rm, Rn */
   571                     sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
   572                     break;
   573                 case 9: /* AND     Rm, Rn */
   574                     RN(ir) &= RM(ir);
   575                     break;
   576                 case 10:/* XOR     Rm, Rn */
   577                     RN(ir) ^= RM(ir);
   578                     break;
   579                 case 11:/* OR      Rm, Rn */
   580                     RN(ir) |= RM(ir);
   581                     break;
   582                 case 12:/* CMP/STR Rm, Rn */
   583                     /* set T = 1 if any byte in RM & RN is the same */
   584                     tmp = RM(ir) ^ RN(ir);
   585                     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   586                               (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   587                     break;
   588                 case 13:/* XTRCT   Rm, Rn */
   589                     RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
   590                     break;
   591                 case 14:/* MULU.W  Rm, Rn */
   592                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   593                         (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
   594                     break;
   595                 case 15:/* MULS.W  Rm, Rn */
   596                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   597                         (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
   598                     break;
   599             }
   600             break;
   601         case 3: /* 0011nnnnmmmmxxxx */
   602             switch( ir&0x000F ) {
   603                 case 0: /* CMP/EQ  Rm, Rn */
   604                     sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
   605                     break;
   606                 case 2: /* CMP/HS  Rm, Rn */
   607                     sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
   608                     break;
   609                 case 3: /* CMP/GE  Rm, Rn */
   610                     sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
   611                     break;
   612                 case 4: { /* DIV1    Rm, Rn */
   613                     /* This is just from the sh4p manual with some
   614                      * simplifications (someone want to check it's correct? :)
   615                      * Why they couldn't just provide a real DIV instruction...
   616                      * Please oh please let the translator batch these things
   617                      * up into a single DIV... */
   618                     uint32_t tmp0, tmp1, tmp2, dir;
   620                     dir = sh4r.q ^ sh4r.m;
   621                     sh4r.q = (RN(ir) >> 31);
   622                     tmp2 = RM(ir);
   623                     RN(ir) = (RN(ir) << 1) | sh4r.t;
   624                     tmp0 = RN(ir);
   625                     if( dir ) {
   626                         RN(ir) += tmp2;
   627                         tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
   628                     } else {
   629                         RN(ir) -= tmp2;
   630                         tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
   631                     }
   632                     sh4r.q ^= sh4r.m ^ tmp1;
   633                     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   634                     break; }
   635                 case 5: /* DMULU.L Rm, Rn */
   636                     sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
   637                     break;
   638                 case 6: /* CMP/HI  Rm, Rn */
   639                     sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
   640                     break;
   641                 case 7: /* CMP/GT  Rm, Rn */
   642                     sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
   643                     break;
   644                 case 8: /* SUB     Rm, Rn */
   645                     RN(ir) -= RM(ir);
   646                     break;
   647                 case 10:/* SUBC    Rm, Rn */
   648                     tmp = RN(ir);
   649                     RN(ir) = RN(ir) - RM(ir) - sh4r.t;
   650                     sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
   651                     break;
   652                 case 11:/* SUBV    Rm, Rn */
   653                     UNIMP(ir);
   654                     break;
   655                 case 12:/* ADD     Rm, Rn */
   656                     RN(ir) += RM(ir);
   657                     break;
   658                 case 13:/* DMULS.L Rm, Rn */
   659                     sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
   660                     break;
   661                 case 14:/* ADDC    Rm, Rn */
   662                     tmp = RN(ir);
   663                     RN(ir) += RM(ir) + sh4r.t;
   664                     sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
   665                     break;
   666                 case 15:/* ADDV    Rm, Rn */
   667                     UNIMP(ir);
   668                     break;
   669                 default: UNDEF(ir);
   670             }
   671             break;
   672         case 4: /* 0100nnnnxxxxxxxx */
   673             switch( ir&0x00FF ) {
   674                 case 0x00: /* SHLL    Rn */
   675                     sh4r.t = RN(ir) >> 31;
   676                     RN(ir) <<= 1;
   677                     break;
   678                 case 0x01: /* SHLR    Rn */
   679                     sh4r.t = RN(ir) & 0x00000001;
   680                     RN(ir) >>= 1;
   681                     break;
   682                 case 0x02: /* STS.L   MACH, [--Rn] */
   683                     RN(ir) -= 4;
   684                     MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
   685                     break;
   686                 case 0x03: /* STC.L   SR, [--Rn] */
   687                     CHECKPRIV();
   688                     RN(ir) -= 4;
   689                     MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
   690                     break;
   691                 case 0x04: /* ROTL    Rn */
   692                     sh4r.t = RN(ir) >> 31;
   693                     RN(ir) <<= 1;
   694                     RN(ir) |= sh4r.t;
   695                     break;
   696                 case 0x05: /* ROTR    Rn */
   697                     sh4r.t = RN(ir) & 0x00000001;
   698                     RN(ir) >>= 1;
   699                     RN(ir) |= (sh4r.t << 31);
   700                     break;
   701                 case 0x06: /* LDS.L   [Rn++], MACH */
   702                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   703                         (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
   704                     RN(ir) += 4;
   705                     break;
   706                 case 0x07: /* LDC.L   [Rn++], SR */
   707                     CHECKPRIV();
   708                     sh4_load_sr( MEM_READ_LONG(RN(ir)) );
   709                     RN(ir) +=4;
   710                     break;
   711                 case 0x08: /* SHLL2   Rn */
   712                     RN(ir) <<= 2;
   713                     break;
   714                 case 0x09: /* SHLR2   Rn */
   715                     RN(ir) >>= 2;
   716                     break;
   717                 case 0x0A: /* LDS     Rn, MACH */
   718                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   719                         (((uint64_t)RN(ir))<<32);
   720                     break;
   721                 case 0x0B: /* JSR     [Rn] */
   722                     CHECKDEST( RN(ir) );
   723                     CHECKSLOTILLEGAL();
   724                     sh4r.in_delay_slot = 1;
   725                     sh4r.pc = sh4r.new_pc;
   726                     sh4r.new_pc = RN(ir);
   727                     sh4r.pr = pc + 4;
   728                     return TRUE;
   729                 case 0x0E: /* LDC     Rn, SR */
   730                     CHECKPRIV();
   731                     sh4_load_sr( RN(ir) );
   732                     break;
   733                 case 0x10: /* DT      Rn */
   734                     RN(ir) --;
   735                     sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
   736                     break;
   737                 case 0x11: /* CMP/PZ  Rn */
   738                     sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
   739                     break;
   740                 case 0x12: /* STS.L   MACL, [--Rn] */
   741                     RN(ir) -= 4;
   742                     MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
   743                     break;
   744                 case 0x13: /* STC.L   GBR, [--Rn] */
   745                     RN(ir) -= 4;
   746                     MEM_WRITE_LONG( RN(ir), sh4r.gbr );
   747                     break;
   748                 case 0x15: /* CMP/PL  Rn */
   749                     sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
   750                     break;
   751                 case 0x16: /* LDS.L   [Rn++], MACL */
   752                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   753                         (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
   754                     RN(ir) += 4;
   755                     break;
   756                 case 0x17: /* LDC.L   [Rn++], GBR */
   757                     sh4r.gbr = MEM_READ_LONG(RN(ir));
   758                     RN(ir) +=4;
   759                     break;
   760                 case 0x18: /* SHLL8   Rn */
   761                     RN(ir) <<= 8;
   762                     break;
   763                 case 0x19: /* SHLR8   Rn */
   764                     RN(ir) >>= 8;
   765                     break;
   766                 case 0x1A: /* LDS     Rn, MACL */
   767                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   768                         (uint64_t)((uint32_t)(RN(ir)));
   769                     break;
   770                 case 0x1B: /* TAS.B   [Rn] */
   771                     tmp = MEM_READ_BYTE( RN(ir) );
   772                     sh4r.t = ( tmp == 0 ? 1 : 0 );
   773                     MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
   774                     break;
   775                 case 0x1E: /* LDC     Rn, GBR */
   776                     sh4r.gbr = RN(ir);
   777                     break;
   778                 case 0x20: /* SHAL    Rn */
   779                     sh4r.t = RN(ir) >> 31;
   780                     RN(ir) <<= 1;
   781                     break;
   782                 case 0x21: /* SHAR    Rn */
   783                     sh4r.t = RN(ir) & 0x00000001;
   784                     RN(ir) = ((int32_t)RN(ir)) >> 1;
   785                     break;
   786                 case 0x22: /* STS.L   PR, [--Rn] */
   787                     RN(ir) -= 4;
   788                     MEM_WRITE_LONG( RN(ir), sh4r.pr );
   789                     break;
   790                 case 0x23: /* STC.L   VBR, [--Rn] */
   791                     CHECKPRIV();
   792                     RN(ir) -= 4;
   793                     MEM_WRITE_LONG( RN(ir), sh4r.vbr );
   794                     break;
   795                 case 0x24: /* ROTCL   Rn */
   796                     tmp = RN(ir) >> 31;
   797                     RN(ir) <<= 1;
   798                     RN(ir) |= sh4r.t;
   799                     sh4r.t = tmp;
   800                     break;
   801                 case 0x25: /* ROTCR   Rn */
   802                     tmp = RN(ir) & 0x00000001;
   803                     RN(ir) >>= 1;
   804                     RN(ir) |= (sh4r.t << 31 );
   805                     sh4r.t = tmp;
   806                     break;
   807                 case 0x26: /* LDS.L   [Rn++], PR */
   808                     sh4r.pr = MEM_READ_LONG( RN(ir) );
   809                     RN(ir) += 4;
   810                     break;
   811                 case 0x27: /* LDC.L   [Rn++], VBR */
   812                     CHECKPRIV();
   813                     sh4r.vbr = MEM_READ_LONG(RN(ir));
   814                     RN(ir) +=4;
   815                     break;
   816                 case 0x28: /* SHLL16  Rn */
   817                     RN(ir) <<= 16;
   818                     break;
   819                 case 0x29: /* SHLR16  Rn */
   820                     RN(ir) >>= 16;
   821                     break;
   822                 case 0x2A: /* LDS     Rn, PR */
   823                     sh4r.pr = RN(ir);
   824                     break;
   825                 case 0x2B: /* JMP     [Rn] */
   826                     CHECKDEST( RN(ir) );
   827                     CHECKSLOTILLEGAL();
   828                     sh4r.in_delay_slot = 1;
   829                     sh4r.pc = sh4r.new_pc;
   830                     sh4r.new_pc = RN(ir);
   831                     return TRUE;
   832                 case 0x2E: /* LDC     Rn, VBR */
   833                     CHECKPRIV();
   834                     sh4r.vbr = RN(ir);
   835                     break;
   836                 case 0x32: /* STC.L   SGR, [--Rn] */
   837                     CHECKPRIV();
   838                     RN(ir) -= 4;
   839                     MEM_WRITE_LONG( RN(ir), sh4r.sgr );
   840                     break;
   841                 case 0x33: /* STC.L   SSR, [--Rn] */
   842                     CHECKPRIV();
   843                     RN(ir) -= 4;
   844                     MEM_WRITE_LONG( RN(ir), sh4r.ssr );
   845                     break;
   846                 case 0x37: /* LDC.L   [Rn++], SSR */
   847                     CHECKPRIV();
   848                     sh4r.ssr = MEM_READ_LONG(RN(ir));
   849                     RN(ir) +=4;
   850                     break;
   851                 case 0x3E: /* LDC     Rn, SSR */
   852                     CHECKPRIV();
   853                     sh4r.ssr = RN(ir);
   854                     break;
   855                 case 0x43: /* STC.L   SPC, [--Rn] */
   856                     CHECKPRIV();
   857                     RN(ir) -= 4;
   858                     MEM_WRITE_LONG( RN(ir), sh4r.spc );
   859                     break;
   860                 case 0x47: /* LDC.L   [Rn++], SPC */
   861                     CHECKPRIV();
   862                     sh4r.spc = MEM_READ_LONG(RN(ir));
   863                     RN(ir) +=4;
   864                     break;
   865                 case 0x4E: /* LDC     Rn, SPC */
   866                     CHECKPRIV();
   867                     sh4r.spc = RN(ir);
   868                     break;
   869                 case 0x52: /* STS.L   FPUL, [--Rn] */
   870                     RN(ir) -= 4;
   871                     MEM_WRITE_LONG( RN(ir), sh4r.fpul );
   872                     break;
   873                 case 0x56: /* LDS.L   [Rn++], FPUL */
   874                     sh4r.fpul = MEM_READ_LONG(RN(ir));
   875                     RN(ir) +=4;
   876                     break;
   877                 case 0x5A: /* LDS     Rn, FPUL */
   878                     sh4r.fpul = RN(ir);
   879                     break;
   880                 case 0x62: /* STS.L   FPSCR, [--Rn] */
   881                     RN(ir) -= 4;
   882                     MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
   883                     break;
   884                 case 0x66: /* LDS.L   [Rn++], FPSCR */
   885                     sh4r.fpscr = MEM_READ_LONG(RN(ir));
   886                     RN(ir) +=4;
   887                     break;
   888                 case 0x6A: /* LDS     Rn, FPSCR */
   889                     sh4r.fpscr = RN(ir);
   890                     break;
   891                 case 0xF2: /* STC.L   DBR, [--Rn] */
   892                     CHECKPRIV();
   893                     RN(ir) -= 4;
   894                     MEM_WRITE_LONG( RN(ir), sh4r.dbr );
   895                     break;
   896                 case 0xF6: /* LDC.L   [Rn++], DBR */
   897                     CHECKPRIV();
   898                     sh4r.dbr = MEM_READ_LONG(RN(ir));
   899                     RN(ir) +=4;
   900                     break;
   901                 case 0xFA: /* LDC     Rn, DBR */
   902                     CHECKPRIV();
   903                     sh4r.dbr = RN(ir);
   904                     break;
   905                 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
   906                 case 0xD3: case 0xE3: case 0xF3: /* STC.L   Rn_BANK, [--Rn] */
   907                     CHECKPRIV();
   908                     RN(ir) -= 4;
   909                     MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
   910                     break;
   911                 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
   912                 case 0xD7: case 0xE7: case 0xF7: /* LDC.L   [Rn++], Rn_BANK */
   913                     CHECKPRIV();
   914                     RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
   915                     RN(ir) += 4;
   916                     break;
   917                 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
   918                 case 0xDE: case 0xEE: case 0xFE: /* LDC     Rm, Rn_BANK */
   919                     CHECKPRIV();
   920                     RN_BANK(ir) = RM(ir);
   921                     break;
   922                 default:
   923                     if( (ir&0x000F) == 0x0F ) {
   924                         /* MAC.W   [Rm++], [Rn++] */
   925                         tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
   926                             SIGNEXT16(MEM_READ_WORD(RN(ir)));
   927                         if( sh4r.s ) {
   928                             /* FIXME */
   929                             UNIMP(ir);
   930                         } else sh4r.mac += SIGNEXT32(tmp);
   931                         RM(ir) += 2;
   932                         RN(ir) += 2;
   933                     } else if( (ir&0x000F) == 0x0C ) {
   934                         /* SHAD    Rm, Rn */
   935                         tmp = RM(ir);
   936                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
   937                         else if( (tmp & 0x1F) == 0 )  
   938 			  RN(ir) = ((int32_t)RN(ir)) >> 31;
   939                         else 
   940 			  RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
   941                     } else if( (ir&0x000F) == 0x0D ) {
   942                         /* SHLD    Rm, Rn */
   943                         tmp = RM(ir);
   944                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
   945                         else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
   946                         else RN(ir) >>= (((~tmp) & 0x1F)+1);
   947                     } else UNDEF(ir);
   948             }
   949             break;
   950         case 5: /* 0101nnnnmmmmdddd */
   951             /* MOV.L   [Rm + disp4*4], Rn */
   952             RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) );
   953             break;
   954         case 6: /* 0110xxxxxxxxxxxx */
   955             switch( ir&0x000f ) {
   956                 case 0: /* MOV.B   [Rm], Rn */
   957                     RN(ir) = MEM_READ_BYTE( RM(ir) );
   958                     break;
   959                 case 1: /* MOV.W   [Rm], Rn */
   960                     RN(ir) = MEM_READ_WORD( RM(ir) );
   961                     break;
   962                 case 2: /* MOV.L   [Rm], Rn */
   963                     RN(ir) = MEM_READ_LONG( RM(ir) );
   964                     break;
   965                 case 3: /* MOV     Rm, Rn */
   966                     RN(ir) = RM(ir);
   967                     break;
   968                 case 4: /* MOV.B   [Rm++], Rn */
   969                     RN(ir) = MEM_READ_BYTE( RM(ir) );
   970                     RM(ir) ++;
   971                     break;
   972                 case 5: /* MOV.W   [Rm++], Rn */
   973                     RN(ir) = MEM_READ_WORD( RM(ir) );
   974                     RM(ir) += 2;
   975                     break;
   976                 case 6: /* MOV.L   [Rm++], Rn */
   977                     RN(ir) = MEM_READ_LONG( RM(ir) );
   978                     RM(ir) += 4;
   979                     break;
   980                 case 7: /* NOT     Rm, Rn */
   981                     RN(ir) = ~RM(ir);
   982                     break;
   983                 case 8: /* SWAP.B  Rm, Rn */
   984                     RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
   985                         ((RM(ir)&0x000000FF)<<8);
   986                     break;
   987                 case 9: /* SWAP.W  Rm, Rn */
   988                     RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
   989                     break;
   990                 case 10:/* NEGC    Rm, Rn */
   991                     tmp = 0 - RM(ir);
   992                     RN(ir) = tmp - sh4r.t;
   993                     sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
   994                     break;
   995                 case 11:/* NEG     Rm, Rn */
   996                     RN(ir) = 0 - RM(ir);
   997                     break;
   998                 case 12:/* EXTU.B  Rm, Rn */
   999                     RN(ir) = RM(ir)&0x000000FF;
  1000                     break;
  1001                 case 13:/* EXTU.W  Rm, Rn */
  1002                     RN(ir) = RM(ir)&0x0000FFFF;
  1003                     break;
  1004                 case 14:/* EXTS.B  Rm, Rn */
  1005                     RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
  1006                     break;
  1007                 case 15:/* EXTS.W  Rm, Rn */
  1008                     RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
  1009                     break;
  1011             break;
  1012         case 7: /* 0111nnnniiiiiiii */
  1013             /* ADD    imm8, Rn */
  1014             RN(ir) += IMM8(ir);
  1015             break;
  1016         case 8: /* 1000xxxxxxxxxxxx */
  1017             switch( (ir&0x0F00) >> 8 ) {
  1018                 case 0: /* MOV.B   R0, [Rm + disp4] */
  1019                     MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
  1020                     break;
  1021                 case 1: /* MOV.W   R0, [Rm + disp4*2] */
  1022                     MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 );
  1023                     break;
  1024                 case 4: /* MOV.B   [Rm + disp4], R0 */
  1025                     R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
  1026                     break;
  1027                 case 5: /* MOV.W   [Rm + disp4*2], R0 */
  1028                     R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) );
  1029                     break;
  1030                 case 8: /* CMP/EQ  imm, R0 */
  1031                     sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
  1032                     break;
  1033                 case 9: /* BT      disp8 */
  1034                     CHECKSLOTILLEGAL()
  1035                     if( sh4r.t ) {
  1036                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1037                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
  1038                         sh4r.new_pc = sh4r.pc + 2;
  1039                         return TRUE;
  1041                     break;
  1042                 case 11:/* BF      disp8 */
  1043                     CHECKSLOTILLEGAL()
  1044                     if( !sh4r.t ) {
  1045                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1046                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
  1047                         sh4r.new_pc = sh4r.pc + 2;
  1048                         return TRUE;
  1050                     break;
  1051                 case 13:/* BT/S    disp8 */
  1052                     CHECKSLOTILLEGAL()
  1053                     if( sh4r.t ) {
  1054                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1055                         sh4r.in_delay_slot = 1;
  1056                         sh4r.pc = sh4r.new_pc;
  1057                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
  1058                         sh4r.in_delay_slot = 1;
  1059                         return TRUE;
  1061                     break;
  1062                 case 15:/* BF/S    disp8 */
  1063                     CHECKSLOTILLEGAL()
  1064                     if( !sh4r.t ) {
  1065                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1066                         sh4r.in_delay_slot = 1;
  1067                         sh4r.pc = sh4r.new_pc;
  1068                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
  1069                         return TRUE;
  1071                     break;
  1072                 default: UNDEF(ir);
  1074             break;
  1075         case 9: /* 1001xxxxxxxxxxxx */
  1076             /* MOV.W   [disp8*2 + pc + 4], Rn */
  1077             RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) );
  1078             break;
  1079         case 10:/* 1010dddddddddddd */
  1080             /* BRA     disp12 */
  1081             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
  1082             CHECKSLOTILLEGAL()
  1083             sh4r.in_delay_slot = 1;
  1084             sh4r.pc = sh4r.new_pc;
  1085             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
  1086             return TRUE;
  1087         case 11:/* 1011dddddddddddd */
  1088             /* BSR     disp12 */
  1089             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
  1090             CHECKSLOTILLEGAL()
  1091             sh4r.in_delay_slot = 1;
  1092             sh4r.pr = pc + 4;
  1093             sh4r.pc = sh4r.new_pc;
  1094             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
  1095             return TRUE;
  1096         case 12:/* 1100xxxxdddddddd */
  1097         switch( (ir&0x0F00)>>8 ) {
  1098                 case 0: /* MOV.B  R0, [GBR + disp8] */
  1099                     MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
  1100                     break;
  1101                 case 1: /* MOV.W  R0, [GBR + disp8*2] */
  1102                     MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 );
  1103                     break;
  1104                 case  2: /*MOV.L   R0, [GBR + disp8*4] */
  1105                     MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 );
  1106                     break;
  1107                 case 3: /* TRAPA   imm8 */
  1108                     CHECKSLOTILLEGAL()
  1109                     sh4r.in_delay_slot = 1;
  1110                     MMIO_WRITE( MMU, TRA, UIMM8(ir) );
  1111                     sh4r.pc = sh4r.new_pc;  /* RAISE ends the instruction */
  1112                     sh4r.new_pc += 2;
  1113                     RAISE( EXC_TRAP, EXV_TRAP );
  1114                     break;
  1115                 case 4: /* MOV.B   [GBR + disp8], R0 */
  1116                     R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
  1117                     break;
  1118                 case 5: /* MOV.W   [GBR + disp8*2], R0 */
  1119                     R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) );
  1120                     break;
  1121                 case 6: /* MOV.L   [GBR + disp8*4], R0 */
  1122                     R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) );
  1123                     break;
  1124                 case 7: /* MOVA    disp8 + pc&~3 + 4, R0 */
  1125                     R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
  1126                     break;
  1127                 case 8: /* TST     imm8, R0 */
  1128                     sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
  1129                     break;
  1130                 case 9: /* AND     imm8, R0 */
  1131                     R0 &= UIMM8(ir);
  1132                     break;
  1133                 case 10:/* XOR     imm8, R0 */
  1134                     R0 ^= UIMM8(ir);
  1135                     break;
  1136                 case 11:/* OR      imm8, R0 */
  1137                     R0 |= UIMM8(ir);
  1138                     break;
  1139                 case 12:/* TST.B   imm8, [R0+GBR] */
  1140                     sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
  1141                     break;
  1142                 case 13:/* AND.B   imm8, [R0+GBR] */
  1143                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1144                                     UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
  1145                     break;
  1146                 case 14:/* XOR.B   imm8, [R0+GBR] */
  1147                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1148                                     UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
  1149                     break;
  1150                 case 15:/* OR.B    imm8, [R0+GBR] */
  1151                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1152                                     UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
  1153                     break;
  1155             break;
  1156         case 13:/* 1101nnnndddddddd */
  1157             /* MOV.L   [disp8*4 + pc&~3 + 4], Rn */
  1158             RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 );
  1159             break;
  1160         case 14:/* 1110nnnniiiiiiii */
  1161             /* MOV     imm8, Rn */
  1162             RN(ir) = IMM8(ir);
  1163             break;
  1164         case 15:/* 1111xxxxxxxxxxxx */
  1165             CHECKFPUEN();
  1166             switch( ir&0x000F ) {
  1167                 case 0: /* FADD    FRm, FRn */
  1168                     FRN(ir) += FRM(ir);
  1169                     break;
  1170                 case 1: /* FSUB    FRm, FRn */
  1171                     FRN(ir) -= FRM(ir);
  1172                     break;
  1173                 case 2: /* FMUL    FRm, FRn */
  1174                     FRN(ir) = FRN(ir) * FRM(ir);
  1175                     break;
  1176                 case 3: /* FDIV    FRm, FRn */
  1177                     FRN(ir) = FRN(ir) / FRM(ir);
  1178                     break;
  1179                 case 4: /* FCMP/EQ FRm, FRn */
  1180                     sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
  1181                     break;
  1182                 case 5: /* FCMP/GT FRm, FRn */
  1183                     sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
  1184                     break;
  1185                 case 6: /* FMOV.S  [Rm+R0], FRn */
  1186                     MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
  1187                     break;
  1188                 case 7: /* FMOV.S  FRm, [Rn+R0] */
  1189                     MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
  1190                     break;
  1191                 case 8: /* FMOV.S  [Rm], FRn */
  1192                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1193                     break;
  1194                 case 9: /* FMOV.S  [Rm++], FRn */
  1195                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1196                     RM(ir) += FP_WIDTH;
  1197                     break;
  1198                 case 10:/* FMOV.S  FRm, [Rn] */
  1199                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1200                     break;
  1201                 case 11:/* FMOV.S  FRm, [--Rn] */
  1202                     RN(ir) -= FP_WIDTH;
  1203                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1204                     break;
  1205                 case 12:/* FMOV    FRm, FRn */
  1206                     if( IS_FPU_DOUBLESIZE() ) {
  1207                         DRN(ir) = DRM(ir);
  1208                     } else {
  1209                         FRN(ir) = FRM(ir);
  1211                     break;
  1212                 case 13:
  1213                     switch( (ir&0x00F0) >> 4 ) {
  1214                         case 0: /* FSTS    FPUL, FRn */
  1215                             FRN(ir) = FPULf;
  1216                             break;
  1217                         case 1: /* FLDS    FRn, FPUL */
  1218                             FPULf = FRN(ir);
  1219                             break;
  1220                         case 2: /* FLOAT   FPUL, FRn */
  1221                             FRN(ir) = (float)FPULi;
  1222                             break;
  1223                         case 3: /* FTRC    FRn, FPUL */
  1224                             FPULi = (uint32_t)FRN(ir);
  1225                             /* FIXME: is this sufficient? */
  1226                             break;
  1227                         case 4: /* FNEG    FRn */
  1228                             FRN(ir) = -FRN(ir);
  1229                             break;
  1230                         case 5: /* FABS    FRn */
  1231                             FRN(ir) = fabsf(FRN(ir));
  1232                             break;
  1233                         case 6: /* FSQRT   FRn */
  1234                             FRN(ir) = sqrtf(FRN(ir));
  1235                             break;
  1236                         case 7: /* FSRRA FRn */
  1237                             FRN(ir) = 1.0/sqrtf(FRN(ir));
  1238                             break;
  1239                         case 8: /* FLDI0   FRn */
  1240                             FRN(ir) = 0.0;
  1241                             break;
  1242                         case 9: /* FLDI1   FRn */
  1243                             FRN(ir) = 1.0;
  1244                             break;
  1245                         case 10: /* FCNVSD FPUL, DRn */
  1246                             if( IS_FPU_DOUBLEPREC() )
  1247                                 DRN(ir) = (double)FPULf;
  1248                             else UNDEF(ir);
  1249                             break;
  1250                         case 11: /* FCNVDS DRn, FPUL */
  1251                             if( IS_FPU_DOUBLEPREC() ) 
  1252                                 FPULf = (float)DRN(ir);
  1253                             else UNDEF(ir);
  1254                             break;
  1255                         case 14:/* FIPR    FVm, FVn */
  1256                             /* FIXME: This is not going to be entirely accurate
  1257                              * as the SH4 instruction is less precise. Also
  1258                              * need to check for 0s and infinities.
  1259                              */
  1261                             float *fr_bank = FR;
  1262                             int tmp2 = FVN(ir);
  1263                             tmp = FVM(ir);
  1264                             fr_bank[tmp2+3] = fr_bank[tmp]*fr_bank[tmp2] +
  1265                                 fr_bank[tmp+1]*fr_bank[tmp2+1] +
  1266                                 fr_bank[tmp+2]*fr_bank[tmp2+2] +
  1267                                 fr_bank[tmp+3]*fr_bank[tmp2+3];
  1268                             break;
  1270                         case 15:
  1271                             if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
  1272                                 float *fvout = FR+FVN(ir);
  1273                                 float *xm = XF;
  1274                                 float fv[4] = { fvout[0], fvout[1], fvout[2], fvout[3] };
  1275                                 fvout[0] = xm[0] * fv[0] + xm[4]*fv[1] +
  1276                                     xm[8]*fv[2] + xm[12]*fv[3];
  1277                                 fvout[1] = xm[1] * fv[0] + xm[5]*fv[1] +
  1278                                     xm[9]*fv[2] + xm[13]*fv[3];
  1279                                 fvout[2] = xm[2] * fv[0] + xm[6]*fv[1] +
  1280                                     xm[10]*fv[2] + xm[14]*fv[3];
  1281                                 fvout[3] = xm[3] * fv[0] + xm[7]*fv[1] +
  1282                                     xm[11]*fv[2] + xm[15]*fv[3];
  1283                                 break;
  1285                             else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */
  1286                                 float angle = (((float)(short)(FPULi>>16)) +
  1287                                                ((float)(FPULi&16)/65536.0)) *
  1288                                     2 * M_PI;
  1289                                 int reg = FRNn(ir);
  1290                                 FR[reg] = sinf(angle);
  1291                                 FR[reg+1] = cosf(angle);
  1292                                 break;
  1294                             else if( ir == 0xFBFD ) {
  1295                                 /* FRCHG   */
  1296                                 sh4r.fpscr ^= FPSCR_FR;
  1297                                 break;
  1299                             else if( ir == 0xF3FD ) {
  1300                                 /* FSCHG   */
  1301                                 sh4r.fpscr ^= FPSCR_SZ;
  1302                                 break;
  1304                         default: UNDEF(ir);
  1306                     break;
  1307                 case 14:/* FMAC    FR0, FRm, FRn */
  1308                     FRN(ir) += FRM(ir)*FR0;
  1309                     break;
  1310                 default: UNDEF(ir);
  1312             break;
  1314     sh4r.pc = sh4r.new_pc;
  1315     sh4r.new_pc += 2;
  1316     sh4r.in_delay_slot = 0;
.