Search
lxdream.org :: lxdream/src/sh4/sh4mmio.h
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/sh4mmio.h
changeset 736:a02d1475ccfd
prev561:533f6b478071
next817:e9d2d9be7cb6
author nkeynes
date Mon Aug 04 06:00:11 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Fix x86-64 bugs (only visible on OS X)
view annotate diff log raw
     1 /**
     2  * $Id$
     3  * 
     4  * MMIO region and supporting function declarations. Private to the sh4
     5  * module.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #include "lxdream.h"
    21 #include "mmio.h"
    23 #if (defined(MMIO_IMPL) && !defined(SH4MMIO_IMPL)) || \
    24     (!defined(MMIO_IMPL) && !defined(SH4MMIO_IFACE))
    26 #ifdef __cplusplus
    27 extern "C" {
    28 #endif
    30 #ifdef MMIO_IMPL
    31 #define SH4MMIO_IMPL
    32 #else
    33 #define SH4MMIO_IFACE
    34 #endif
    35 /* SH7750 onchip mmio devices */
    37 MMIO_REGION_BEGIN( 0xFF000000, MMU, "MMU Registers" )
    38     LONG_PORT( 0x000, PTEH, PORT_MRW, UNDEFINED, "Page table entry high" )
    39     LONG_PORT( 0x004, PTEL, PORT_MRW, UNDEFINED, "Page table entry low" )
    40     LONG_PORT( 0x008, TTB,  PORT_MRW, UNDEFINED, "Translation table base" )
    41     LONG_PORT( 0x00C, TEA,  PORT_MRW, UNDEFINED, "TLB exception address" )
    42     LONG_PORT( 0x010, MMUCR,PORT_MRW, 0, "MMU control register" )
    43     BYTE_PORT( 0x014, BASRA, PORT_MRW, UNDEFINED, "Break ASID A" ) /* UBC */
    44     BYTE_PORT( 0x018, BASRB, PORT_MRW, UNDEFINED, "Break ASID B" ) /* UBC */
    45     LONG_PORT( 0x01C, CCR,  PORT_MRW, 0, "Cache control register" )
    46     LONG_PORT( 0x020, TRA,  PORT_MRW, UNDEFINED, "TRAPA exception register" )
    47     LONG_PORT( 0x024, EXPEVT,PORT_MRW, 0, "Exception event register" )
    48     LONG_PORT( 0x028, INTEVT,PORT_MRW, UNDEFINED, "Interrupt event register" )
    49     LONG_PORT( 0x034, PTEA, PORT_MRW, UNDEFINED, "Page table entry assistance" )
    50     LONG_PORT( 0x038, QACR0,PORT_MRW, UNDEFINED, "Queue address control 0" )
    51     LONG_PORT( 0x03C, QACR1,PORT_MRW, UNDEFINED, "Queue address control 1" )
    52 MMIO_REGION_END
    54 /* User Break Controller (Page 717 [757] of sh7750h manual) */
    55 MMIO_REGION_BEGIN( 0xFF200000, UBC, "User Break Controller" )
    56     LONG_PORT( 0x000, BARA, PORT_MRW, UNDEFINED, "Break address A" )
    57     BYTE_PORT( 0x004, BAMRA, PORT_MRW, UNDEFINED, "Break address mask A" )
    58     WORD_PORT( 0x008, BBRA, PORT_MRW, 0, "Break bus cycle A" )
    59     LONG_PORT( 0x00C, BARB, PORT_MRW, UNDEFINED, "Break address B" )
    60     BYTE_PORT( 0x010, BAMRB, PORT_MRW, UNDEFINED, "Break address mask B" )
    61     WORD_PORT( 0x014, BBRB, PORT_MRW, 0, "Break bus cycle B" )
    62     LONG_PORT( 0x018, BDRB, PORT_MRW, UNDEFINED, "Break data B" )
    63     LONG_PORT( 0x01C, BDMRB, PORT_MRW, UNDEFINED, "Break data mask B" )
    64     WORD_PORT( 0x020, BRCR, PORT_MRW, 0, "Break control" )
    65 MMIO_REGION_END
    66 /* Bus State Controller (Page 293 [333] of sh7750h manual)
    67  * I/O Ports */
    68 MMIO_REGION_BEGIN( 0xFF800000, BSC, "Bus State Controller" )
    69     LONG_PORT( 0x000, BCR1, PORT_MRW, 0, "Bus control 1" )
    70     WORD_PORT( 0x004, BCR2, PORT_MRW, 0x3FFC, "Bus control 2" )
    71     LONG_PORT( 0x008, WCR1, PORT_MRW, 0x77777777, "Wait state control 1" )
    72     LONG_PORT( 0x00C, WCR2, PORT_MRW, 0xFFFEEFFF, "Wait state control 2" )
    73     LONG_PORT( 0x010, WCR3, PORT_MRW, 0x07777777, "Wait state control 3" )
    74     LONG_PORT( 0x014, MCR, PORT_MRW, 0, "Memory control register" )
    75     WORD_PORT( 0x018, PCR, PORT_MRW, 0, "PCMCIA control register" )
    76     WORD_PORT( 0x01C, RTCSR, PORT_MRW, 0, "Refresh timer control/status" )
    77     WORD_PORT( 0x020, RTCNT, PORT_MRW, 0, "Refresh timer counter" )
    78     WORD_PORT( 0x024, RTCOR, PORT_MRW, 0, "Refresh timer constant" )
    79     WORD_PORT( 0x028, RFCR, PORT_MRW, 0, "Refresh count" )
    80     LONG_PORT( 0x02C, PCTRA, PORT_MRW, 0, "Port control register A" )
    81     WORD_PORT( 0x030, PDTRA, PORT_RW, UNDEFINED, "Port data register A" )
    82     LONG_PORT( 0x040, PCTRB, PORT_MRW, 0, "Port control register B" )
    83     WORD_PORT( 0x044, PDTRB, PORT_RW, UNDEFINED, "Port data register B" )
    84     WORD_PORT( 0x048, GPIOIC, PORT_MRW, 0, "GPIO interrupt control register" )
    85 MMIO_REGION_END
    87 /* DMA Controller (Page 457 [497] of sh7750h manual) */
    88 MMIO_REGION_BEGIN( 0xFFA00000, DMAC, "DMA Controller" )
    89     LONG_PORT( 0x000, SAR0, PORT_MRW, UNDEFINED, "DMA source address 0" )
    90     LONG_PORT( 0x004, DAR0, PORT_MRW, UNDEFINED, "DMA destination address 0" )
    91     LONG_PORT( 0x008, DMATCR0, PORT_MRW, UNDEFINED, "DMA transfer count 0" )
    92     LONG_PORT( 0x00C, CHCR0, PORT_MRW, 0, "DMA channel control 0" )
    93     LONG_PORT( 0x010, SAR1, PORT_MRW, UNDEFINED, "DMA source address 1" )
    94     LONG_PORT( 0x014, DAR1, PORT_MRW, UNDEFINED, "DMA destination address 1" )
    95     LONG_PORT( 0x018, DMATCR1, PORT_MRW, UNDEFINED, "DMA transfer count 1" )
    96     LONG_PORT( 0x01C, CHCR1, PORT_MRW, 0, "DMA channel control 1" )
    97     LONG_PORT( 0x020, SAR2, PORT_MRW, UNDEFINED, "DMA source address 2" )
    98     LONG_PORT( 0x024, DAR2, PORT_MRW, UNDEFINED, "DMA destination address 2" )
    99     LONG_PORT( 0x028, DMATCR2, PORT_MRW, UNDEFINED, "DMA transfer count 2" )
   100     LONG_PORT( 0x02C, CHCR2, PORT_MRW, 0, "DMA channel control 2" )
   101     LONG_PORT( 0x030, SAR3, PORT_MRW, UNDEFINED, "DMA source address 3" )
   102     LONG_PORT( 0x034, DAR3, PORT_MRW, UNDEFINED, "DMA destination address 3" )
   103     LONG_PORT( 0x038, DMATCR3, PORT_MRW, UNDEFINED, "DMA transfer count 3" )
   104     LONG_PORT( 0x03C, CHCR3, PORT_MRW, 0, "DMA channel control 3" )
   105     LONG_PORT( 0x040, DMAOR, PORT_MRW, 0, "DMA operation register" )
   106 MMIO_REGION_END
   108 /* Clock Pulse Generator (page 233 [273] of sh7750h manual) */
   109 MMIO_REGION_BEGIN( 0xFFC00000, CPG, "Clock Pulse Generator" )
   110     WORD_PORT( 0x000, FRQCR, PORT_MRW, UNDEFINED, "Frequency control" )
   111     BYTE_PORT( 0x004, STBCR, PORT_MRW, 0, "Standby control" )
   112     BYTE_PORT( 0x008, WTCNT, PORT_MRW, 0, "Watchdog timer counter" )
   113     BYTE_PORT( 0x00C, WTCSR, PORT_MRW, 0, "Watchdog timer control/status" )
   114     BYTE_PORT( 0x010, STBCR2, PORT_MRW, 0, "Standby control 2" )
   115 MMIO_REGION_END
   117 /* Real time clock (Page 253 [293] of sh7750h manual) */
   118 MMIO_REGION_BEGIN( 0xFFC80000, RTC, "Realtime Clock" )
   119     BYTE_PORT( 0x000, R64CNT, PORT_R, UNDEFINED, "64 Hz counter" )
   120     BYTE_PORT( 0x004, RSECCNT, PORT_MRW, UNDEFINED, "Second counter" )
   121     /* ... */
   122 MMIO_REGION_END
   124 /* Interrupt controller (Page 699 [739] of sh7750h manual) */
   125 MMIO_REGION_BEGIN( 0xFFD00000, INTC, "Interrupt Controller" )
   126     WORD_PORT( 0x000, ICR, PORT_MRW, 0x0000, "Interrupt control register" )
   127     WORD_PORT( 0x004, IPRA, PORT_MRW, 0x0000, "Interrupt priority register A" )
   128     WORD_PORT( 0x008, IPRB, PORT_MRW, 0x0000, "Interrupt priority register B" )
   129     WORD_PORT( 0x00C, IPRC, PORT_MRW, 0x0000, "Interrupt priority register C" )
   130     WORD_PORT( 0x010, IPRD, PORT_MRW, 0xDA74, "Interrupt priority register D" )
   131 MMIO_REGION_END
   133 /* Timer unit (Page 277 [317] of sh7750h manual) */
   134 MMIO_REGION_BEGIN( 0xFFD80000, TMU, "Timer Unit" )
   135     BYTE_PORT( 0x000, TOCR, PORT_MRW, 0x00, "Timer output control register" )
   136     BYTE_PORT( 0x004, TSTR, PORT_MRW, 0x00, "Timer start register" )
   137     LONG_PORT( 0x008, TCOR0, PORT_MRW, 0xFFFFFFFF, "Timer constant 0" )
   138     LONG_PORT( 0x00C, TCNT0, PORT_MRW, 0xFFFFFFFF, "Timer counter 0" )
   139     WORD_PORT( 0x010, TCR0, PORT_MRW, 0x0000, "Timer control 0" )
   140     LONG_PORT( 0x014, TCOR1, PORT_MRW, 0xFFFFFFFF, "Timer constant 1" )
   141     LONG_PORT( 0x018, TCNT1, PORT_MRW, 0xFFFFFFFF, "Timer counter 1" )
   142     WORD_PORT( 0x01C, TCR1, PORT_MRW, 0x0000, "Timer control 1" )
   143     LONG_PORT( 0x020, TCOR2, PORT_MRW, 0xFFFFFFFF, "Timer constant 2" )
   144     LONG_PORT( 0x024, TCNT2, PORT_MRW, 0xFFFFFFFF, "Timer counter 2" )
   145     WORD_PORT( 0x028, TCR2, PORT_MRW, 0x0000, "Timer control 2" )
   146     LONG_PORT( 0x02C, TCPR2, PORT_R, UNDEFINED, "Input capture register" )
   147 MMIO_REGION_END
   149 /* Serial channel (page 541 [581] of sh7750h manual) */
   150 MMIO_REGION_BEGIN( 0xFFE00000, SCI, "Serial Communication Interface" )
   151     BYTE_PORT( 0x000, SCSMR1, PORT_MRW, 0x00, "Serial mode register" )
   152     BYTE_PORT( 0x004, SCBRR1, PORT_MRW, 0xFF, "Bit rate register" )
   153     BYTE_PORT( 0x008, SCSCR1, PORT_MRW, 0x00, "Serial control register" )
   154     BYTE_PORT( 0x00C, SCTDR1, PORT_MRW, 0xFF, "Transmit data register" )
   155     BYTE_PORT( 0x010, SCSSR1, PORT_MRW, 0x84, "Serial status register" )
   156     BYTE_PORT( 0x014, SCRDR1, PORT_R, 0x00, "Receive data register" )
   157     BYTE_PORT( 0x01C, SCSPTR1, PORT_MRW, 0x00, "Serial port register" )
   158 MMIO_REGION_END
   160 MMIO_REGION_BEGIN( 0xFFE80000, SCIF, "Serial Controller (FIFO) Registers" )
   161     WORD_PORT( 0x000, SCSMR2, PORT_MRW, 0x0000, "Serial mode register (FIFO)" )
   162     BYTE_PORT( 0x004, SCBRR2, PORT_MRW, 0xFF, "Bit rate register (FIFO)" )
   163     WORD_PORT( 0x008, SCSCR2, PORT_MRW, 0x0000, "Serial control register" )
   164     BYTE_PORT( 0x00C, SCFTDR2, PORT_W, UNDEFINED, "Transmit FIFO data register" )
   165     WORD_PORT( 0x010, SCFSR2, PORT_MRW, 0x0060, "Serial status register (FIFO)") 
   166     BYTE_PORT( 0x014, SCFRDR2, PORT_R, UNDEFINED, "Receive FIFO data register" )
   167     WORD_PORT( 0x018, SCFCR2, PORT_MRW, 0x0000, "FIFO control register" )
   168     WORD_PORT( 0x01C, SCFDR2, PORT_MR, 0x0000, "FIFO data count register" )
   169     WORD_PORT( 0x020, SCSPTR2, PORT_MRW, 0x0000, "Serial port register (FIFO)" )
   170     WORD_PORT( 0x024, SCLSR2, PORT_MRW, 0x0000, "Line status register (FIFO)" )
   171 MMIO_REGION_END
   173 MMIO_REGION_LIST_BEGIN( sh4mmio )
   174     MMIO_REGION( MMU )
   175     MMIO_REGION( UBC )
   176     MMIO_REGION( BSC )
   177     MMIO_REGION( DMAC )
   178     MMIO_REGION( CPG )
   179     MMIO_REGION( RTC )
   180     MMIO_REGION( INTC )
   181     MMIO_REGION( TMU )
   182     MMIO_REGION( SCI )
   183     MMIO_REGION( SCIF )
   184 MMIO_REGION_LIST_END
   186 /* mmucr register bits */
   187 #define MMUCR_AT   0x00000001 /* Address Translation enabled */
   188 #define MMUCR_TI   0x00000004 /* TLB invalidate (always read as 0) */
   189 #define MMUCR_SV   0x00000100 /* Single Virtual mode=1 / multiple virtual=0 */
   190 #define MMUCR_SQMD 0x00000200 /* Store queue mode bit (0=user, 1=priv only) */
   191 #define MMUCR_URC  0x0000FC00 /* UTLB access counter */
   192 #define MMUCR_URB  0x00FC0000 /* UTLB entry boundary */
   193 #define MMUCR_LRUI 0xFC000000 /* Least recently used ITLB */
   194 #define MMUCR_MASK 0xFCFCFF05
   195 #define MMUCR_RMASK 0xFCFCFF01 /* Read mask */
   197 #define IS_MMU_ENABLED() (MMIO_READ(MMU, MMUCR)&MMUCR_AT)
   199 /* ccr register bits */
   200 #define CCR_IIX    0x00008000 /* IC index enable */
   201 #define CCR_ICI    0x00000800 /* IC invalidation (always read as 0) */
   202 #define CCR_ICE    0x00000100 /* IC enable */
   203 #define CCR_OIX    0x00000080 /* OC index enable */
   204 #define CCR_ORA    0x00000020 /* OC RAM enable */
   205 #define CCR_OCI    0x00000008 /* OC invalidation (always read as 0) */
   206 #define CCR_CB     0x00000004 /* Copy-back (P1 area cache write mode) */
   207 #define CCR_WT     0x00000002 /* Write-through (P0,U0,P3 write mode) */
   208 #define CCR_OCE    0x00000001 /* OC enable */
   209 #define CCR_MASK   0x000089AF
   210 #define CCR_RMASK  0x000081A7 /* Read mask */
   212 #define MEM_OC_DISABLED 0
   213 #define MEM_OC_INDEX0   CCR_ORA
   214 #define MEM_OC_INDEX1   CCR_ORA|CCR_OIX
   216 /* MMU functions */
   217 void mmu_init(void);
   218 void mmu_set_cache_mode( int );
   219 void mmu_ldtlb(void);
   221 int32_t mmu_icache_addr_read( sh4addr_t addr );
   222 int32_t mmu_icache_data_read( sh4addr_t addr );
   223 int32_t mmu_itlb_addr_read( sh4addr_t addr );
   224 int32_t mmu_itlb_data_read( sh4addr_t addr );
   225 int32_t mmu_ocache_addr_read( sh4addr_t addr );
   226 int32_t mmu_ocache_data_read( sh4addr_t addr );
   227 int32_t mmu_utlb_addr_read( sh4addr_t addr );
   228 int32_t mmu_utlb_data_read( sh4addr_t addr );
   229 void mmu_icache_addr_write( sh4addr_t addr, uint32_t val );
   230 void mmu_icache_data_write( sh4addr_t addr, uint32_t val );
   231 void mmu_itlb_addr_write( sh4addr_t addr, uint32_t val );
   232 void mmu_itlb_data_write( sh4addr_t addr, uint32_t val );
   233 void mmu_ocache_addr_write( sh4addr_t addr, uint32_t val );
   234 void mmu_ocache_data_write( sh4addr_t addr, uint32_t val );
   235 void mmu_utlb_addr_write( sh4addr_t addr, uint32_t val );
   236 void mmu_utlb_data_write( sh4addr_t addr, uint32_t val );
   239 #ifdef __cplusplus
   240 }
   241 #endif
   243 #endif
.