6 * Copyright (c) 2006 Nathan Keynes.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
22 #define DMA_BASE 0xFFA00000
24 #define DMA_SAR(c) (DMA_BASE+0x00+(c<<4))
25 #define DMA_DAR(c) (DMA_BASE+0x04+(c<<4))
26 #define DMA_TCR(c) (DMA_BASE+0x08+(c<<4))
27 #define DMA_CHCR(c) (DMA_BASE+0x0C+(c<<4))
28 #define DMA_OR (DMA_BASE+0x40)
30 #define ASIC_BASE 0xA05F6000
31 #define PVR_DMA_DEST (ASIC_BASE+0x800)
32 #define PVR_DMA_COUNT (ASIC_BASE+0x804)
33 #define PVR_DMA_CTL (ASIC_BASE+0x808)
34 #define PVR_DMA_REGION (ASIC_BASE+0x884)
36 #define SORT_DMA_TABLE (ASIC_BASE+0x810)
37 #define SORT_DMA_DATA (ASIC_BASE+0x814)
38 #define SORT_DMA_TABLEBITS (ASIC_BASE+0x818)
39 #define SORT_DMA_DATASIZE (ASIC_BASE+0x81C)
40 #define SORT_DMA_CTL (ASIC_BASE+0x820)
41 #define SORT_DMA_COUNT (ASIC_BASE+0x860)
43 void dmac_dump_channel( FILE *f, unsigned int channel )
45 fprintf( f, "DMAC SAR: %08X Count: %08X Ctl: %08X OR: %08X\n",
46 long_read(DMA_SAR(channel)), long_read(DMA_TCR(channel)),
47 long_read(DMA_CHCR(channel)), long_read(DMA_OR) );
52 * Setup the DMAC for a transfer. Assumes 32-byte block transfer.
53 * Caller is responsible for making sure no-one else is using the
56 * @param channel DMA channel to use, 0 to 3
57 * @param source source address (if a memory source)
58 * @param dest destination address (if a memory destination)
59 * @param length number of bytes to transfer (must be a multiple of
61 * @param direction 0 = host to device, 1 = device to host
63 void dmac_prepare_channel( int channel, uint32_t source, uint32_t dest,
64 uint32_t length, int direction )
68 if( direction == 0 ) {
69 /* DMA Disabled, IRQ disabled, 32 byte transfer, burst mode,
70 * Memory => Device, Source addr increment, dest addr fixed
74 /* DMA Disabled, IRQ disabled, 32 byte transfer, burst mode,
75 * Device => Memory, Source addr fixed, dest addr increment
79 long_write( DMA_CHCR(channel), control );
80 long_write( DMA_SAR(channel), source );
81 long_write( DMA_DAR(channel), dest );
82 long_write( DMA_TCR(channel), (length >> 5) );
84 long_write( DMA_CHCR(channel), control ); /* Enable DMA channel */
85 long_write( DMA_OR, 0x8201 ); /* Ensure the DMAC config is set */
89 int pvr_dma_write( unsigned int target, char *buf, int len, int region )
91 uint32_t addr =(uint32_t)buf;
93 if( (addr & 0xFFFFFFE0) != addr ) {
94 fprintf( stderr, "Address error: Attempting DMA from %08X\n", addr );
97 long_write( PVR_DMA_CTL, 0 ); /* Stop PVR dma if it's already running */
100 dmac_prepare_channel( 2, (uint32_t)buf, 0, len, 0 ); /* Allocate channel 2 */
101 long_write( PVR_DMA_DEST, target );
102 long_write( PVR_DMA_COUNT, len );
103 long_write( PVR_DMA_REGION, region );
105 CHECK_IEQUALS( target, long_read(PVR_DMA_DEST) );
106 CHECK_IEQUALS( len, long_read(PVR_DMA_COUNT) );
107 CHECK_IEQUALS( 0, long_read(PVR_DMA_REGION) );
108 CHECK_IEQUALS( (uint32_t)buf, long_read(DMA_SAR(2)) );
109 CHECK_IEQUALS( len/32, long_read(DMA_TCR(2)) );
110 CHECK_IEQUALS( 0x12C1, long_read(DMA_CHCR(2)) );
112 long_write( PVR_DMA_CTL, 1 );
113 result = asic_wait(EVENT_PVR_DMA);
116 fprintf( stderr, "PVR DMA failed (timeout)\n" );
118 fprintf( stderr, "Dest: %08X Count: %08X Ctl: %08X\n", long_read(PVR_DMA_DEST),
119 long_read(PVR_DMA_COUNT), long_read(PVR_DMA_CTL) );
120 dmac_dump_channel(stderr, 2);
121 long_write( PVR_DMA_CTL, 0 );
124 CHECK_IEQUALS( 0, long_read(PVR_DMA_CTL) );
125 CHECK_IEQUALS( ((uint32_t)buf)+len, long_read(DMA_SAR(2)) );
126 CHECK_IEQUALS( 0, long_read(DMA_TCR(2)) );
127 CHECK_IEQUALS( 0x12C3, long_read(DMA_CHCR(2)) );
128 CHECK_IEQUALS( target, long_read(PVR_DMA_DEST) );
129 CHECK_IEQUALS( 0, long_read(PVR_DMA_COUNT) );
130 CHECK_IEQUALS( 0, long_read(PVR_DMA_REGION) );
135 int sort_dma_write( char *sorttable, int tablelen, char *data, int datalen, int bitwidth, int datasize )
138 uint32_t tableaddr = (uint32_t)sorttable;
139 uint32_t dataaddr = (uint32_t)data;
141 long_write( SORT_DMA_CTL, 0 );
144 long_write( SORT_DMA_TABLE, tableaddr );
145 long_write( SORT_DMA_DATA, dataaddr );
146 long_write( SORT_DMA_TABLEBITS, bitwidth );
147 long_write( SORT_DMA_DATASIZE, datasize );
148 long_write( SORT_DMA_CTL, 1 );
149 result = asic_wait2(EVENT_SORT_DMA, EVENT_SORT_DMA_ERR);
151 fprintf( stderr, "SORT DMA failed (timeout)\n" );
153 fprintf( stderr, "Table: %08X Count: %08X Ctl: %08X\n", long_read(SORT_DMA_TABLE), long_read(SORT_DMA_COUNT),
154 long_read(SORT_DMA_CTL) );
155 long_write( SORT_DMA_CTL, 0 );
157 CHECK_IEQUALS( 0, long_read(SORT_DMA_CTL) );
.