lxdream 0.9.1| filename | src/pvr2/pvr2.c |
| changeset | 441:0ff0093f3088 |
| prev | 433:a4f61551d79d |
| next | 477:9a373f2ff009 |
| author | nkeynes |
| date | Sat Oct 13 03:59:32 2007 +0000 (13 years ago) |
| permissions | -rw-r--r-- |
| last change | Track the last-displayed render buffer, so-as not to overwrite it while its still on-screen |
| view | annotate | diff | log | raw |
1 /**
2 * $Id: pvr2.c,v 1.47 2007-10-13 03:59:32 nkeynes Exp $
3 *
4 * PVR2 (Video) Core module implementation and MMIO registers.
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18 #define MODULE pvr2_module
20 #include "dream.h"
21 #include "eventq.h"
22 #include "display.h"
23 #include "mem.h"
24 #include "asic.h"
25 #include "clock.h"
26 #include "pvr2/pvr2.h"
27 #include "sh4/sh4core.h"
28 #define MMIO_IMPL
29 #include "pvr2/pvr2mmio.h"
31 char *video_base;
33 #define MAX_RENDER_BUFFERS 4
35 #define HPOS_PER_FRAME 0
36 #define HPOS_PER_LINECOUNT 1
38 static void pvr2_init( void );
39 static void pvr2_reset( void );
40 static uint32_t pvr2_run_slice( uint32_t );
41 static void pvr2_save_state( FILE *f );
42 static int pvr2_load_state( FILE *f );
43 static void pvr2_update_raster_posn( uint32_t nanosecs );
44 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
45 static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
46 static render_buffer_t pvr2_next_render_buffer( );
47 uint32_t pvr2_get_sync_status();
49 void pvr2_display_frame( void );
51 static int output_colour_formats[] = { COLFMT_ARGB1555, COLFMT_RGB565, COLFMT_RGB888, COLFMT_ARGB8888 };
53 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,
54 pvr2_run_slice, NULL,
55 pvr2_save_state, pvr2_load_state };
58 display_driver_t display_driver = NULL;
60 struct pvr2_state {
61 uint32_t frame_count;
62 uint32_t line_count;
63 uint32_t line_remainder;
64 uint32_t cycles_run; /* Cycles already executed prior to main time slice */
65 uint32_t irq_hpos_line;
66 uint32_t irq_hpos_line_count;
67 uint32_t irq_hpos_mode;
68 uint32_t irq_hpos_time_ns; /* Time within the line */
69 uint32_t irq_vpos1;
70 uint32_t irq_vpos2;
71 uint32_t odd_even_field; /* 1 = odd, 0 = even */
72 gboolean palette_changed; /* TRUE if palette has changed since last render */
73 gchar *save_next_render_filename;
74 /* timing */
75 uint32_t dot_clock;
76 uint32_t total_lines;
77 uint32_t line_size;
78 uint32_t line_time_ns;
79 uint32_t vsync_lines;
80 uint32_t hsync_width_ns;
81 uint32_t front_porch_ns;
82 uint32_t back_porch_ns;
83 uint32_t retrace_start_line;
84 uint32_t retrace_end_line;
85 gboolean interlaced;
86 } pvr2_state;
88 static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
89 static int render_buffer_count = 0;
90 static render_buffer_t displayed_render_buffer = NULL;
92 /**
93 * Event handler for the hpos callback
94 */
95 static void pvr2_hpos_callback( int eventid ) {
96 asic_event( eventid );
97 pvr2_update_raster_posn(sh4r.slice_cycle);
98 if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
99 pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
100 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
101 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
102 }
103 }
104 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1,
105 pvr2_state.irq_hpos_time_ns );
106 }
108 /**
109 * Event handler for the scanline callbacks. Fires the corresponding
110 * ASIC event, and resets the timer for the next field.
111 */
112 static void pvr2_scanline_callback( int eventid ) {
113 asic_event( eventid );
114 pvr2_update_raster_posn(sh4r.slice_cycle);
115 if( eventid == EVENT_SCANLINE1 ) {
116 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
117 } else {
118 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
119 }
120 }
122 static void pvr2_init( void )
123 {
124 int i;
125 register_io_region( &mmio_region_PVR2 );
126 register_io_region( &mmio_region_PVR2PAL );
127 register_io_region( &mmio_region_PVR2TA );
128 register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
129 register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
130 register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
131 video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
132 texcache_init();
133 pvr2_reset();
134 pvr2_ta_reset();
135 pvr2_state.save_next_render_filename = NULL;
136 for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
137 render_buffers[i] = NULL;
138 }
139 render_buffer_count = 0;
140 displayed_render_buffer = NULL;
141 }
143 static void pvr2_reset( void )
144 {
145 pvr2_state.line_count = 0;
146 pvr2_state.line_remainder = 0;
147 pvr2_state.cycles_run = 0;
148 pvr2_state.irq_vpos1 = 0;
149 pvr2_state.irq_vpos2 = 0;
150 pvr2_state.dot_clock = PVR2_DOT_CLOCK;
151 pvr2_state.back_porch_ns = 4000;
152 pvr2_state.palette_changed = FALSE;
153 mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
154 mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
155 mmio_region_PVR2_write( YUV_ADDR, 0 );
156 mmio_region_PVR2_write( YUV_CFG, 0 );
158 pvr2_ta_init();
159 texcache_flush();
160 }
162 static void pvr2_save_state( FILE *f )
163 {
164 fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
165 pvr2_ta_save_state( f );
166 pvr2_yuv_save_state( f );
167 }
169 static int pvr2_load_state( FILE *f )
170 {
171 if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
172 return 1;
173 if( pvr2_ta_load_state(f) ) {
174 return 1;
175 }
176 return pvr2_yuv_load_state(f);
177 }
179 /**
180 * Update the current raster position to the given number of nanoseconds,
181 * relative to the last time slice. (ie the raster will be adjusted forward
182 * by nanosecs - nanosecs_already_run_this_timeslice)
183 */
184 static void pvr2_update_raster_posn( uint32_t nanosecs )
185 {
186 uint32_t old_line_count = pvr2_state.line_count;
187 if( pvr2_state.line_time_ns == 0 ) {
188 return; /* do nothing */
189 }
190 pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
191 pvr2_state.cycles_run = nanosecs;
192 while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
193 pvr2_state.line_count ++;
194 pvr2_state.line_remainder -= pvr2_state.line_time_ns;
195 }
197 if( pvr2_state.line_count >= pvr2_state.total_lines ) {
198 pvr2_state.line_count -= pvr2_state.total_lines;
199 if( pvr2_state.interlaced ) {
200 pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
201 }
202 }
203 if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
204 (old_line_count < pvr2_state.retrace_end_line ||
205 old_line_count > pvr2_state.line_count) ) {
206 pvr2_state.frame_count++;
207 pvr2_display_frame();
208 }
209 }
211 static uint32_t pvr2_run_slice( uint32_t nanosecs )
212 {
213 pvr2_update_raster_posn( nanosecs );
214 pvr2_state.cycles_run = 0;
215 return nanosecs;
216 }
218 int pvr2_get_frame_count()
219 {
220 return pvr2_state.frame_count;
221 }
223 gboolean pvr2_save_next_scene( const gchar *filename )
224 {
225 if( pvr2_state.save_next_render_filename != NULL ) {
226 g_free( pvr2_state.save_next_render_filename );
227 }
228 pvr2_state.save_next_render_filename = g_strdup(filename);
229 return TRUE;
230 }
234 /**
235 * Display the next frame, copying the current contents of video ram to
236 * the window. If the video configuration has changed, first recompute the
237 * new frame size/depth.
238 */
239 void pvr2_display_frame( void )
240 {
241 int dispmode = MMIO_READ( PVR2, DISP_MODE );
242 int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
243 gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
245 if( display_driver == NULL ) {
246 return; /* can't really do anything much */
247 } else if( !bEnabled ) {
248 /* Output disabled == black */
249 display_driver->display_blank( 0 );
250 displayed_render_buffer = NULL;
251 } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) {
252 /* Enabled but blanked - border colour */
253 uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
254 display_driver->display_blank( colour );
255 displayed_render_buffer = NULL;
256 } else {
257 /* Real output - determine dimensions etc */
258 struct frame_buffer fbuf;
259 uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
260 int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
261 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
263 fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
264 fbuf.width = vid_ppl << 2 / colour_formats[fbuf.colour_format].bpp;
265 fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
266 fbuf.size = vid_ppl << 2 * fbuf.height;
267 fbuf.rowstride = (vid_ppl + vid_stride) << 2;
269 /* Determine the field to display, and deinterlace if possible */
270 if( pvr2_state.interlaced ) {
271 if( vid_ppl == vid_stride ) { /* Magic deinterlace */
272 fbuf.height = fbuf.height << 1;
273 fbuf.rowstride = vid_ppl << 2;
274 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
275 } else {
276 /* Just display the field as is, folks. This is slightly tricky -
277 * we pick the field based on which frame is about to come through,
278 * which may not be the same as the odd_even_field.
279 */
280 gboolean oddfield = pvr2_state.odd_even_field;
281 if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
282 oddfield = !oddfield;
283 }
284 if( oddfield ) {
285 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
286 } else {
287 fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
288 }
289 }
290 } else {
291 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
292 }
293 fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
295 render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
296 displayed_render_buffer = rbuf;
297 if( rbuf != NULL ) {
298 display_driver->display_render_buffer( rbuf );
299 } else {
300 fbuf.data = video_base + (fbuf.address&0x00FFFFFF);
301 display_driver->display_frame_buffer( &fbuf );
302 }
303 }
304 }
306 /**
307 * This has to handle every single register individually as they all get masked
308 * off differently (and its easier to do it at write time)
309 */
310 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
311 {
312 if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
313 MMIO_WRITE( PVR2, reg, val );
314 return;
315 }
317 switch(reg) {
318 case PVRID:
319 case PVRVER:
320 case GUNPOS: /* Read only registers */
321 break;
322 case PVRRESET:
323 val &= 0x00000007; /* Do stuff? */
324 MMIO_WRITE( PVR2, reg, val );
325 break;
326 case RENDER_START: /* Don't really care what value */
327 if( pvr2_state.save_next_render_filename != NULL ) {
328 if( pvr2_render_save_scene(pvr2_state.save_next_render_filename) == 0 ) {
329 INFO( "Saved scene to %s", pvr2_state.save_next_render_filename);
330 }
331 g_free( pvr2_state.save_next_render_filename );
332 pvr2_state.save_next_render_filename = NULL;
333 }
334 render_buffer_t buffer = pvr2_next_render_buffer();
335 if( buffer != NULL ) {
336 pvr2_render_scene( buffer );
337 }
338 asic_event( EVENT_PVR_RENDER_DONE );
339 break;
340 case RENDER_POLYBASE:
341 MMIO_WRITE( PVR2, reg, val&0x00F00000 );
342 break;
343 case RENDER_TSPCFG:
344 MMIO_WRITE( PVR2, reg, val&0x00010101 );
345 break;
346 case DISP_BORDER:
347 MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
348 break;
349 case DISP_MODE:
350 MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
351 break;
352 case RENDER_MODE:
353 MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
354 break;
355 case RENDER_SIZE:
356 MMIO_WRITE( PVR2, reg, val&0x000001FF );
357 break;
358 case DISP_ADDR1:
359 val &= 0x00FFFFFC;
360 MMIO_WRITE( PVR2, reg, val );
361 pvr2_update_raster_posn(sh4r.slice_cycle);
362 break;
363 case DISP_ADDR2:
364 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
365 pvr2_update_raster_posn(sh4r.slice_cycle);
366 break;
367 case DISP_SIZE:
368 MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
369 break;
370 case RENDER_ADDR1:
371 case RENDER_ADDR2:
372 MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
373 break;
374 case RENDER_HCLIP:
375 MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
376 break;
377 case RENDER_VCLIP:
378 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
379 break;
380 case DISP_HPOSIRQ:
381 MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
382 pvr2_state.irq_hpos_line = val & 0x03FF;
383 pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
384 pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
385 switch( pvr2_state.irq_hpos_mode ) {
386 case 3: /* Reserved - treat as 0 */
387 case 0: /* Once per frame at specified line */
388 pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
389 break;
390 case 2: /* Once per line - as per-line-count */
391 pvr2_state.irq_hpos_line = 1;
392 pvr2_state.irq_hpos_mode = 1;
393 case 1: /* Once per N lines */
394 pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
395 pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) +
396 pvr2_state.irq_hpos_line_count;
397 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
398 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
399 }
400 pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
401 }
402 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
403 pvr2_state.irq_hpos_time_ns );
404 break;
405 case DISP_VPOSIRQ:
406 val = val & 0x03FF03FF;
407 pvr2_state.irq_vpos1 = (val >> 16);
408 pvr2_state.irq_vpos2 = val & 0x03FF;
409 pvr2_update_raster_posn(sh4r.slice_cycle);
410 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
411 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
412 MMIO_WRITE( PVR2, reg, val );
413 break;
414 case RENDER_NEARCLIP:
415 MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
416 break;
417 case RENDER_SHADOW:
418 MMIO_WRITE( PVR2, reg, val&0x000001FF );
419 break;
420 case RENDER_OBJCFG:
421 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
422 break;
423 case RENDER_TSPCLIP:
424 MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
425 break;
426 case RENDER_FARCLIP:
427 MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
428 break;
429 case RENDER_BGPLANE:
430 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
431 break;
432 case RENDER_ISPCFG:
433 MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
434 break;
435 case VRAM_CFG1:
436 MMIO_WRITE( PVR2, reg, val&0x000000FF );
437 break;
438 case VRAM_CFG2:
439 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
440 break;
441 case VRAM_CFG3:
442 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
443 break;
444 case RENDER_FOGTBLCOL:
445 case RENDER_FOGVRTCOL:
446 MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
447 break;
448 case RENDER_FOGCOEFF:
449 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
450 break;
451 case RENDER_CLAMPHI:
452 case RENDER_CLAMPLO:
453 MMIO_WRITE( PVR2, reg, val );
454 break;
455 case RENDER_TEXSIZE:
456 MMIO_WRITE( PVR2, reg, val&0x00031F1F );
457 break;
458 case RENDER_PALETTE:
459 MMIO_WRITE( PVR2, reg, val&0x00000003 );
460 break;
462 /********** CRTC registers *************/
463 case DISP_HBORDER:
464 case DISP_VBORDER:
465 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
466 break;
467 case DISP_TOTAL:
468 val = val & 0x03FF03FF;
469 MMIO_WRITE( PVR2, reg, val );
470 pvr2_update_raster_posn(sh4r.slice_cycle);
471 pvr2_state.total_lines = (val >> 16) + 1;
472 pvr2_state.line_size = (val & 0x03FF) + 1;
473 pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
474 pvr2_state.retrace_end_line = 0x2A;
475 pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
476 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
477 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
478 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
479 pvr2_state.irq_hpos_time_ns );
480 break;
481 case DISP_SYNCCFG:
482 MMIO_WRITE( PVR2, reg, val&0x000003FF );
483 pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
484 break;
485 case DISP_SYNCTIME:
486 pvr2_state.vsync_lines = (val >> 8) & 0x0F;
487 pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
488 MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
489 break;
490 case DISP_CFG2:
491 MMIO_WRITE( PVR2, reg, val&0x003F01FF );
492 break;
493 case DISP_HPOS:
494 val = val & 0x03FF;
495 pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
496 MMIO_WRITE( PVR2, reg, val );
497 break;
498 case DISP_VPOS:
499 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
500 break;
502 /*********** Tile accelerator registers ***********/
503 case TA_POLYPOS:
504 case TA_LISTPOS:
505 /* Readonly registers */
506 break;
507 case TA_TILEBASE:
508 case TA_LISTEND:
509 case TA_LISTBASE:
510 MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
511 break;
512 case RENDER_TILEBASE:
513 case TA_POLYBASE:
514 case TA_POLYEND:
515 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
516 break;
517 case TA_TILESIZE:
518 MMIO_WRITE( PVR2, reg, val&0x000F003F );
519 break;
520 case TA_TILECFG:
521 MMIO_WRITE( PVR2, reg, val&0x00133333 );
522 break;
523 case TA_INIT:
524 if( val & 0x80000000 )
525 pvr2_ta_init();
526 break;
527 case TA_REINIT:
528 break;
529 /**************** Scaler registers? ****************/
530 case RENDER_SCALER:
531 MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
532 break;
534 case YUV_ADDR:
535 val = val & 0x00FFFFF8;
536 MMIO_WRITE( PVR2, reg, val );
537 pvr2_yuv_init( val );
538 break;
539 case YUV_CFG:
540 MMIO_WRITE( PVR2, reg, val&0x01013F3F );
541 pvr2_yuv_set_config(val);
542 break;
544 /**************** Unknowns ***************/
545 case PVRUNK1:
546 MMIO_WRITE( PVR2, reg, val&0x000007FF );
547 break;
548 case PVRUNK2:
549 MMIO_WRITE( PVR2, reg, val&0x00000007 );
550 break;
551 case PVRUNK3:
552 MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
553 break;
554 case PVRUNK5:
555 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
556 break;
557 case PVRUNK6:
558 MMIO_WRITE( PVR2, reg, val&0x000000FF );
559 break;
560 case PVRUNK7:
561 MMIO_WRITE( PVR2, reg, val&0x00000001 );
562 break;
563 }
564 }
566 /**
567 * Calculate the current read value of the syncstat register, using
568 * the current SH4 clock time as an offset from the last timeslice.
569 * The register reads (LSB to MSB) as:
570 * 0..9 Current scan line
571 * 10 Odd/even field (1 = odd, 0 = even)
572 * 11 Display active (including border and overscan)
573 * 12 Horizontal sync off
574 * 13 Vertical sync off
575 * Note this method is probably incorrect for anything other than straight
576 * interlaced PAL/NTSC, and needs further testing.
577 */
578 uint32_t pvr2_get_sync_status()
579 {
580 pvr2_update_raster_posn(sh4r.slice_cycle);
581 uint32_t result = pvr2_state.line_count;
583 if( pvr2_state.odd_even_field ) {
584 result |= 0x0400;
585 }
586 if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
587 if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
588 result |= 0x1000; /* !HSYNC */
589 }
590 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
591 if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
592 result |= 0x2800; /* Display active */
593 } else {
594 result |= 0x2000; /* Front porch */
595 }
596 }
597 } else {
598 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
599 if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
600 result |= 0x3800; /* Display active */
601 } else {
602 result |= 0x3000;
603 }
604 } else {
605 result |= 0x1000; /* Back porch */
606 }
607 }
608 return result;
609 }
611 /**
612 * Schedule a "scanline" event. This actually goes off at
613 * 2 * line in even fields and 2 * line + 1 in odd fields.
614 * Otherwise this behaves as per pvr2_schedule_line_event().
615 * The raster position should be updated before calling this
616 * method.
617 * @param eventid Event to fire at the specified time
618 * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
619 * displays).
620 * @param hpos_ns Nanoseconds into the line at which to fire.
621 */
622 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
623 {
624 uint32_t field = pvr2_state.odd_even_field;
625 if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
626 field = !field;
627 }
628 if( hpos_ns > pvr2_state.line_time_ns ) {
629 hpos_ns = pvr2_state.line_time_ns;
630 }
632 line <<= 1;
633 if( field ) {
634 line += 1;
635 }
637 if( line < pvr2_state.total_lines ) {
638 uint32_t lines;
639 uint32_t time;
640 if( line <= pvr2_state.line_count ) {
641 lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
642 } else {
643 lines = (line - pvr2_state.line_count);
644 }
645 if( lines <= minimum_lines ) {
646 lines += pvr2_state.total_lines;
647 }
648 time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
649 event_schedule( eventid, time );
650 } else {
651 event_cancel( eventid );
652 }
653 }
655 MMIO_REGION_READ_FN( PVR2, reg )
656 {
657 switch( reg ) {
658 case DISP_SYNCSTAT:
659 return pvr2_get_sync_status();
660 default:
661 return MMIO_READ( PVR2, reg );
662 }
663 }
665 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
666 {
667 MMIO_WRITE( PVR2PAL, reg, val );
668 pvr2_state.palette_changed = TRUE;
669 }
671 void pvr2_check_palette_changed()
672 {
673 if( pvr2_state.palette_changed ) {
674 texcache_invalidate_palette();
675 pvr2_state.palette_changed = FALSE;
676 }
677 }
679 MMIO_REGION_READ_DEFFN( PVR2PAL );
681 void pvr2_set_base_address( uint32_t base )
682 {
683 mmio_region_PVR2_write( DISP_ADDR1, base );
684 }
689 int32_t mmio_region_PVR2TA_read( uint32_t reg )
690 {
691 return 0xFFFFFFFF;
692 }
694 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
695 {
696 pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );
697 }
699 /**
700 * Find the render buffer corresponding to the requested output frame
701 * (does not consider texture renders).
702 * @return the render_buffer if found, or null if no such buffer.
703 *
704 * Note: Currently does not consider "partial matches", ie partial
705 * frame overlap - it probably needs to do this.
706 */
707 render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
708 {
709 int i;
710 for( i=0; i<render_buffer_count; i++ ) {
711 if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
712 return render_buffers[i];
713 }
714 }
715 return NULL;
716 }
718 /**
719 * Determine the next render buffer to write into. The order of preference is:
720 * 1. An existing buffer with the same address. (not flushed unless the new
721 * size is smaller than the old one).
722 * 2. An existing buffer with the same size chosen by LRU order. Old buffer
723 * is flushed to vram.
724 * 3. A new buffer if one can be created.
725 * 4. The current display buff
726 * Note: The current display field(s) will never be overwritten except as a last
727 * resort.
728 */
729 render_buffer_t pvr2_next_render_buffer()
730 {
731 render_buffer_t result = NULL;
732 uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
733 uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
734 uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
735 uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
737 if( render_addr & 0x01000000 ) { /* vram64 */
738 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
739 } else { /* vram32 */
740 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
741 }
743 int width, height, i;
744 int colour_format = pvr2_render_colour_format[render_mode&0x07];
745 pvr2_render_getsize( &width, &height );
747 /* Check existing buffers for an available buffer */
748 for( i=0; i<render_buffer_count; i++ ) {
749 if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
750 /* needs to be the right dimensions */
751 if( render_buffers[i]->address == render_addr ) {
752 if( displayed_render_buffer == render_buffers[i] ) {
753 /* Same address, but we can't use it because the
754 * display has it. Mark it as unaddressed for later.
755 render_buffers[i]->address = -1;
756 } else {
757 /* perfect */
758 result = render_buffers[i];
759 break;
760 }
761 } else if( render_buffers[i]->address == -1 && result == NULL &&
762 displayed_render_buffer != render_buffers[i] ) {
763 result = render_buffers[i];
764 }
766 } else if( render_buffers[i]->address == render_addr ) {
767 /* right address, wrong size - if it's larger, flush it, otherwise
768 * nuke it quietly */
769 if( render_buffers[i]->width * render_buffers[i]->height >
770 width*height ) {
771 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
772 }
773 render_buffers[i]->address = -1;
774 }
775 }
777 /* Nothing available - make one */
778 if( result == NULL ) {
779 if( render_buffer_count == MAX_RENDER_BUFFERS ) {
780 /* maximum buffers reached - need to throw one away */
781 uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
782 uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
783 for( i=0; i<render_buffer_count; i++ ) {
784 if( render_buffers[i]->address != field1_addr &&
785 render_buffers[i]->address != field2_addr &&
786 render_buffers[i] != displayed_render_buffer ) {
787 /* Never throw away the current "front buffer(s)" */
788 result = render_buffers[i];
789 pvr2_render_buffer_copy_to_sh4( result );
790 if( result->width != width || result->height != height ) {
791 display_driver->destroy_render_buffer(render_buffers[i]);
792 result = display_driver->create_render_buffer(width,height);
793 render_buffers[i] = result;
794 }
795 break;
796 }
797 }
798 } else {
799 result = display_driver->create_render_buffer(width,height);
800 if( result != NULL ) {
801 render_buffers[render_buffer_count++] = result;
802 } else {
803 // ERROR( "Failed to obtain a render buffer!" );
804 return NULL;
805 }
806 }
807 }
809 /* Setup the buffer */
810 result->rowstride = render_stride;
811 result->colour_format = colour_format;
812 result->scale = render_scale;
813 result->size = width * height * colour_formats[colour_format].bpp;
814 result->address = render_addr;
815 result->flushed = FALSE;
816 return result;
817 }
819 /**
820 * Invalidate any caching on the supplied address. Specifically, if it falls
821 * within any of the render buffers, flush the buffer back to PVR2 ram.
822 */
823 gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
824 {
825 int i;
826 address = address & 0x1FFFFFFF;
827 for( i=0; i<render_buffer_count; i++ ) {
828 uint32_t bufaddr = render_buffers[i]->address;
829 if( bufaddr != -1 && bufaddr <= address &&
830 (bufaddr + render_buffers[i]->size) > address ) {
831 if( !render_buffers[i]->flushed ) {
832 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
833 render_buffers[i]->flushed = TRUE;
834 }
835 if( isWrite ) {
836 render_buffers[i]->address = -1; /* Invalid */
837 }
838 return TRUE; /* should never have overlapping buffers */
839 }
840 }
841 return FALSE;
842 }
.