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lxdream.org :: lxdream/src/sh4/ia32abi.h
lxdream 0.9.1
released Jun 29
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filename src/sh4/ia32abi.h
changeset 604:1024c3a9cb88
prev596:dfc0c93d882e
next669:ab344e42bca9
author nkeynes
date Tue Jan 22 11:30:37 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Fix backpatching when the block moves during translation
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     1 /**
     2  * $Id$
     3  * 
     4  * Provides the implementation for the ia32 ABI (eg prologue, epilogue, and
     5  * calling conventions)
     6  *
     7  * Copyright (c) 2007 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #ifndef __lxdream_ia32abi_H
    21 #define __lxdream_ia32abi_H 1
    23 #define load_ptr( reg, ptr ) load_imm32( reg, (uint32_t)ptr );
    25 /**
    26  * Note: clobbers EAX to make the indirect call - this isn't usually
    27  * a problem since the callee will usually clobber it anyway.
    28  */
    29 #define CALL_FUNC0_SIZE 7
    30 static inline void call_func0( void *ptr )
    31 {
    32     load_imm32(R_EAX, (uint32_t)ptr);
    33     CALL_r32(R_EAX);
    34 }
    36 #define CALL_FUNC1_SIZE 11
    37 static inline void call_func1( void *ptr, int arg1 )
    38 {
    39     PUSH_r32(arg1);
    40     call_func0(ptr);
    41     ADD_imm8s_r32( 4, R_ESP );
    42 }
    44 #define CALL_FUNC2_SIZE 12
    45 static inline void call_func2( void *ptr, int arg1, int arg2 )
    46 {
    47     PUSH_r32(arg2);
    48     PUSH_r32(arg1);
    49     call_func0(ptr);
    50     ADD_imm8s_r32( 8, R_ESP );
    51 }
    53 /**
    54  * Write a double (64-bit) value into memory, with the first word in arg2a, and
    55  * the second in arg2b
    56  * NB: 30 bytes
    57  */
    58 #define MEM_WRITE_DOUBLE_SIZE 30
    59 static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
    60 {
    61     ADD_imm8s_r32( 4, addr );
    62     PUSH_r32(arg2b);
    63     PUSH_r32(addr);
    64     ADD_imm8s_r32( -4, addr );
    65     PUSH_r32(arg2a);
    66     PUSH_r32(addr);
    67     call_func0(sh4_write_long);
    68     ADD_imm8s_r32( 8, R_ESP );
    69     call_func0(sh4_write_long);
    70     ADD_imm8s_r32( 8, R_ESP );
    71 }
    73 /**
    74  * Read a double (64-bit) value from memory, writing the first word into arg2a
    75  * and the second into arg2b. The addr must not be in EAX
    76  * NB: 27 bytes
    77  */
    78 #define MEM_READ_DOUBLE_SIZE 27
    79 static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
    80 {
    81     PUSH_r32(addr);
    82     call_func0(sh4_read_long);
    83     POP_r32(R_ECX);
    84     PUSH_r32(R_EAX);
    85     ADD_imm8s_r32( 4, R_ECX );
    86     PUSH_r32(R_ECX);
    87     call_func0(sh4_read_long);
    88     ADD_imm8s_r32( 4, R_ESP );
    89     MOV_r32_r32( R_EAX, arg2b );
    90     POP_r32(arg2a);
    91 }
    93 /**
    94  * Emit the 'start of block' assembly. Sets up the stack frame and save
    95  * SI/DI as required
    96  */
    97 void sh4_translate_begin_block( sh4addr_t pc ) 
    98 {
    99     PUSH_r32(R_EBP);
   100     /* mov &sh4r, ebp */
   101     load_ptr( R_EBP, &sh4r );
   103     sh4_x86.in_delay_slot = FALSE;
   104     sh4_x86.priv_checked = FALSE;
   105     sh4_x86.fpuen_checked = FALSE;
   106     sh4_x86.branch_taken = FALSE;
   107     sh4_x86.backpatch_posn = 0;
   108     sh4_x86.block_start_pc = pc;
   109     sh4_x86.tlb_on = IS_MMU_ENABLED();
   110     sh4_x86.tstate = TSTATE_NONE;
   111 #ifdef STACK_ALIGN
   112 	sh4_x86.stack_posn = 8;
   113 #endif
   114 }
   116 /**
   117  * Exit the block with sh4r.pc already written
   118  */
   119 void exit_block_pcset( sh4addr_t pc )
   120 {
   121     load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   122     ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );    // 6
   123     load_spreg( R_EAX, R_PC );
   124     if( sh4_x86.tlb_on ) {
   125 	call_func1(xlat_get_code_by_vma,R_EAX);
   126     } else {
   127 	call_func1(xlat_get_code,R_EAX);
   128     } 
   129     POP_r32(R_EBP);
   130     RET();
   131 }
   133 /**
   134  * Exit the block with sh4r.new_pc written with the target pc
   135  */
   136 void exit_block_newpcset( sh4addr_t pc )
   137 {
   138     load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   139     ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );    // 6
   140     load_spreg( R_EAX, R_NEW_PC );
   141     store_spreg( R_EAX, R_PC );
   142     if( sh4_x86.tlb_on ) {
   143 	call_func1(xlat_get_code_by_vma,R_EAX);
   144     } else {
   145 	call_func1(xlat_get_code,R_EAX);
   146     } 
   147     POP_r32(R_EBP);
   148     RET();
   149 }
   151 #define EXIT_BLOCK_SIZE(pc)  (24 + (IS_IN_ICACHE(pc)?5:CALL_FUNC1_SIZE))
   154 /**
   155  * Exit the block to an absolute PC
   156  */
   157 void exit_block( sh4addr_t pc, sh4addr_t endpc )
   158 {
   159     load_imm32( R_ECX, pc );                            // 5
   160     store_spreg( R_ECX, REG_OFFSET(pc) );               // 3
   161     if( IS_IN_ICACHE(pc) ) {
   162 	MOV_moff32_EAX( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) ); // 5
   163     } else if( sh4_x86.tlb_on ) {
   164 	call_func1(xlat_get_code_by_vma,R_ECX);
   165     } else {
   166 	call_func1(xlat_get_code,R_ECX);
   167     }
   168     AND_imm8s_r32( 0xFC, R_EAX ); // 3
   169     load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   170     ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
   171     POP_r32(R_EBP);
   172     RET();
   173 }
   175 #define EXIT_BLOCK_REL_SIZE(pc)  (27 + (IS_IN_ICACHE(pc)?5:CALL_FUNC1_SIZE))
   177 /**
   178  * Exit the block to a relative PC
   179  */
   180 void exit_block_rel( sh4addr_t pc, sh4addr_t endpc )
   181 {
   182     load_imm32( R_ECX, pc - sh4_x86.block_start_pc );   // 5
   183     ADD_sh4r_r32( R_PC, R_ECX );
   184     store_spreg( R_ECX, REG_OFFSET(pc) );               // 3
   185     if( IS_IN_ICACHE(pc) ) {
   186 	MOV_moff32_EAX( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) ); // 5
   187     } else if( sh4_x86.tlb_on ) {
   188 	call_func1(xlat_get_code_by_vma,R_ECX);
   189     } else {
   190 	call_func1(xlat_get_code,R_ECX);
   191     }
   192     AND_imm8s_r32( 0xFC, R_EAX ); // 3
   193     load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   194     ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
   195     POP_r32(R_EBP);
   196     RET();
   197 }
   199 /**
   200  * Write the block trailer (exception handling block)
   201  */
   202 void sh4_translate_end_block( sh4addr_t pc ) {
   203     if( sh4_x86.branch_taken == FALSE ) {
   204 	// Didn't exit unconditionally already, so write the termination here
   205 	exit_block_rel( pc, pc );
   206     }
   207     if( sh4_x86.backpatch_posn != 0 ) {
   208 	unsigned int i;
   209 	// Raise exception
   210 	uint8_t *end_ptr = xlat_output;
   211 	MOV_r32_r32( R_EDX, R_ECX );
   212 	ADD_r32_r32( R_EDX, R_ECX );
   213 	ADD_r32_sh4r( R_ECX, R_PC );
   214 	MOV_moff32_EAX( &sh4_cpu_period );
   215 	MUL_r32( R_EDX );
   216 	ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
   218 	call_func0( sh4_raise_exception );
   219 	ADD_imm8s_r32( 4, R_ESP );
   220 	load_spreg( R_EAX, R_PC );
   221 	if( sh4_x86.tlb_on ) {
   222 	    call_func1(xlat_get_code_by_vma,R_EAX);
   223 	} else {
   224 	    call_func1(xlat_get_code,R_EAX);
   225 	}
   226 	POP_r32(R_EBP);
   227 	RET();
   229 	// Exception already raised - just cleanup
   230 	uint8_t *preexc_ptr = xlat_output;
   231 	MOV_r32_r32( R_EDX, R_ECX );
   232 	ADD_r32_r32( R_EDX, R_ECX );
   233 	ADD_r32_sh4r( R_ECX, R_SPC );
   234 	MOV_moff32_EAX( &sh4_cpu_period );
   235 	MUL_r32( R_EDX );
   236 	ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
   237 	load_spreg( R_EAX, R_PC );
   238 	if( sh4_x86.tlb_on ) {
   239 	    call_func1(xlat_get_code_by_vma,R_EAX);
   240 	} else {
   241 	    call_func1(xlat_get_code,R_EAX);
   242 	}
   243 	POP_r32(R_EBP);
   244 	RET();
   246 	for( i=0; i< sh4_x86.backpatch_posn; i++ ) {
   247 	    uint32_t *fixup_addr = (uint32_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset];
   248 	    *fixup_addr = xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
   249 	    if( sh4_x86.backpatch_list[i].exc_code < 0 ) {
   250 		load_imm32( R_EDX, sh4_x86.backpatch_list[i].fixup_icount );
   251 		int stack_adj = -1 - sh4_x86.backpatch_list[i].exc_code;
   252 		if( stack_adj > 0 ) { 
   253 		    ADD_imm8s_r32( stack_adj, R_ESP );
   254 		}
   255 		int rel = preexc_ptr - xlat_output;
   256 		JMP_rel(rel);
   257 	    } else {
   258 		PUSH_imm32( sh4_x86.backpatch_list[i].exc_code );
   259 		load_imm32( R_EDX, sh4_x86.backpatch_list[i].fixup_icount );
   260 		int rel = end_ptr - xlat_output;
   261 		JMP_rel(rel);
   262 	    }
   263 	}
   264     }
   265 }
   267 void *xlat_get_native_pc()
   268 {
   269     void *result = NULL;
   270     asm(
   271 	"mov %%ebp, %%eax\n\t"
   272 	"mov $0x8, %%ecx\n\t"
   273 	"mov %1, %%edx\n"
   274 "frame_loop: test %%eax, %%eax\n\t"
   275 	"je frame_not_found\n\t"
   276 	"cmp (%%eax), %%edx\n\t"
   277 	"je frame_found\n\t"
   278 	"sub $0x1, %%ecx\n\t"
   279 	"je frame_not_found\n\t"
   280 	"movl (%%eax), %%eax\n\t"
   281 	"jmp frame_loop\n"
   282 "frame_found: movl 0x4(%%eax), %0\n"
   283 "frame_not_found:"
   284 	: "=r" (result)
   285 	: "r" (&sh4r)
   286 	: "eax", "ecx", "edx" );
   287     return result;
   288 }
   290 #endif
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