filename | src/sh4/sh4core.c |
changeset | 391:16afb90b5d47 |
prev | 384:c9d5c194984b |
next | 401:f79327f39818 |
author | nkeynes |
date | Tue Sep 18 09:14:20 2007 +0000 (16 years ago) |
permissions | -rw-r--r-- |
last change | Add sh4_raise_trap() routine Share the new fsca/ftrv code between core + trans |
view | annotate | diff | log | raw |
1 /**
2 * $Id: sh4core.c,v 1.47 2007-09-18 09:14:20 nkeynes Exp $
3 *
4 * SH4 emulation core, and parent module for all the SH4 peripheral
5 * modules.
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #define MODULE sh4_module
21 #include <math.h>
22 #include "dream.h"
23 #include "sh4/sh4core.h"
24 #include "sh4/sh4mmio.h"
25 #include "sh4/intc.h"
26 #include "mem.h"
27 #include "clock.h"
28 #include "syscall.h"
30 #define SH4_CALLTRACE 1
32 #define MAX_INT 0x7FFFFFFF
33 #define MIN_INT 0x80000000
34 #define MAX_INTF 2147483647.0
35 #define MIN_INTF -2147483648.0
37 #define EXV_EXCEPTION 0x100 /* General exception vector */
38 #define EXV_TLBMISS 0x400 /* TLB-miss exception vector */
39 #define EXV_INTERRUPT 0x600 /* External interrupt vector */
41 /********************** SH4 Module Definition ****************************/
43 uint32_t sh4_run_slice( uint32_t );
45 uint16_t *sh4_icache = NULL;
46 uint32_t sh4_icache_addr = 0;
48 uint32_t sh4_run_slice( uint32_t nanosecs )
49 {
50 int i;
51 sh4r.slice_cycle = 0;
53 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
54 if( sh4r.event_pending < nanosecs ) {
55 sh4r.sh4_state = SH4_STATE_RUNNING;
56 sh4r.slice_cycle = sh4r.event_pending;
57 }
58 }
60 if( sh4_breakpoint_count == 0 ) {
61 for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
62 if( SH4_EVENT_PENDING() ) {
63 if( sh4r.event_types & PENDING_EVENT ) {
64 event_execute();
65 }
66 /* Eventq execute may (quite likely) deliver an immediate IRQ */
67 if( sh4r.event_types & PENDING_IRQ ) {
68 sh4_accept_interrupt();
69 }
70 }
71 // sh4_stats_add( sh4r.pc );
72 if( !sh4_execute_instruction() ) {
73 break;
74 }
75 }
76 } else {
77 for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
78 if( SH4_EVENT_PENDING() ) {
79 if( sh4r.event_types & PENDING_EVENT ) {
80 event_execute();
81 }
82 /* Eventq execute may (quite likely) deliver an immediate IRQ */
83 if( sh4r.event_types & PENDING_IRQ ) {
84 sh4_accept_interrupt();
85 }
86 }
88 if( !sh4_execute_instruction() )
89 break;
90 #ifdef ENABLE_DEBUG_MODE
91 for( i=0; i<sh4_breakpoint_count; i++ ) {
92 if( sh4_breakpoints[i].address == sh4r.pc ) {
93 break;
94 }
95 }
96 if( i != sh4_breakpoint_count ) {
97 dreamcast_stop();
98 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
99 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
100 break;
101 }
102 #endif
103 }
104 }
106 /* If we aborted early, but the cpu is still technically running,
107 * we're doing a hard abort - cut the timeslice back to what we
108 * actually executed
109 */
110 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
111 nanosecs = sh4r.slice_cycle;
112 }
113 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
114 TMU_run_slice( nanosecs );
115 SCIF_run_slice( nanosecs );
116 }
117 return nanosecs;
118 }
120 /********************** SH4 emulation core ****************************/
122 void sh4_set_pc( int pc )
123 {
124 sh4r.pc = pc;
125 sh4r.new_pc = pc+2;
126 }
128 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
129 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
131 #if(SH4_CALLTRACE == 1)
132 #define MAX_CALLSTACK 32
133 static struct call_stack {
134 sh4addr_t call_addr;
135 sh4addr_t target_addr;
136 sh4addr_t stack_pointer;
137 } call_stack[MAX_CALLSTACK];
139 static int call_stack_depth = 0;
140 int sh4_call_trace_on = 0;
142 static inline trace_call( sh4addr_t source, sh4addr_t dest )
143 {
144 if( call_stack_depth < MAX_CALLSTACK ) {
145 call_stack[call_stack_depth].call_addr = source;
146 call_stack[call_stack_depth].target_addr = dest;
147 call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
148 }
149 call_stack_depth++;
150 }
152 static inline trace_return( sh4addr_t source, sh4addr_t dest )
153 {
154 if( call_stack_depth > 0 ) {
155 call_stack_depth--;
156 }
157 }
159 void fprint_stack_trace( FILE *f )
160 {
161 int i = call_stack_depth -1;
162 if( i >= MAX_CALLSTACK )
163 i = MAX_CALLSTACK - 1;
164 for( ; i >= 0; i-- ) {
165 fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",
166 (call_stack_depth - i), call_stack[i].call_addr,
167 call_stack[i].target_addr, call_stack[i].stack_pointer );
168 }
169 }
171 #define TRACE_CALL( source, dest ) trace_call(source, dest)
172 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
173 #else
174 #define TRACE_CALL( dest, rts )
175 #define TRACE_RETURN( source, dest )
176 #endif
178 #define RAISE( x, v ) do{ \
179 if( sh4r.vbr == 0 ) { \
180 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
181 dreamcast_stop(); return FALSE; \
182 } else { \
183 sh4r.spc = sh4r.pc; \
184 sh4r.ssr = sh4_read_sr(); \
185 sh4r.sgr = sh4r.r[15]; \
186 MMIO_WRITE(MMU,EXPEVT,x); \
187 sh4r.pc = sh4r.vbr + v; \
188 sh4r.new_pc = sh4r.pc + 2; \
189 sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
190 if( sh4r.in_delay_slot ) { \
191 sh4r.in_delay_slot = 0; \
192 sh4r.spc -= 2; \
193 } \
194 } \
195 return TRUE; } while(0)
197 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
198 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
199 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
200 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
201 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
202 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
204 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
206 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
207 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
209 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
210 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
211 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
212 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
213 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
215 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
216 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
217 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
219 static void sh4_switch_banks( )
220 {
221 uint32_t tmp[8];
223 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
224 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
225 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
226 }
228 void sh4_write_sr( uint32_t newval )
229 {
230 if( (newval ^ sh4r.sr) & SR_RB )
231 sh4_switch_banks();
232 sh4r.sr = newval;
233 sh4r.t = (newval&SR_T) ? 1 : 0;
234 sh4r.s = (newval&SR_S) ? 1 : 0;
235 sh4r.m = (newval&SR_M) ? 1 : 0;
236 sh4r.q = (newval&SR_Q) ? 1 : 0;
237 intc_mask_changed();
238 }
240 static void sh4_write_float( uint32_t addr, int reg )
241 {
242 if( IS_FPU_DOUBLESIZE() ) {
243 if( reg & 1 ) {
244 sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
245 sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
246 } else {
247 sh4_write_long( addr, *((uint32_t *)&FR(reg)) );
248 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
249 }
250 } else {
251 sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
252 }
253 }
255 static void sh4_read_float( uint32_t addr, int reg )
256 {
257 if( IS_FPU_DOUBLESIZE() ) {
258 if( reg & 1 ) {
259 *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
260 *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
261 } else {
262 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
263 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
264 }
265 } else {
266 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
267 }
268 }
270 uint32_t sh4_read_sr( void )
271 {
272 /* synchronize sh4r.sr with the various bitflags */
273 sh4r.sr &= SR_MQSTMASK;
274 if( sh4r.t ) sh4r.sr |= SR_T;
275 if( sh4r.s ) sh4r.sr |= SR_S;
276 if( sh4r.m ) sh4r.sr |= SR_M;
277 if( sh4r.q ) sh4r.sr |= SR_Q;
278 return sh4r.sr;
279 }
281 /**
282 * Raise a general CPU exception for the specified exception code.
283 * (NOT for TRAPA or TLB exceptions)
284 */
285 gboolean sh4_raise_exception( int code )
286 {
287 RAISE( code, EXV_EXCEPTION );
288 }
290 gboolean sh4_raise_trap( int trap )
291 {
292 MMIO_WRITE( MMU, TRA, trap<<2 );
293 return sh4_raise_exception( EXC_TRAP );
294 }
296 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
297 if( sh4r.in_delay_slot ) {
298 return sh4_raise_exception(slot_code);
299 } else {
300 return sh4_raise_exception(normal_code);
301 }
302 }
304 gboolean sh4_raise_tlb_exception( int code )
305 {
306 RAISE( code, EXV_TLBMISS );
307 }
309 void sh4_accept_interrupt( void )
310 {
311 uint32_t code = intc_accept_interrupt();
312 sh4r.ssr = sh4_read_sr();
313 sh4r.spc = sh4r.pc;
314 sh4r.sgr = sh4r.r[15];
315 sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
316 MMIO_WRITE( MMU, INTEVT, code );
317 sh4r.pc = sh4r.vbr + 0x600;
318 sh4r.new_pc = sh4r.pc + 2;
319 // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
320 }
322 gboolean sh4_execute_instruction( void )
323 {
324 uint32_t pc;
325 unsigned short ir;
326 uint32_t tmp;
327 float ftmp;
328 double dtmp;
330 #define R0 sh4r.r[0]
331 pc = sh4r.pc;
332 if( pc > 0xFFFFFF00 ) {
333 /* SYSCALL Magic */
334 syscall_invoke( pc );
335 sh4r.in_delay_slot = 0;
336 pc = sh4r.pc = sh4r.pr;
337 sh4r.new_pc = sh4r.pc + 2;
338 }
339 CHECKRALIGN16(pc);
341 /* Read instruction */
342 uint32_t pageaddr = pc >> 12;
343 if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
344 ir = sh4_icache[(pc&0xFFF)>>1];
345 } else {
346 sh4_icache = (uint16_t *)mem_get_page(pc);
347 if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
348 /* If someone's actually been so daft as to try to execute out of an IO
349 * region, fallback on the full-blown memory read
350 */
351 sh4_icache = NULL;
352 ir = MEM_READ_WORD(pc);
353 } else {
354 sh4_icache_addr = pageaddr;
355 ir = sh4_icache[(pc&0xFFF)>>1];
356 }
357 }
358 switch( (ir&0xF000) >> 12 ) {
359 case 0x0:
360 switch( ir&0xF ) {
361 case 0x2:
362 switch( (ir&0x80) >> 7 ) {
363 case 0x0:
364 switch( (ir&0x70) >> 4 ) {
365 case 0x0:
366 { /* STC SR, Rn */
367 uint32_t Rn = ((ir>>8)&0xF);
368 CHECKPRIV();
369 sh4r.r[Rn] = sh4_read_sr();
370 }
371 break;
372 case 0x1:
373 { /* STC GBR, Rn */
374 uint32_t Rn = ((ir>>8)&0xF);
375 CHECKPRIV();
376 sh4r.r[Rn] = sh4r.gbr;
377 }
378 break;
379 case 0x2:
380 { /* STC VBR, Rn */
381 uint32_t Rn = ((ir>>8)&0xF);
382 CHECKPRIV();
383 sh4r.r[Rn] = sh4r.vbr;
384 }
385 break;
386 case 0x3:
387 { /* STC SSR, Rn */
388 uint32_t Rn = ((ir>>8)&0xF);
389 CHECKPRIV();
390 sh4r.r[Rn] = sh4r.ssr;
391 }
392 break;
393 case 0x4:
394 { /* STC SPC, Rn */
395 uint32_t Rn = ((ir>>8)&0xF);
396 CHECKPRIV();
397 sh4r.r[Rn] = sh4r.spc;
398 }
399 break;
400 default:
401 UNDEF();
402 break;
403 }
404 break;
405 case 0x1:
406 { /* STC Rm_BANK, Rn */
407 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
408 CHECKPRIV();
409 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
410 }
411 break;
412 }
413 break;
414 case 0x3:
415 switch( (ir&0xF0) >> 4 ) {
416 case 0x0:
417 { /* BSRF Rn */
418 uint32_t Rn = ((ir>>8)&0xF);
419 CHECKSLOTILLEGAL();
420 CHECKDEST( pc + 4 + sh4r.r[Rn] );
421 sh4r.in_delay_slot = 1;
422 sh4r.pr = sh4r.pc + 4;
423 sh4r.pc = sh4r.new_pc;
424 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
425 TRACE_CALL( pc, sh4r.new_pc );
426 return TRUE;
427 }
428 break;
429 case 0x2:
430 { /* BRAF Rn */
431 uint32_t Rn = ((ir>>8)&0xF);
432 CHECKSLOTILLEGAL();
433 CHECKDEST( pc + 4 + sh4r.r[Rn] );
434 sh4r.in_delay_slot = 1;
435 sh4r.pc = sh4r.new_pc;
436 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
437 return TRUE;
438 }
439 break;
440 case 0x8:
441 { /* PREF @Rn */
442 uint32_t Rn = ((ir>>8)&0xF);
443 tmp = sh4r.r[Rn];
444 if( (tmp & 0xFC000000) == 0xE0000000 ) {
445 sh4_flush_store_queue(tmp);
446 }
447 }
448 break;
449 case 0x9:
450 { /* OCBI @Rn */
451 uint32_t Rn = ((ir>>8)&0xF);
452 }
453 break;
454 case 0xA:
455 { /* OCBP @Rn */
456 uint32_t Rn = ((ir>>8)&0xF);
457 }
458 break;
459 case 0xB:
460 { /* OCBWB @Rn */
461 uint32_t Rn = ((ir>>8)&0xF);
462 }
463 break;
464 case 0xC:
465 { /* MOVCA.L R0, @Rn */
466 uint32_t Rn = ((ir>>8)&0xF);
467 tmp = sh4r.r[Rn];
468 CHECKWALIGN32(tmp);
469 MEM_WRITE_LONG( tmp, R0 );
470 }
471 break;
472 default:
473 UNDEF();
474 break;
475 }
476 break;
477 case 0x4:
478 { /* MOV.B Rm, @(R0, Rn) */
479 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
480 MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] );
481 }
482 break;
483 case 0x5:
484 { /* MOV.W Rm, @(R0, Rn) */
485 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
486 CHECKWALIGN16( R0 + sh4r.r[Rn] );
487 MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
488 }
489 break;
490 case 0x6:
491 { /* MOV.L Rm, @(R0, Rn) */
492 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
493 CHECKWALIGN32( R0 + sh4r.r[Rn] );
494 MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
495 }
496 break;
497 case 0x7:
498 { /* MUL.L Rm, Rn */
499 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
500 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
501 (sh4r.r[Rm] * sh4r.r[Rn]);
502 }
503 break;
504 case 0x8:
505 switch( (ir&0xFF0) >> 4 ) {
506 case 0x0:
507 { /* CLRT */
508 sh4r.t = 0;
509 }
510 break;
511 case 0x1:
512 { /* SETT */
513 sh4r.t = 1;
514 }
515 break;
516 case 0x2:
517 { /* CLRMAC */
518 sh4r.mac = 0;
519 }
520 break;
521 case 0x3:
522 { /* LDTLB */
523 /* TODO */
524 }
525 break;
526 case 0x4:
527 { /* CLRS */
528 sh4r.s = 0;
529 }
530 break;
531 case 0x5:
532 { /* SETS */
533 sh4r.s = 1;
534 }
535 break;
536 default:
537 UNDEF();
538 break;
539 }
540 break;
541 case 0x9:
542 switch( (ir&0xF0) >> 4 ) {
543 case 0x0:
544 { /* NOP */
545 /* NOP */
546 }
547 break;
548 case 0x1:
549 { /* DIV0U */
550 sh4r.m = sh4r.q = sh4r.t = 0;
551 }
552 break;
553 case 0x2:
554 { /* MOVT Rn */
555 uint32_t Rn = ((ir>>8)&0xF);
556 sh4r.r[Rn] = sh4r.t;
557 }
558 break;
559 default:
560 UNDEF();
561 break;
562 }
563 break;
564 case 0xA:
565 switch( (ir&0xF0) >> 4 ) {
566 case 0x0:
567 { /* STS MACH, Rn */
568 uint32_t Rn = ((ir>>8)&0xF);
569 sh4r.r[Rn] = (sh4r.mac>>32);
570 }
571 break;
572 case 0x1:
573 { /* STS MACL, Rn */
574 uint32_t Rn = ((ir>>8)&0xF);
575 sh4r.r[Rn] = (uint32_t)sh4r.mac;
576 }
577 break;
578 case 0x2:
579 { /* STS PR, Rn */
580 uint32_t Rn = ((ir>>8)&0xF);
581 sh4r.r[Rn] = sh4r.pr;
582 }
583 break;
584 case 0x3:
585 { /* STC SGR, Rn */
586 uint32_t Rn = ((ir>>8)&0xF);
587 CHECKPRIV();
588 sh4r.r[Rn] = sh4r.sgr;
589 }
590 break;
591 case 0x5:
592 { /* STS FPUL, Rn */
593 uint32_t Rn = ((ir>>8)&0xF);
594 sh4r.r[Rn] = sh4r.fpul;
595 }
596 break;
597 case 0x6:
598 { /* STS FPSCR, Rn */
599 uint32_t Rn = ((ir>>8)&0xF);
600 sh4r.r[Rn] = sh4r.fpscr;
601 }
602 break;
603 case 0xF:
604 { /* STC DBR, Rn */
605 uint32_t Rn = ((ir>>8)&0xF);
606 CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr;
607 }
608 break;
609 default:
610 UNDEF();
611 break;
612 }
613 break;
614 case 0xB:
615 switch( (ir&0xFF0) >> 4 ) {
616 case 0x0:
617 { /* RTS */
618 CHECKSLOTILLEGAL();
619 CHECKDEST( sh4r.pr );
620 sh4r.in_delay_slot = 1;
621 sh4r.pc = sh4r.new_pc;
622 sh4r.new_pc = sh4r.pr;
623 TRACE_RETURN( pc, sh4r.new_pc );
624 return TRUE;
625 }
626 break;
627 case 0x1:
628 { /* SLEEP */
629 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
630 sh4r.sh4_state = SH4_STATE_STANDBY;
631 } else {
632 sh4r.sh4_state = SH4_STATE_SLEEP;
633 }
634 return FALSE; /* Halt CPU */
635 }
636 break;
637 case 0x2:
638 { /* RTE */
639 CHECKPRIV();
640 CHECKDEST( sh4r.spc );
641 CHECKSLOTILLEGAL();
642 sh4r.in_delay_slot = 1;
643 sh4r.pc = sh4r.new_pc;
644 sh4r.new_pc = sh4r.spc;
645 sh4_write_sr( sh4r.ssr );
646 return TRUE;
647 }
648 break;
649 default:
650 UNDEF();
651 break;
652 }
653 break;
654 case 0xC:
655 { /* MOV.B @(R0, Rm), Rn */
656 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
657 sh4r.r[Rn] = MEM_READ_BYTE( R0 + sh4r.r[Rm] );
658 }
659 break;
660 case 0xD:
661 { /* MOV.W @(R0, Rm), Rn */
662 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
663 CHECKRALIGN16( R0 + sh4r.r[Rm] );
664 sh4r.r[Rn] = MEM_READ_WORD( R0 + sh4r.r[Rm] );
665 }
666 break;
667 case 0xE:
668 { /* MOV.L @(R0, Rm), Rn */
669 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
670 CHECKRALIGN32( R0 + sh4r.r[Rm] );
671 sh4r.r[Rn] = MEM_READ_LONG( R0 + sh4r.r[Rm] );
672 }
673 break;
674 case 0xF:
675 { /* MAC.L @Rm+, @Rn+ */
676 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
677 CHECKRALIGN32( sh4r.r[Rm] );
678 CHECKRALIGN32( sh4r.r[Rn] );
679 int64_t tmpl = SIGNEXT32(MEM_READ_LONG(sh4r.r[Rn]));
680 sh4r.r[Rn] += 4;
681 tmpl = tmpl * SIGNEXT32(MEM_READ_LONG(sh4r.r[Rm])) + sh4r.mac;
682 sh4r.r[Rm] += 4;
683 if( sh4r.s ) {
684 /* 48-bit Saturation. Yuch */
685 if( tmpl < (int64_t)0xFFFF800000000000LL )
686 tmpl = 0xFFFF800000000000LL;
687 else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
688 tmpl = 0x00007FFFFFFFFFFFLL;
689 }
690 sh4r.mac = tmpl;
691 }
692 break;
693 default:
694 UNDEF();
695 break;
696 }
697 break;
698 case 0x1:
699 { /* MOV.L Rm, @(disp, Rn) */
700 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
701 tmp = sh4r.r[Rn] + disp;
702 CHECKWALIGN32( tmp );
703 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
704 }
705 break;
706 case 0x2:
707 switch( ir&0xF ) {
708 case 0x0:
709 { /* MOV.B Rm, @Rn */
710 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
711 MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );
712 }
713 break;
714 case 0x1:
715 { /* MOV.W Rm, @Rn */
716 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
717 CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );
718 }
719 break;
720 case 0x2:
721 { /* MOV.L Rm, @Rn */
722 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
723 CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );
724 }
725 break;
726 case 0x4:
727 { /* MOV.B Rm, @-Rn */
728 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
729 sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );
730 }
731 break;
732 case 0x5:
733 { /* MOV.W Rm, @-Rn */
734 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
735 sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );
736 }
737 break;
738 case 0x6:
739 { /* MOV.L Rm, @-Rn */
740 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
741 sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );
742 }
743 break;
744 case 0x7:
745 { /* DIV0S Rm, Rn */
746 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
747 sh4r.q = sh4r.r[Rn]>>31;
748 sh4r.m = sh4r.r[Rm]>>31;
749 sh4r.t = sh4r.q ^ sh4r.m;
750 }
751 break;
752 case 0x8:
753 { /* TST Rm, Rn */
754 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
755 sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1);
756 }
757 break;
758 case 0x9:
759 { /* AND Rm, Rn */
760 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
761 sh4r.r[Rn] &= sh4r.r[Rm];
762 }
763 break;
764 case 0xA:
765 { /* XOR Rm, Rn */
766 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
767 sh4r.r[Rn] ^= sh4r.r[Rm];
768 }
769 break;
770 case 0xB:
771 { /* OR Rm, Rn */
772 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
773 sh4r.r[Rn] |= sh4r.r[Rm];
774 }
775 break;
776 case 0xC:
777 { /* CMP/STR Rm, Rn */
778 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
779 /* set T = 1 if any byte in RM & RN is the same */
780 tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
781 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
782 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
783 }
784 break;
785 case 0xD:
786 { /* XTRCT Rm, Rn */
787 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
788 sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16);
789 }
790 break;
791 case 0xE:
792 { /* MULU.W Rm, Rn */
793 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
794 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
795 (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
796 }
797 break;
798 case 0xF:
799 { /* MULS.W Rm, Rn */
800 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
801 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
802 (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
803 }
804 break;
805 default:
806 UNDEF();
807 break;
808 }
809 break;
810 case 0x3:
811 switch( ir&0xF ) {
812 case 0x0:
813 { /* CMP/EQ Rm, Rn */
814 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
815 sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 );
816 }
817 break;
818 case 0x2:
819 { /* CMP/HS Rm, Rn */
820 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
821 sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 );
822 }
823 break;
824 case 0x3:
825 { /* CMP/GE Rm, Rn */
826 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
827 sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
828 }
829 break;
830 case 0x4:
831 { /* DIV1 Rm, Rn */
832 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
833 /* This is derived from the sh4 manual with some simplifications */
834 uint32_t tmp0, tmp1, tmp2, dir;
836 dir = sh4r.q ^ sh4r.m;
837 sh4r.q = (sh4r.r[Rn] >> 31);
838 tmp2 = sh4r.r[Rm];
839 sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
840 tmp0 = sh4r.r[Rn];
841 if( dir ) {
842 sh4r.r[Rn] += tmp2;
843 tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
844 } else {
845 sh4r.r[Rn] -= tmp2;
846 tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
847 }
848 sh4r.q ^= sh4r.m ^ tmp1;
849 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
850 }
851 break;
852 case 0x5:
853 { /* DMULU.L Rm, Rn */
854 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
855 sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]);
856 }
857 break;
858 case 0x6:
859 { /* CMP/HI Rm, Rn */
860 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
861 sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 );
862 }
863 break;
864 case 0x7:
865 { /* CMP/GT Rm, Rn */
866 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
867 sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
868 }
869 break;
870 case 0x8:
871 { /* SUB Rm, Rn */
872 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
873 sh4r.r[Rn] -= sh4r.r[Rm];
874 }
875 break;
876 case 0xA:
877 { /* SUBC Rm, Rn */
878 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
879 tmp = sh4r.r[Rn];
880 sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
881 sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
882 }
883 break;
884 case 0xB:
885 UNIMP(ir); /* SUBV Rm, Rn */
886 break;
887 case 0xC:
888 { /* ADD Rm, Rn */
889 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
890 sh4r.r[Rn] += sh4r.r[Rm];
891 }
892 break;
893 case 0xD:
894 { /* DMULS.L Rm, Rn */
895 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
896 sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]);
897 }
898 break;
899 case 0xE:
900 { /* ADDC Rm, Rn */
901 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
902 tmp = sh4r.r[Rn];
903 sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
904 sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
905 }
906 break;
907 case 0xF:
908 { /* ADDV Rm, Rn */
909 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
910 tmp = sh4r.r[Rn] + sh4r.r[Rm];
911 sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
912 sh4r.r[Rn] = tmp;
913 }
914 break;
915 default:
916 UNDEF();
917 break;
918 }
919 break;
920 case 0x4:
921 switch( ir&0xF ) {
922 case 0x0:
923 switch( (ir&0xF0) >> 4 ) {
924 case 0x0:
925 { /* SHLL Rn */
926 uint32_t Rn = ((ir>>8)&0xF);
927 sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1;
928 }
929 break;
930 case 0x1:
931 { /* DT Rn */
932 uint32_t Rn = ((ir>>8)&0xF);
933 sh4r.r[Rn] --;
934 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
935 }
936 break;
937 case 0x2:
938 { /* SHAL Rn */
939 uint32_t Rn = ((ir>>8)&0xF);
940 sh4r.t = sh4r.r[Rn] >> 31;
941 sh4r.r[Rn] <<= 1;
942 }
943 break;
944 default:
945 UNDEF();
946 break;
947 }
948 break;
949 case 0x1:
950 switch( (ir&0xF0) >> 4 ) {
951 case 0x0:
952 { /* SHLR Rn */
953 uint32_t Rn = ((ir>>8)&0xF);
954 sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1;
955 }
956 break;
957 case 0x1:
958 { /* CMP/PZ Rn */
959 uint32_t Rn = ((ir>>8)&0xF);
960 sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 );
961 }
962 break;
963 case 0x2:
964 { /* SHAR Rn */
965 uint32_t Rn = ((ir>>8)&0xF);
966 sh4r.t = sh4r.r[Rn] & 0x00000001;
967 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
968 }
969 break;
970 default:
971 UNDEF();
972 break;
973 }
974 break;
975 case 0x2:
976 switch( (ir&0xF0) >> 4 ) {
977 case 0x0:
978 { /* STS.L MACH, @-Rn */
979 uint32_t Rn = ((ir>>8)&0xF);
980 sh4r.r[Rn] -= 4;
981 CHECKWALIGN32( sh4r.r[Rn] );
982 MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );
983 }
984 break;
985 case 0x1:
986 { /* STS.L MACL, @-Rn */
987 uint32_t Rn = ((ir>>8)&0xF);
988 sh4r.r[Rn] -= 4;
989 CHECKWALIGN32( sh4r.r[Rn] );
990 MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );
991 }
992 break;
993 case 0x2:
994 { /* STS.L PR, @-Rn */
995 uint32_t Rn = ((ir>>8)&0xF);
996 sh4r.r[Rn] -= 4;
997 CHECKWALIGN32( sh4r.r[Rn] );
998 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );
999 }
1000 break;
1001 case 0x3:
1002 { /* STC.L SGR, @-Rn */
1003 uint32_t Rn = ((ir>>8)&0xF);
1004 CHECKPRIV();
1005 sh4r.r[Rn] -= 4;
1006 CHECKWALIGN32( sh4r.r[Rn] );
1007 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );
1008 }
1009 break;
1010 case 0x5:
1011 { /* STS.L FPUL, @-Rn */
1012 uint32_t Rn = ((ir>>8)&0xF);
1013 sh4r.r[Rn] -= 4;
1014 CHECKWALIGN32( sh4r.r[Rn] );
1015 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );
1016 }
1017 break;
1018 case 0x6:
1019 { /* STS.L FPSCR, @-Rn */
1020 uint32_t Rn = ((ir>>8)&0xF);
1021 sh4r.r[Rn] -= 4;
1022 CHECKWALIGN32( sh4r.r[Rn] );
1023 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );
1024 }
1025 break;
1026 case 0xF:
1027 { /* STC.L DBR, @-Rn */
1028 uint32_t Rn = ((ir>>8)&0xF);
1029 CHECKPRIV();
1030 sh4r.r[Rn] -= 4;
1031 CHECKWALIGN32( sh4r.r[Rn] );
1032 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );
1033 }
1034 break;
1035 default:
1036 UNDEF();
1037 break;
1038 }
1039 break;
1040 case 0x3:
1041 switch( (ir&0x80) >> 7 ) {
1042 case 0x0:
1043 switch( (ir&0x70) >> 4 ) {
1044 case 0x0:
1045 { /* STC.L SR, @-Rn */
1046 uint32_t Rn = ((ir>>8)&0xF);
1047 CHECKPRIV();
1048 sh4r.r[Rn] -= 4;
1049 CHECKWALIGN32( sh4r.r[Rn] );
1050 MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );
1051 }
1052 break;
1053 case 0x1:
1054 { /* STC.L GBR, @-Rn */
1055 uint32_t Rn = ((ir>>8)&0xF);
1056 sh4r.r[Rn] -= 4;
1057 CHECKWALIGN32( sh4r.r[Rn] );
1058 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );
1059 }
1060 break;
1061 case 0x2:
1062 { /* STC.L VBR, @-Rn */
1063 uint32_t Rn = ((ir>>8)&0xF);
1064 CHECKPRIV();
1065 sh4r.r[Rn] -= 4;
1066 CHECKWALIGN32( sh4r.r[Rn] );
1067 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );
1068 }
1069 break;
1070 case 0x3:
1071 { /* STC.L SSR, @-Rn */
1072 uint32_t Rn = ((ir>>8)&0xF);
1073 CHECKPRIV();
1074 sh4r.r[Rn] -= 4;
1075 CHECKWALIGN32( sh4r.r[Rn] );
1076 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );
1077 }
1078 break;
1079 case 0x4:
1080 { /* STC.L SPC, @-Rn */
1081 uint32_t Rn = ((ir>>8)&0xF);
1082 CHECKPRIV();
1083 sh4r.r[Rn] -= 4;
1084 CHECKWALIGN32( sh4r.r[Rn] );
1085 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );
1086 }
1087 break;
1088 default:
1089 UNDEF();
1090 break;
1091 }
1092 break;
1093 case 0x1:
1094 { /* STC.L Rm_BANK, @-Rn */
1095 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
1096 CHECKPRIV();
1097 sh4r.r[Rn] -= 4;
1098 CHECKWALIGN32( sh4r.r[Rn] );
1099 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );
1100 }
1101 break;
1102 }
1103 break;
1104 case 0x4:
1105 switch( (ir&0xF0) >> 4 ) {
1106 case 0x0:
1107 { /* ROTL Rn */
1108 uint32_t Rn = ((ir>>8)&0xF);
1109 sh4r.t = sh4r.r[Rn] >> 31;
1110 sh4r.r[Rn] <<= 1;
1111 sh4r.r[Rn] |= sh4r.t;
1112 }
1113 break;
1114 case 0x2:
1115 { /* ROTCL Rn */
1116 uint32_t Rn = ((ir>>8)&0xF);
1117 tmp = sh4r.r[Rn] >> 31;
1118 sh4r.r[Rn] <<= 1;
1119 sh4r.r[Rn] |= sh4r.t;
1120 sh4r.t = tmp;
1121 }
1122 break;
1123 default:
1124 UNDEF();
1125 break;
1126 }
1127 break;
1128 case 0x5:
1129 switch( (ir&0xF0) >> 4 ) {
1130 case 0x0:
1131 { /* ROTR Rn */
1132 uint32_t Rn = ((ir>>8)&0xF);
1133 sh4r.t = sh4r.r[Rn] & 0x00000001;
1134 sh4r.r[Rn] >>= 1;
1135 sh4r.r[Rn] |= (sh4r.t << 31);
1136 }
1137 break;
1138 case 0x1:
1139 { /* CMP/PL Rn */
1140 uint32_t Rn = ((ir>>8)&0xF);
1141 sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 );
1142 }
1143 break;
1144 case 0x2:
1145 { /* ROTCR Rn */
1146 uint32_t Rn = ((ir>>8)&0xF);
1147 tmp = sh4r.r[Rn] & 0x00000001;
1148 sh4r.r[Rn] >>= 1;
1149 sh4r.r[Rn] |= (sh4r.t << 31 );
1150 sh4r.t = tmp;
1151 }
1152 break;
1153 default:
1154 UNDEF();
1155 break;
1156 }
1157 break;
1158 case 0x6:
1159 switch( (ir&0xF0) >> 4 ) {
1160 case 0x0:
1161 { /* LDS.L @Rm+, MACH */
1162 uint32_t Rm = ((ir>>8)&0xF);
1163 CHECKRALIGN32( sh4r.r[Rm] );
1164 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
1165 (((uint64_t)MEM_READ_LONG(sh4r.r[Rm]))<<32);
1166 sh4r.r[Rm] += 4;
1167 }
1168 break;
1169 case 0x1:
1170 { /* LDS.L @Rm+, MACL */
1171 uint32_t Rm = ((ir>>8)&0xF);
1172 CHECKRALIGN32( sh4r.r[Rm] );
1173 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
1174 (uint64_t)((uint32_t)MEM_READ_LONG(sh4r.r[Rm]));
1175 sh4r.r[Rm] += 4;
1176 }
1177 break;
1178 case 0x2:
1179 { /* LDS.L @Rm+, PR */
1180 uint32_t Rm = ((ir>>8)&0xF);
1181 CHECKRALIGN32( sh4r.r[Rm] );
1182 sh4r.pr = MEM_READ_LONG( sh4r.r[Rm] );
1183 sh4r.r[Rm] += 4;
1184 }
1185 break;
1186 case 0x3:
1187 { /* LDC.L @Rm+, SGR */
1188 uint32_t Rm = ((ir>>8)&0xF);
1189 CHECKPRIV();
1190 CHECKRALIGN32( sh4r.r[Rm] );
1191 sh4r.sgr = MEM_READ_LONG(sh4r.r[Rm]);
1192 sh4r.r[Rm] +=4;
1193 }
1194 break;
1195 case 0x5:
1196 { /* LDS.L @Rm+, FPUL */
1197 uint32_t Rm = ((ir>>8)&0xF);
1198 CHECKRALIGN32( sh4r.r[Rm] );
1199 sh4r.fpul = MEM_READ_LONG(sh4r.r[Rm]);
1200 sh4r.r[Rm] +=4;
1201 }
1202 break;
1203 case 0x6:
1204 { /* LDS.L @Rm+, FPSCR */
1205 uint32_t Rm = ((ir>>8)&0xF);
1206 CHECKRALIGN32( sh4r.r[Rm] );
1207 sh4r.fpscr = MEM_READ_LONG(sh4r.r[Rm]);
1208 sh4r.r[Rm] +=4;
1209 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
1210 }
1211 break;
1212 case 0xF:
1213 { /* LDC.L @Rm+, DBR */
1214 uint32_t Rm = ((ir>>8)&0xF);
1215 CHECKPRIV();
1216 CHECKRALIGN32( sh4r.r[Rm] );
1217 sh4r.dbr = MEM_READ_LONG(sh4r.r[Rm]);
1218 sh4r.r[Rm] +=4;
1219 }
1220 break;
1221 default:
1222 UNDEF();
1223 break;
1224 }
1225 break;
1226 case 0x7:
1227 switch( (ir&0x80) >> 7 ) {
1228 case 0x0:
1229 switch( (ir&0x70) >> 4 ) {
1230 case 0x0:
1231 { /* LDC.L @Rm+, SR */
1232 uint32_t Rm = ((ir>>8)&0xF);
1233 CHECKSLOTILLEGAL();
1234 CHECKPRIV();
1235 CHECKWALIGN32( sh4r.r[Rm] );
1236 sh4_write_sr( MEM_READ_LONG(sh4r.r[Rm]) );
1237 sh4r.r[Rm] +=4;
1238 }
1239 break;
1240 case 0x1:
1241 { /* LDC.L @Rm+, GBR */
1242 uint32_t Rm = ((ir>>8)&0xF);
1243 CHECKRALIGN32( sh4r.r[Rm] );
1244 sh4r.gbr = MEM_READ_LONG(sh4r.r[Rm]);
1245 sh4r.r[Rm] +=4;
1246 }
1247 break;
1248 case 0x2:
1249 { /* LDC.L @Rm+, VBR */
1250 uint32_t Rm = ((ir>>8)&0xF);
1251 CHECKPRIV();
1252 CHECKRALIGN32( sh4r.r[Rm] );
1253 sh4r.vbr = MEM_READ_LONG(sh4r.r[Rm]);
1254 sh4r.r[Rm] +=4;
1255 }
1256 break;
1257 case 0x3:
1258 { /* LDC.L @Rm+, SSR */
1259 uint32_t Rm = ((ir>>8)&0xF);
1260 CHECKPRIV();
1261 CHECKRALIGN32( sh4r.r[Rm] );
1262 sh4r.ssr = MEM_READ_LONG(sh4r.r[Rm]);
1263 sh4r.r[Rm] +=4;
1264 }
1265 break;
1266 case 0x4:
1267 { /* LDC.L @Rm+, SPC */
1268 uint32_t Rm = ((ir>>8)&0xF);
1269 CHECKPRIV();
1270 CHECKRALIGN32( sh4r.r[Rm] );
1271 sh4r.spc = MEM_READ_LONG(sh4r.r[Rm]);
1272 sh4r.r[Rm] +=4;
1273 }
1274 break;
1275 default:
1276 UNDEF();
1277 break;
1278 }
1279 break;
1280 case 0x1:
1281 { /* LDC.L @Rm+, Rn_BANK */
1282 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
1283 CHECKPRIV();
1284 CHECKRALIGN32( sh4r.r[Rm] );
1285 sh4r.r_bank[Rn_BANK] = MEM_READ_LONG( sh4r.r[Rm] );
1286 sh4r.r[Rm] += 4;
1287 }
1288 break;
1289 }
1290 break;
1291 case 0x8:
1292 switch( (ir&0xF0) >> 4 ) {
1293 case 0x0:
1294 { /* SHLL2 Rn */
1295 uint32_t Rn = ((ir>>8)&0xF);
1296 sh4r.r[Rn] <<= 2;
1297 }
1298 break;
1299 case 0x1:
1300 { /* SHLL8 Rn */
1301 uint32_t Rn = ((ir>>8)&0xF);
1302 sh4r.r[Rn] <<= 8;
1303 }
1304 break;
1305 case 0x2:
1306 { /* SHLL16 Rn */
1307 uint32_t Rn = ((ir>>8)&0xF);
1308 sh4r.r[Rn] <<= 16;
1309 }
1310 break;
1311 default:
1312 UNDEF();
1313 break;
1314 }
1315 break;
1316 case 0x9:
1317 switch( (ir&0xF0) >> 4 ) {
1318 case 0x0:
1319 { /* SHLR2 Rn */
1320 uint32_t Rn = ((ir>>8)&0xF);
1321 sh4r.r[Rn] >>= 2;
1322 }
1323 break;
1324 case 0x1:
1325 { /* SHLR8 Rn */
1326 uint32_t Rn = ((ir>>8)&0xF);
1327 sh4r.r[Rn] >>= 8;
1328 }
1329 break;
1330 case 0x2:
1331 { /* SHLR16 Rn */
1332 uint32_t Rn = ((ir>>8)&0xF);
1333 sh4r.r[Rn] >>= 16;
1334 }
1335 break;
1336 default:
1337 UNDEF();
1338 break;
1339 }
1340 break;
1341 case 0xA:
1342 switch( (ir&0xF0) >> 4 ) {
1343 case 0x0:
1344 { /* LDS Rm, MACH */
1345 uint32_t Rm = ((ir>>8)&0xF);
1346 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
1347 (((uint64_t)sh4r.r[Rm])<<32);
1348 }
1349 break;
1350 case 0x1:
1351 { /* LDS Rm, MACL */
1352 uint32_t Rm = ((ir>>8)&0xF);
1353 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
1354 (uint64_t)((uint32_t)(sh4r.r[Rm]));
1355 }
1356 break;
1357 case 0x2:
1358 { /* LDS Rm, PR */
1359 uint32_t Rm = ((ir>>8)&0xF);
1360 sh4r.pr = sh4r.r[Rm];
1361 }
1362 break;
1363 case 0x3:
1364 { /* LDC Rm, SGR */
1365 uint32_t Rm = ((ir>>8)&0xF);
1366 CHECKPRIV();
1367 sh4r.sgr = sh4r.r[Rm];
1368 }
1369 break;
1370 case 0x5:
1371 { /* LDS Rm, FPUL */
1372 uint32_t Rm = ((ir>>8)&0xF);
1373 sh4r.fpul = sh4r.r[Rm];
1374 }
1375 break;
1376 case 0x6:
1377 { /* LDS Rm, FPSCR */
1378 uint32_t Rm = ((ir>>8)&0xF);
1379 sh4r.fpscr = sh4r.r[Rm];
1380 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
1381 }
1382 break;
1383 case 0xF:
1384 { /* LDC Rm, DBR */
1385 uint32_t Rm = ((ir>>8)&0xF);
1386 CHECKPRIV();
1387 sh4r.dbr = sh4r.r[Rm];
1388 }
1389 break;
1390 default:
1391 UNDEF();
1392 break;
1393 }
1394 break;
1395 case 0xB:
1396 switch( (ir&0xF0) >> 4 ) {
1397 case 0x0:
1398 { /* JSR @Rn */
1399 uint32_t Rn = ((ir>>8)&0xF);
1400 CHECKDEST( sh4r.r[Rn] );
1401 CHECKSLOTILLEGAL();
1402 sh4r.in_delay_slot = 1;
1403 sh4r.pc = sh4r.new_pc;
1404 sh4r.new_pc = sh4r.r[Rn];
1405 sh4r.pr = pc + 4;
1406 TRACE_CALL( pc, sh4r.new_pc );
1407 return TRUE;
1408 }
1409 break;
1410 case 0x1:
1411 { /* TAS.B @Rn */
1412 uint32_t Rn = ((ir>>8)&0xF);
1413 tmp = MEM_READ_BYTE( sh4r.r[Rn] );
1414 sh4r.t = ( tmp == 0 ? 1 : 0 );
1415 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
1416 }
1417 break;
1418 case 0x2:
1419 { /* JMP @Rn */
1420 uint32_t Rn = ((ir>>8)&0xF);
1421 CHECKDEST( sh4r.r[Rn] );
1422 CHECKSLOTILLEGAL();
1423 sh4r.in_delay_slot = 1;
1424 sh4r.pc = sh4r.new_pc;
1425 sh4r.new_pc = sh4r.r[Rn];
1426 return TRUE;
1427 }
1428 break;
1429 default:
1430 UNDEF();
1431 break;
1432 }
1433 break;
1434 case 0xC:
1435 { /* SHAD Rm, Rn */
1436 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1437 tmp = sh4r.r[Rm];
1438 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
1439 else if( (tmp & 0x1F) == 0 )
1440 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
1441 else
1442 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
1443 }
1444 break;
1445 case 0xD:
1446 { /* SHLD Rm, Rn */
1447 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1448 tmp = sh4r.r[Rm];
1449 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
1450 else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
1451 else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
1452 }
1453 break;
1454 case 0xE:
1455 switch( (ir&0x80) >> 7 ) {
1456 case 0x0:
1457 switch( (ir&0x70) >> 4 ) {
1458 case 0x0:
1459 { /* LDC Rm, SR */
1460 uint32_t Rm = ((ir>>8)&0xF);
1461 CHECKSLOTILLEGAL();
1462 CHECKPRIV();
1463 sh4_write_sr( sh4r.r[Rm] );
1464 }
1465 break;
1466 case 0x1:
1467 { /* LDC Rm, GBR */
1468 uint32_t Rm = ((ir>>8)&0xF);
1469 sh4r.gbr = sh4r.r[Rm];
1470 }
1471 break;
1472 case 0x2:
1473 { /* LDC Rm, VBR */
1474 uint32_t Rm = ((ir>>8)&0xF);
1475 CHECKPRIV();
1476 sh4r.vbr = sh4r.r[Rm];
1477 }
1478 break;
1479 case 0x3:
1480 { /* LDC Rm, SSR */
1481 uint32_t Rm = ((ir>>8)&0xF);
1482 CHECKPRIV();
1483 sh4r.ssr = sh4r.r[Rm];
1484 }
1485 break;
1486 case 0x4:
1487 { /* LDC Rm, SPC */
1488 uint32_t Rm = ((ir>>8)&0xF);
1489 CHECKPRIV();
1490 sh4r.spc = sh4r.r[Rm];
1491 }
1492 break;
1493 default:
1494 UNDEF();
1495 break;
1496 }
1497 break;
1498 case 0x1:
1499 { /* LDC Rm, Rn_BANK */
1500 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
1501 CHECKPRIV();
1502 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
1503 }
1504 break;
1505 }
1506 break;
1507 case 0xF:
1508 { /* MAC.W @Rm+, @Rn+ */
1509 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1510 CHECKRALIGN16( sh4r.r[Rn] );
1511 CHECKRALIGN16( sh4r.r[Rm] );
1512 int32_t stmp = SIGNEXT16(MEM_READ_WORD(sh4r.r[Rn]));
1513 sh4r.r[Rn] += 2;
1514 stmp = stmp * SIGNEXT16(MEM_READ_WORD(sh4r.r[Rm]));
1515 sh4r.r[Rm] += 2;
1516 if( sh4r.s ) {
1517 int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
1518 if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
1519 sh4r.mac = 0x000000017FFFFFFFLL;
1520 } else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
1521 sh4r.mac = 0x0000000180000000LL;
1522 } else {
1523 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
1524 ((uint32_t)(sh4r.mac + stmp));
1525 }
1526 } else {
1527 sh4r.mac += SIGNEXT32(stmp);
1528 }
1529 }
1530 break;
1531 }
1532 break;
1533 case 0x5:
1534 { /* MOV.L @(disp, Rm), Rn */
1535 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
1536 tmp = sh4r.r[Rm] + disp;
1537 CHECKRALIGN32( tmp );
1538 sh4r.r[Rn] = MEM_READ_LONG( tmp );
1539 }
1540 break;
1541 case 0x6:
1542 switch( ir&0xF ) {
1543 case 0x0:
1544 { /* MOV.B @Rm, Rn */
1545 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1546 sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] );
1547 }
1548 break;
1549 case 0x1:
1550 { /* MOV.W @Rm, Rn */
1551 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1552 CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] );
1553 }
1554 break;
1555 case 0x2:
1556 { /* MOV.L @Rm, Rn */
1557 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1558 CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] );
1559 }
1560 break;
1561 case 0x3:
1562 { /* MOV Rm, Rn */
1563 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1564 sh4r.r[Rn] = sh4r.r[Rm];
1565 }
1566 break;
1567 case 0x4:
1568 { /* MOV.B @Rm+, Rn */
1569 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1570 sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); sh4r.r[Rm] ++;
1571 }
1572 break;
1573 case 0x5:
1574 { /* MOV.W @Rm+, Rn */
1575 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1576 CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); sh4r.r[Rm] += 2;
1577 }
1578 break;
1579 case 0x6:
1580 { /* MOV.L @Rm+, Rn */
1581 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1582 CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); sh4r.r[Rm] += 4;
1583 }
1584 break;
1585 case 0x7:
1586 { /* NOT Rm, Rn */
1587 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1588 sh4r.r[Rn] = ~sh4r.r[Rm];
1589 }
1590 break;
1591 case 0x8:
1592 { /* SWAP.B Rm, Rn */
1593 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1594 sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8);
1595 }
1596 break;
1597 case 0x9:
1598 { /* SWAP.W Rm, Rn */
1599 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1600 sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16);
1601 }
1602 break;
1603 case 0xA:
1604 { /* NEGC Rm, Rn */
1605 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1606 tmp = 0 - sh4r.r[Rm];
1607 sh4r.r[Rn] = tmp - sh4r.t;
1608 sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
1609 }
1610 break;
1611 case 0xB:
1612 { /* NEG Rm, Rn */
1613 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1614 sh4r.r[Rn] = 0 - sh4r.r[Rm];
1615 }
1616 break;
1617 case 0xC:
1618 { /* EXTU.B Rm, Rn */
1619 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1620 sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF;
1621 }
1622 break;
1623 case 0xD:
1624 { /* EXTU.W Rm, Rn */
1625 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1626 sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF;
1627 }
1628 break;
1629 case 0xE:
1630 { /* EXTS.B Rm, Rn */
1631 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1632 sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF );
1633 }
1634 break;
1635 case 0xF:
1636 { /* EXTS.W Rm, Rn */
1637 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1638 sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF );
1639 }
1640 break;
1641 }
1642 break;
1643 case 0x7:
1644 { /* ADD #imm, Rn */
1645 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
1646 sh4r.r[Rn] += imm;
1647 }
1648 break;
1649 case 0x8:
1650 switch( (ir&0xF00) >> 8 ) {
1651 case 0x0:
1652 { /* MOV.B R0, @(disp, Rn) */
1653 uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
1654 MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 );
1655 }
1656 break;
1657 case 0x1:
1658 { /* MOV.W R0, @(disp, Rn) */
1659 uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
1660 tmp = sh4r.r[Rn] + disp;
1661 CHECKWALIGN16( tmp );
1662 MEM_WRITE_WORD( tmp, R0 );
1663 }
1664 break;
1665 case 0x4:
1666 { /* MOV.B @(disp, Rm), R0 */
1667 uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
1668 R0 = MEM_READ_BYTE( sh4r.r[Rm] + disp );
1669 }
1670 break;
1671 case 0x5:
1672 { /* MOV.W @(disp, Rm), R0 */
1673 uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
1674 tmp = sh4r.r[Rm] + disp;
1675 CHECKRALIGN16( tmp );
1676 R0 = MEM_READ_WORD( tmp );
1677 }
1678 break;
1679 case 0x8:
1680 { /* CMP/EQ #imm, R0 */
1681 int32_t imm = SIGNEXT8(ir&0xFF);
1682 sh4r.t = ( R0 == imm ? 1 : 0 );
1683 }
1684 break;
1685 case 0x9:
1686 { /* BT disp */
1687 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1688 CHECKSLOTILLEGAL();
1689 if( sh4r.t ) {
1690 CHECKDEST( sh4r.pc + disp + 4 )
1691 sh4r.pc += disp + 4;
1692 sh4r.new_pc = sh4r.pc + 2;
1693 return TRUE;
1694 }
1695 }
1696 break;
1697 case 0xB:
1698 { /* BF disp */
1699 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1700 CHECKSLOTILLEGAL();
1701 if( !sh4r.t ) {
1702 CHECKDEST( sh4r.pc + disp + 4 )
1703 sh4r.pc += disp + 4;
1704 sh4r.new_pc = sh4r.pc + 2;
1705 return TRUE;
1706 }
1707 }
1708 break;
1709 case 0xD:
1710 { /* BT/S disp */
1711 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1712 CHECKSLOTILLEGAL();
1713 if( sh4r.t ) {
1714 CHECKDEST( sh4r.pc + disp + 4 )
1715 sh4r.in_delay_slot = 1;
1716 sh4r.pc = sh4r.new_pc;
1717 sh4r.new_pc = pc + disp + 4;
1718 sh4r.in_delay_slot = 1;
1719 return TRUE;
1720 }
1721 }
1722 break;
1723 case 0xF:
1724 { /* BF/S disp */
1725 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1726 CHECKSLOTILLEGAL();
1727 if( !sh4r.t ) {
1728 CHECKDEST( sh4r.pc + disp + 4 )
1729 sh4r.in_delay_slot = 1;
1730 sh4r.pc = sh4r.new_pc;
1731 sh4r.new_pc = pc + disp + 4;
1732 return TRUE;
1733 }
1734 }
1735 break;
1736 default:
1737 UNDEF();
1738 break;
1739 }
1740 break;
1741 case 0x9:
1742 { /* MOV.W @(disp, PC), Rn */
1743 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;
1744 CHECKSLOTILLEGAL();
1745 tmp = pc + 4 + disp;
1746 sh4r.r[Rn] = MEM_READ_WORD( tmp );
1747 }
1748 break;
1749 case 0xA:
1750 { /* BRA disp */
1751 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
1752 CHECKSLOTILLEGAL();
1753 CHECKDEST( sh4r.pc + disp + 4 );
1754 sh4r.in_delay_slot = 1;
1755 sh4r.pc = sh4r.new_pc;
1756 sh4r.new_pc = pc + 4 + disp;
1757 return TRUE;
1758 }
1759 break;
1760 case 0xB:
1761 { /* BSR disp */
1762 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
1763 CHECKDEST( sh4r.pc + disp + 4 );
1764 CHECKSLOTILLEGAL();
1765 sh4r.in_delay_slot = 1;
1766 sh4r.pr = pc + 4;
1767 sh4r.pc = sh4r.new_pc;
1768 sh4r.new_pc = pc + 4 + disp;
1769 TRACE_CALL( pc, sh4r.new_pc );
1770 return TRUE;
1771 }
1772 break;
1773 case 0xC:
1774 switch( (ir&0xF00) >> 8 ) {
1775 case 0x0:
1776 { /* MOV.B R0, @(disp, GBR) */
1777 uint32_t disp = (ir&0xFF);
1778 MEM_WRITE_BYTE( sh4r.gbr + disp, R0 );
1779 }
1780 break;
1781 case 0x1:
1782 { /* MOV.W R0, @(disp, GBR) */
1783 uint32_t disp = (ir&0xFF)<<1;
1784 tmp = sh4r.gbr + disp;
1785 CHECKWALIGN16( tmp );
1786 MEM_WRITE_WORD( tmp, R0 );
1787 }
1788 break;
1789 case 0x2:
1790 { /* MOV.L R0, @(disp, GBR) */
1791 uint32_t disp = (ir&0xFF)<<2;
1792 tmp = sh4r.gbr + disp;
1793 CHECKWALIGN32( tmp );
1794 MEM_WRITE_LONG( tmp, R0 );
1795 }
1796 break;
1797 case 0x3:
1798 { /* TRAPA #imm */
1799 uint32_t imm = (ir&0xFF);
1800 CHECKSLOTILLEGAL();
1801 MMIO_WRITE( MMU, TRA, imm<<2 );
1802 sh4r.pc += 2;
1803 sh4_raise_exception( EXC_TRAP );
1804 }
1805 break;
1806 case 0x4:
1807 { /* MOV.B @(disp, GBR), R0 */
1808 uint32_t disp = (ir&0xFF);
1809 R0 = MEM_READ_BYTE( sh4r.gbr + disp );
1810 }
1811 break;
1812 case 0x5:
1813 { /* MOV.W @(disp, GBR), R0 */
1814 uint32_t disp = (ir&0xFF)<<1;
1815 tmp = sh4r.gbr + disp;
1816 CHECKRALIGN16( tmp );
1817 R0 = MEM_READ_WORD( tmp );
1818 }
1819 break;
1820 case 0x6:
1821 { /* MOV.L @(disp, GBR), R0 */
1822 uint32_t disp = (ir&0xFF)<<2;
1823 tmp = sh4r.gbr + disp;
1824 CHECKRALIGN32( tmp );
1825 R0 = MEM_READ_LONG( tmp );
1826 }
1827 break;
1828 case 0x7:
1829 { /* MOVA @(disp, PC), R0 */
1830 uint32_t disp = (ir&0xFF)<<2;
1831 CHECKSLOTILLEGAL();
1832 R0 = (pc&0xFFFFFFFC) + disp + 4;
1833 }
1834 break;
1835 case 0x8:
1836 { /* TST #imm, R0 */
1837 uint32_t imm = (ir&0xFF);
1838 sh4r.t = (R0 & imm ? 0 : 1);
1839 }
1840 break;
1841 case 0x9:
1842 { /* AND #imm, R0 */
1843 uint32_t imm = (ir&0xFF);
1844 R0 &= imm;
1845 }
1846 break;
1847 case 0xA:
1848 { /* XOR #imm, R0 */
1849 uint32_t imm = (ir&0xFF);
1850 R0 ^= imm;
1851 }
1852 break;
1853 case 0xB:
1854 { /* OR #imm, R0 */
1855 uint32_t imm = (ir&0xFF);
1856 R0 |= imm;
1857 }
1858 break;
1859 case 0xC:
1860 { /* TST.B #imm, @(R0, GBR) */
1861 uint32_t imm = (ir&0xFF);
1862 sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & imm ? 0 : 1 );
1863 }
1864 break;
1865 case 0xD:
1866 { /* AND.B #imm, @(R0, GBR) */
1867 uint32_t imm = (ir&0xFF);
1868 MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & MEM_READ_BYTE(R0 + sh4r.gbr) );
1869 }
1870 break;
1871 case 0xE:
1872 { /* XOR.B #imm, @(R0, GBR) */
1873 uint32_t imm = (ir&0xFF);
1874 MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
1875 }
1876 break;
1877 case 0xF:
1878 { /* OR.B #imm, @(R0, GBR) */
1879 uint32_t imm = (ir&0xFF);
1880 MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | MEM_READ_BYTE(R0 + sh4r.gbr) );
1881 }
1882 break;
1883 }
1884 break;
1885 case 0xD:
1886 { /* MOV.L @(disp, PC), Rn */
1887 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;
1888 CHECKSLOTILLEGAL();
1889 tmp = (pc&0xFFFFFFFC) + disp + 4;
1890 sh4r.r[Rn] = MEM_READ_LONG( tmp );
1891 }
1892 break;
1893 case 0xE:
1894 { /* MOV #imm, Rn */
1895 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
1896 sh4r.r[Rn] = imm;
1897 }
1898 break;
1899 case 0xF:
1900 switch( ir&0xF ) {
1901 case 0x0:
1902 { /* FADD FRm, FRn */
1903 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1904 CHECKFPUEN();
1905 if( IS_FPU_DOUBLEPREC() ) {
1906 DR(FRn) += DR(FRm);
1907 } else {
1908 FR(FRn) += FR(FRm);
1909 }
1910 }
1911 break;
1912 case 0x1:
1913 { /* FSUB FRm, FRn */
1914 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1915 CHECKFPUEN();
1916 if( IS_FPU_DOUBLEPREC() ) {
1917 DR(FRn) -= DR(FRm);
1918 } else {
1919 FR(FRn) -= FR(FRm);
1920 }
1921 }
1922 break;
1923 case 0x2:
1924 { /* FMUL FRm, FRn */
1925 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1926 CHECKFPUEN();
1927 if( IS_FPU_DOUBLEPREC() ) {
1928 DR(FRn) *= DR(FRm);
1929 } else {
1930 FR(FRn) *= FR(FRm);
1931 }
1932 }
1933 break;
1934 case 0x3:
1935 { /* FDIV FRm, FRn */
1936 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1937 CHECKFPUEN();
1938 if( IS_FPU_DOUBLEPREC() ) {
1939 DR(FRn) /= DR(FRm);
1940 } else {
1941 FR(FRn) /= FR(FRm);
1942 }
1943 }
1944 break;
1945 case 0x4:
1946 { /* FCMP/EQ FRm, FRn */
1947 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1948 CHECKFPUEN();
1949 if( IS_FPU_DOUBLEPREC() ) {
1950 sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
1951 } else {
1952 sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
1953 }
1954 }
1955 break;
1956 case 0x5:
1957 { /* FCMP/GT FRm, FRn */
1958 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1959 CHECKFPUEN();
1960 if( IS_FPU_DOUBLEPREC() ) {
1961 sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
1962 } else {
1963 sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
1964 }
1965 }
1966 break;
1967 case 0x6:
1968 { /* FMOV @(R0, Rm), FRn */
1969 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1970 MEM_FP_READ( sh4r.r[Rm] + R0, FRn );
1971 }
1972 break;
1973 case 0x7:
1974 { /* FMOV FRm, @(R0, Rn) */
1975 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1976 MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm );
1977 }
1978 break;
1979 case 0x8:
1980 { /* FMOV @Rm, FRn */
1981 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1982 MEM_FP_READ( sh4r.r[Rm], FRn );
1983 }
1984 break;
1985 case 0x9:
1986 { /* FMOV @Rm+, FRn */
1987 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1988 MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH;
1989 }
1990 break;
1991 case 0xA:
1992 { /* FMOV FRm, @Rn */
1993 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1994 MEM_FP_WRITE( sh4r.r[Rn], FRm );
1995 }
1996 break;
1997 case 0xB:
1998 { /* FMOV FRm, @-Rn */
1999 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
2000 sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm );
2001 }
2002 break;
2003 case 0xC:
2004 { /* FMOV FRm, FRn */
2005 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
2006 if( IS_FPU_DOUBLESIZE() )
2007 DR(FRn) = DR(FRm);
2008 else
2009 FR(FRn) = FR(FRm);
2010 }
2011 break;
2012 case 0xD:
2013 switch( (ir&0xF0) >> 4 ) {
2014 case 0x0:
2015 { /* FSTS FPUL, FRn */
2016 uint32_t FRn = ((ir>>8)&0xF);
2017 CHECKFPUEN(); FR(FRn) = FPULf;
2018 }
2019 break;
2020 case 0x1:
2021 { /* FLDS FRm, FPUL */
2022 uint32_t FRm = ((ir>>8)&0xF);
2023 CHECKFPUEN(); FPULf = FR(FRm);
2024 }
2025 break;
2026 case 0x2:
2027 { /* FLOAT FPUL, FRn */
2028 uint32_t FRn = ((ir>>8)&0xF);
2029 CHECKFPUEN();
2030 if( IS_FPU_DOUBLEPREC() ) {
2031 if( FRn&1 ) { // No, really...
2032 dtmp = (double)FPULi;
2033 FR(FRn) = *(((float *)&dtmp)+1);
2034 } else {
2035 DRF(FRn>>1) = (double)FPULi;
2036 }
2037 } else {
2038 FR(FRn) = (float)FPULi;
2039 }
2040 }
2041 break;
2042 case 0x3:
2043 { /* FTRC FRm, FPUL */
2044 uint32_t FRm = ((ir>>8)&0xF);
2045 CHECKFPUEN();
2046 if( IS_FPU_DOUBLEPREC() ) {
2047 if( FRm&1 ) {
2048 dtmp = 0;
2049 *(((float *)&dtmp)+1) = FR(FRm);
2050 } else {
2051 dtmp = DRF(FRm>>1);
2052 }
2053 if( dtmp >= MAX_INTF )
2054 FPULi = MAX_INT;
2055 else if( dtmp <= MIN_INTF )
2056 FPULi = MIN_INT;
2057 else
2058 FPULi = (int32_t)dtmp;
2059 } else {
2060 ftmp = FR(FRm);
2061 if( ftmp >= MAX_INTF )
2062 FPULi = MAX_INT;
2063 else if( ftmp <= MIN_INTF )
2064 FPULi = MIN_INT;
2065 else
2066 FPULi = (int32_t)ftmp;
2067 }
2068 }
2069 break;
2070 case 0x4:
2071 { /* FNEG FRn */
2072 uint32_t FRn = ((ir>>8)&0xF);
2073 CHECKFPUEN();
2074 if( IS_FPU_DOUBLEPREC() ) {
2075 DR(FRn) = -DR(FRn);
2076 } else {
2077 FR(FRn) = -FR(FRn);
2078 }
2079 }
2080 break;
2081 case 0x5:
2082 { /* FABS FRn */
2083 uint32_t FRn = ((ir>>8)&0xF);
2084 CHECKFPUEN();
2085 if( IS_FPU_DOUBLEPREC() ) {
2086 DR(FRn) = fabs(DR(FRn));
2087 } else {
2088 FR(FRn) = fabsf(FR(FRn));
2089 }
2090 }
2091 break;
2092 case 0x6:
2093 { /* FSQRT FRn */
2094 uint32_t FRn = ((ir>>8)&0xF);
2095 CHECKFPUEN();
2096 if( IS_FPU_DOUBLEPREC() ) {
2097 DR(FRn) = sqrt(DR(FRn));
2098 } else {
2099 FR(FRn) = sqrtf(FR(FRn));
2100 }
2101 }
2102 break;
2103 case 0x7:
2104 { /* FSRRA FRn */
2105 uint32_t FRn = ((ir>>8)&0xF);
2106 CHECKFPUEN();
2107 if( !IS_FPU_DOUBLEPREC() ) {
2108 FR(FRn) = 1.0/sqrtf(FR(FRn));
2109 }
2110 }
2111 break;
2112 case 0x8:
2113 { /* FLDI0 FRn */
2114 uint32_t FRn = ((ir>>8)&0xF);
2115 CHECKFPUEN();
2116 if( IS_FPU_DOUBLEPREC() ) {
2117 DR(FRn) = 0.0;
2118 } else {
2119 FR(FRn) = 0.0;
2120 }
2121 }
2122 break;
2123 case 0x9:
2124 { /* FLDI1 FRn */
2125 uint32_t FRn = ((ir>>8)&0xF);
2126 CHECKFPUEN();
2127 if( IS_FPU_DOUBLEPREC() ) {
2128 DR(FRn) = 1.0;
2129 } else {
2130 FR(FRn) = 1.0;
2131 }
2132 }
2133 break;
2134 case 0xA:
2135 { /* FCNVSD FPUL, FRn */
2136 uint32_t FRn = ((ir>>8)&0xF);
2137 CHECKFPUEN();
2138 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
2139 DR(FRn) = (double)FPULf;
2140 }
2141 }
2142 break;
2143 case 0xB:
2144 { /* FCNVDS FRm, FPUL */
2145 uint32_t FRm = ((ir>>8)&0xF);
2146 CHECKFPUEN();
2147 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
2148 FPULf = (float)DR(FRm);
2149 }
2150 }
2151 break;
2152 case 0xE:
2153 { /* FIPR FVm, FVn */
2154 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);
2155 CHECKFPUEN();
2156 if( !IS_FPU_DOUBLEPREC() ) {
2157 int tmp2 = FVn<<2;
2158 tmp = FVm<<2;
2159 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
2160 FR(tmp+1)*FR(tmp2+1) +
2161 FR(tmp+2)*FR(tmp2+2) +
2162 FR(tmp+3)*FR(tmp2+3);
2163 }
2164 }
2165 break;
2166 case 0xF:
2167 switch( (ir&0x100) >> 8 ) {
2168 case 0x0:
2169 { /* FSCA FPUL, FRn */
2170 uint32_t FRn = ((ir>>9)&0x7)<<1;
2171 CHECKFPUEN();
2172 if( !IS_FPU_DOUBLEPREC() ) {
2173 sh4_fsca( FPULi, &(DRF(FRn>>1)) );
2174 /*
2175 float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
2176 FR(FRn) = sinf(angle);
2177 FR((FRn)+1) = cosf(angle);
2178 */
2179 }
2180 }
2181 break;
2182 case 0x1:
2183 switch( (ir&0x200) >> 9 ) {
2184 case 0x0:
2185 { /* FTRV XMTRX, FVn */
2186 uint32_t FVn = ((ir>>10)&0x3);
2187 CHECKFPUEN();
2188 if( !IS_FPU_DOUBLEPREC() ) {
2189 sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);
2190 /*
2191 tmp = FVn<<2;
2192 float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];
2193 float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
2194 FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +
2195 xf[9]*fv[2] + xf[13]*fv[3];
2196 FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +
2197 xf[8]*fv[2] + xf[12]*fv[3];
2198 FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +
2199 xf[11]*fv[2] + xf[15]*fv[3];
2200 FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +
2201 xf[10]*fv[2] + xf[14]*fv[3];
2202 */
2203 }
2204 }
2205 break;
2206 case 0x1:
2207 switch( (ir&0xC00) >> 10 ) {
2208 case 0x0:
2209 { /* FSCHG */
2210 CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ;
2211 }
2212 break;
2213 case 0x2:
2214 { /* FRCHG */
2215 CHECKFPUEN();
2216 sh4r.fpscr ^= FPSCR_FR;
2217 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
2218 }
2219 break;
2220 case 0x3:
2221 { /* UNDEF */
2222 UNDEF(ir);
2223 }
2224 break;
2225 default:
2226 UNDEF();
2227 break;
2228 }
2229 break;
2230 }
2231 break;
2232 }
2233 break;
2234 default:
2235 UNDEF();
2236 break;
2237 }
2238 break;
2239 case 0xE:
2240 { /* FMAC FR0, FRm, FRn */
2241 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
2242 CHECKFPUEN();
2243 if( IS_FPU_DOUBLEPREC() ) {
2244 DR(FRn) += DR(FRm)*DR(0);
2245 } else {
2246 FR(FRn) += FR(FRm)*FR(0);
2247 }
2248 }
2249 break;
2250 default:
2251 UNDEF();
2252 break;
2253 }
2254 break;
2255 }
2257 sh4r.pc = sh4r.new_pc;
2258 sh4r.new_pc += 2;
2259 sh4r.in_delay_slot = 0;
2260 return TRUE;
2261 }
.