Search
lxdream.org :: lxdream/src/sh4/sh4core.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/sh4core.c
changeset 227:1b98af7fc601
prev208:ad290228eea1
next229:f27eb26ccdd2
author nkeynes
date Sat Sep 23 11:38:41 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Commit implementation of ADDV
view annotate diff log raw
     1 /**
     2  * $Id: sh4core.c,v 1.31 2006-09-23 11:38:41 nkeynes Exp $
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "sh4/sh4core.h"
    24 #include "sh4/sh4mmio.h"
    25 #include "sh4/intc.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "syscall.h"
    30 #define SH4_CALLTRACE 1
    32 #define MAX_INT 0x7FFFFFFF
    33 #define MIN_INT 0x80000000
    34 #define MAX_INTF 2147483647.0
    35 #define MIN_INTF -2147483648.0
    37 /* CPU-generated exception code/vector pairs */
    38 #define EXC_POWER_RESET  0x000 /* vector special */
    39 #define EXC_MANUAL_RESET 0x020
    40 #define EXC_READ_ADDR_ERR 0x0E0
    41 #define EXC_WRITE_ADDR_ERR 0x100
    42 #define EXC_SLOT_ILLEGAL 0x1A0
    43 #define EXC_ILLEGAL      0x180
    44 #define EXV_ILLEGAL      0x100
    45 #define EXC_TRAP         0x160
    46 #define EXV_TRAP         0x100
    47 #define EXC_FPDISABLE    0x800
    48 #define EXV_FPDISABLE    0x100
    50 /********************** SH4 Module Definition ****************************/
    52 void sh4_init( void );
    53 void sh4_reset( void );
    54 uint32_t sh4_run_slice( uint32_t );
    55 void sh4_start( void );
    56 void sh4_stop( void );
    57 void sh4_save_state( FILE *f );
    58 int sh4_load_state( FILE *f );
    60 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    61 				       NULL, sh4_run_slice, sh4_stop,
    62 				       sh4_save_state, sh4_load_state };
    64 struct sh4_registers sh4r;
    66 void sh4_init(void)
    67 {
    68     register_io_regions( mmio_list_sh4mmio );
    69     mmu_init();
    70     sh4_reset();
    71 }
    73 void sh4_reset(void)
    74 {
    75     /* zero everything out, for the sake of having a consistent state. */
    76     memset( &sh4r, 0, sizeof(sh4r) );
    78     /* Resume running if we were halted */
    79     sh4r.sh4_state = SH4_STATE_RUNNING;
    81     sh4r.pc    = 0xA0000000;
    82     sh4r.new_pc= 0xA0000002;
    83     sh4r.vbr   = 0x00000000;
    84     sh4r.fpscr = 0x00040001;
    85     sh4r.sr    = 0x700000F0;
    87     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
    88     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
    90     /* Peripheral modules */
    91     INTC_reset();
    92     TMU_reset();
    93     SCIF_reset();
    94 }
    96 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    97 static int sh4_breakpoint_count = 0;
    99 void sh4_set_breakpoint( uint32_t pc, int type )
   100 {
   101     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   102     sh4_breakpoints[sh4_breakpoint_count].type = type;
   103     sh4_breakpoint_count++;
   104 }
   106 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
   107 {
   108     int i;
   110     for( i=0; i<sh4_breakpoint_count; i++ ) {
   111 	if( sh4_breakpoints[i].address == pc && 
   112 	    sh4_breakpoints[i].type == type ) {
   113 	    while( ++i < sh4_breakpoint_count ) {
   114 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   115 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   116 	    }
   117 	    sh4_breakpoint_count--;
   118 	    return TRUE;
   119 	}
   120     }
   121     return FALSE;
   122 }
   124 int sh4_get_breakpoint( uint32_t pc )
   125 {
   126     int i;
   127     for( i=0; i<sh4_breakpoint_count; i++ ) {
   128 	if( sh4_breakpoints[i].address == pc )
   129 	    return sh4_breakpoints[i].type;
   130     }
   131     return 0;
   132 }
   134 uint32_t sh4_run_slice( uint32_t nanosecs ) 
   135 {
   136     int target = sh4r.icount + nanosecs / sh4_cpu_period;
   137     int start = sh4r.icount;
   138     int i;
   140     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
   141 	if( sh4r.int_pending != 0 )
   142 	    sh4r.sh4_state = SH4_STATE_RUNNING;;
   143     }
   145     for( sh4r.slice_cycle = 0; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
   146 	if( !sh4_execute_instruction() )
   147 	    break;
   148 #ifdef ENABLE_DEBUG_MODE
   149 	for( i=0; i<sh4_breakpoint_count; i++ ) {
   150 	    if( sh4_breakpoints[i].address == sh4r.pc ) {
   151 		break;
   152 	    }
   153 	}
   154 	if( i != sh4_breakpoint_count ) {
   155 	    dreamcast_stop();
   156 	    if( sh4_breakpoints[i].type == BREAK_ONESHOT )
   157 		sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
   158 	    break;
   159 	}
   160 #endif	
   161     }
   163     /* If we aborted early, but the cpu is still technically running,
   164      * we're doing a hard abort - cut the timeslice back to what we
   165      * actually executed
   166      */
   167     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   168 	nanosecs = sh4r.slice_cycle;
   169     }
   170     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   171 	TMU_run_slice( nanosecs );
   172 	SCIF_run_slice( nanosecs );
   173     }
   174     sh4r.icount += sh4r.slice_cycle / sh4_cpu_period;
   175     return nanosecs;
   176 }
   178 void sh4_stop(void)
   179 {
   181 }
   183 void sh4_save_state( FILE *f )
   184 {
   185     fwrite( &sh4r, sizeof(sh4r), 1, f );
   186     INTC_save_state( f );
   187     TMU_save_state( f );
   188     SCIF_save_state( f );
   189 }
   191 int sh4_load_state( FILE * f )
   192 {
   193     fread( &sh4r, sizeof(sh4r), 1, f );
   194     INTC_load_state( f );
   195     TMU_load_state( f );
   196     return SCIF_load_state( f );
   197 }
   199 /********************** SH4 emulation core  ****************************/
   201 void sh4_set_pc( int pc )
   202 {
   203     sh4r.pc = pc;
   204     sh4r.new_pc = pc+2;
   205 }
   207 #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop();  return FALSE; }while(0)
   208 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
   210 #if(SH4_CALLTRACE == 1)
   211 #define MAX_CALLSTACK 32
   212 static struct call_stack {
   213     sh4addr_t call_addr;
   214     sh4addr_t target_addr;
   215     sh4addr_t stack_pointer;
   216 } call_stack[MAX_CALLSTACK];
   218 static int call_stack_depth = 0;
   219 int sh4_call_trace_on = 0;
   221 static inline trace_call( sh4addr_t source, sh4addr_t dest ) 
   222 {
   223     if( call_stack_depth < MAX_CALLSTACK ) {
   224 	call_stack[call_stack_depth].call_addr = source;
   225 	call_stack[call_stack_depth].target_addr = dest;
   226 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   227     }
   228     call_stack_depth++;
   229 }
   231 static inline trace_return( sh4addr_t source, sh4addr_t dest )
   232 {
   233     if( call_stack_depth > 0 ) {
   234 	call_stack_depth--;
   235     }
   236 }
   238 void fprint_stack_trace( FILE *f )
   239 {
   240     int i = call_stack_depth -1;
   241     if( i >= MAX_CALLSTACK )
   242 	i = MAX_CALLSTACK - 1;
   243     for( ; i >= 0; i-- ) {
   244 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   245 		 (call_stack_depth - i), call_stack[i].call_addr,
   246 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   247     }
   248 }
   250 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   251 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   252 #else
   253 #define TRACE_CALL( dest, rts ) 
   254 #define TRACE_RETURN( source, dest )
   255 #endif
   257 #define RAISE( x, v ) do{ \
   258     if( sh4r.vbr == 0 ) { \
   259         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   260         dreamcast_stop(); return FALSE;	\
   261     } else { \
   262         sh4r.spc = sh4r.pc + 2; \
   263         sh4r.ssr = sh4_read_sr(); \
   264         sh4r.sgr = sh4r.r[15]; \
   265         MMIO_WRITE(MMU,EXPEVT,x); \
   266         sh4r.pc = sh4r.vbr + v; \
   267         sh4r.new_pc = sh4r.pc + 2; \
   268         sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   269     } \
   270     return TRUE; } while(0)
   272 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
   273 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
   274 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
   275 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
   276 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
   277 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
   279 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   281 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
   283 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
   285 #define CHECK( x, c, v ) if( !x ) RAISE( c, v )
   286 #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
   287 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) RAISE( EXC_READ_ADDR_ERR, EXV_TRAP )
   288 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) RAISE( EXC_READ_ADDR_ERR, EXV_TRAP )
   289 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) RAISE( EXC_WRITE_ADDR_ERR, EXV_TRAP )
   290 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) RAISE( EXC_WRITE_ADDR_ERR, EXV_TRAP )
   292 #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
   293 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
   294 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }
   296 static void sh4_switch_banks( )
   297 {
   298     uint32_t tmp[8];
   300     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   301     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   302     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   303 }
   305 static void sh4_load_sr( uint32_t newval )
   306 {
   307     if( (newval ^ sh4r.sr) & SR_RB )
   308         sh4_switch_banks();
   309     sh4r.sr = newval;
   310     sh4r.t = (newval&SR_T) ? 1 : 0;
   311     sh4r.s = (newval&SR_S) ? 1 : 0;
   312     sh4r.m = (newval&SR_M) ? 1 : 0;
   313     sh4r.q = (newval&SR_Q) ? 1 : 0;
   314     intc_mask_changed();
   315 }
   317 static void sh4_write_float( uint32_t addr, int reg )
   318 {
   319     if( IS_FPU_DOUBLESIZE() ) {
   320 	if( reg & 1 ) {
   321 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
   322 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
   323 	} else {
   324 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 
   325 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
   326 	}
   327     } else {
   328 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
   329     }
   330 }
   332 static void sh4_read_float( uint32_t addr, int reg )
   333 {
   334     if( IS_FPU_DOUBLESIZE() ) {
   335 	if( reg & 1 ) {
   336 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
   337 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
   338 	} else {
   339 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   340 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
   341 	}
   342     } else {
   343 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   344     }
   345 }
   347 static uint32_t sh4_read_sr( void )
   348 {
   349     /* synchronize sh4r.sr with the various bitflags */
   350     sh4r.sr &= SR_MQSTMASK;
   351     if( sh4r.t ) sh4r.sr |= SR_T;
   352     if( sh4r.s ) sh4r.sr |= SR_S;
   353     if( sh4r.m ) sh4r.sr |= SR_M;
   354     if( sh4r.q ) sh4r.sr |= SR_Q;
   355     return sh4r.sr;
   356 }
   357 /* function for external use */
   358 void sh4_raise_exception( int code, int vector )
   359 {
   360     RAISE(code, vector);
   361 }
   363 static void sh4_accept_interrupt( void )
   364 {
   365     uint32_t code = intc_accept_interrupt();
   366     sh4r.ssr = sh4_read_sr();
   367     sh4r.spc = sh4r.pc;
   368     sh4r.sgr = sh4r.r[15];
   369     sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   370     MMIO_WRITE( MMU, INTEVT, code );
   371     sh4r.pc = sh4r.vbr + 0x600;
   372     sh4r.new_pc = sh4r.pc + 2;
   373     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   374 }
   376 gboolean sh4_execute_instruction( void )
   377 {
   378     uint32_t pc;
   379     unsigned short ir;
   380     uint32_t tmp;
   381     uint64_t tmpl;
   382     float ftmp;
   383     double dtmp;
   385 #define R0 sh4r.r[0]
   386 #define FR0 FR(0)
   387 #define DR0 DR(0)
   388 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
   389 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
   390 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
   391 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
   392 #define DISP8(ir) (ir&0x00FF)
   393 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
   394 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
   395 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
   396 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
   397 #define FRNn(ir) ((ir&0x0F00)>>8)
   398 #define FRMn(ir) ((ir&0x00F0)>>4)
   399 #define DRNn(ir) ((ir&0x0E00)>>9)
   400 #define DRMn(ir) ((ir&0x00E0)>>5)
   401 #define FVN(ir) ((ir&0x0C00)>>8)
   402 #define FVM(ir) ((ir&0x0300)>>6)
   403 #define FRN(ir) FR(FRNn(ir))
   404 #define FRM(ir) FR(FRMn(ir))
   405 #define FRNi(ir) (*((uint32_t *)&FR(FRNn(ir))))
   406 #define FRMi(ir) (*((uint32_t *)&FR(FRMn(ir))))
   407 #define DRN(ir) DRb(DRNn(ir), ir&0x0100)
   408 #define DRM(ir) DRb(DRMn(ir),ir&0x0010)
   409 #define DRNi(ir) (*((uint64_t *)&DR(FRNn(ir))))
   410 #define DRMi(ir) (*((uint64_t *)&DR(FRMn(ir))))
   411 #define FPULf   *((float *)&sh4r.fpul)
   412 #define FPULi    (sh4r.fpul)
   414     if( SH4_INT_PENDING() ) 
   415         sh4_accept_interrupt();
   417     pc = sh4r.pc;
   418     if( pc > 0xFFFFFF00 ) {
   419 	/* SYSCALL Magic */
   420 	syscall_invoke( pc );
   421 	sh4r.in_delay_slot = 0;
   422 	pc = sh4r.pc = sh4r.pr;
   423 	sh4r.new_pc = sh4r.pc + 2;
   424     }
   425     CHECKRALIGN16(pc);
   426     ir = MEM_READ_WORD(pc);
   427     sh4r.icount++;
   429     switch( (ir&0xF000)>>12 ) {
   430         case 0: /* 0000nnnnmmmmxxxx */
   431             switch( ir&0x000F ) {
   432                 case 2:
   433                     switch( (ir&0x00F0)>>4 ) {
   434                         case 0: /* STC     SR, Rn */
   435                             CHECKPRIV();
   436                             RN(ir) = sh4_read_sr();
   437                             break;
   438                         case 1: /* STC     GBR, Rn */
   439                             RN(ir) = sh4r.gbr;
   440                             break;
   441                         case 2: /* STC     VBR, Rn */
   442                             CHECKPRIV();
   443                             RN(ir) = sh4r.vbr;
   444                             break;
   445                         case 3: /* STC     SSR, Rn */
   446                             CHECKPRIV();
   447                             RN(ir) = sh4r.ssr;
   448                             break;
   449                         case 4: /* STC     SPC, Rn */
   450                             CHECKPRIV();
   451                             RN(ir) = sh4r.spc;
   452                             break;
   453                         case 8: case 9: case 10: case 11: case 12: case 13:
   454                         case 14: case 15:/* STC     Rm_bank, Rn */
   455                             CHECKPRIV();
   456                             RN(ir) = RN_BANK(ir);
   457                             break;
   458                         default: UNDEF(ir);
   459                     }
   460                     break;
   461                 case 3:
   462                     switch( (ir&0x00F0)>>4 ) {
   463                         case 0: /* BSRF    Rn */
   464                             CHECKDEST( pc + 4 + RN(ir) );
   465                             CHECKSLOTILLEGAL();
   466                             sh4r.in_delay_slot = 1;
   467                             sh4r.pr = sh4r.pc + 4;
   468                             sh4r.pc = sh4r.new_pc;
   469                             sh4r.new_pc = pc + 4 + RN(ir);
   470 			    TRACE_CALL( pc, sh4r.new_pc );
   471                             return TRUE;
   472                         case 2: /* BRAF    Rn */
   473                             CHECKDEST( pc + 4 + RN(ir) );
   474                             CHECKSLOTILLEGAL();
   475                             sh4r.in_delay_slot = 1;
   476                             sh4r.pc = sh4r.new_pc;
   477                             sh4r.new_pc = pc + 4 + RN(ir);
   478                             return TRUE;
   479                         case 8: /* PREF    [Rn] */
   480                             tmp = RN(ir);
   481                             if( (tmp & 0xFC000000) == 0xE0000000 ) {
   482                                 /* Store queue operation */
   483                                 int queue = (tmp&0x20)>>2;
   484                                 int32_t *src = &sh4r.store_queue[queue];
   485                                 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
   486                                 uint32_t target = tmp&0x03FFFFE0 | hi;
   487                                 mem_copy_to_sh4( target, src, 32 );
   488                             }
   489                             break;
   490                         case 9: /* OCBI    [Rn] */
   491                         case 10:/* OCBP    [Rn] */
   492                         case 11:/* OCBWB   [Rn] */
   493                             /* anything? */
   494                             break;
   495                         case 12:/* MOVCA.L R0, [Rn] */
   496 			    tmp = RN(ir);
   497 			    CHECKWALIGN32(tmp);
   498 			    MEM_WRITE_LONG( tmp, R0 );
   499 			    break;
   500                         default: UNDEF(ir);
   501                     }
   502                     break;
   503                 case 4: /* MOV.B   Rm, [R0 + Rn] */
   504                     MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
   505                     break;
   506                 case 5: /* MOV.W   Rm, [R0 + Rn] */
   507 		    CHECKWALIGN16( R0 + RN(ir) );
   508                     MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
   509                     break;
   510                 case 6: /* MOV.L   Rm, [R0 + Rn] */
   511 		    CHECKWALIGN32( R0 + RN(ir) );
   512                     MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
   513                     break;
   514                 case 7: /* MUL.L   Rm, Rn */
   515                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   516                         (RM(ir) * RN(ir));
   517                     break;
   518                 case 8: 
   519                     switch( (ir&0x0FF0)>>4 ) {
   520                         case 0: /* CLRT    */
   521                             sh4r.t = 0;
   522                             break;
   523                         case 1: /* SETT    */
   524                             sh4r.t = 1;
   525                             break;
   526                         case 2: /* CLRMAC  */
   527                             sh4r.mac = 0;
   528                             break;
   529                         case 3: /* LDTLB   */
   530                             break;
   531                         case 4: /* CLRS    */
   532                             sh4r.s = 0;
   533                             break;
   534                         case 5: /* SETS    */
   535                             sh4r.s = 1;
   536                             break;
   537                         default: UNDEF(ir);
   538                     }
   539                     break;
   540                 case 9: 
   541                     if( (ir&0x00F0) == 0x20 ) /* MOVT    Rn */
   542                         RN(ir) = sh4r.t;
   543                     else if( ir == 0x0019 ) /* DIV0U   */
   544                         sh4r.m = sh4r.q = sh4r.t = 0;
   545                     else if( ir == 0x0009 )
   546                         /* NOP     */;
   547                     else UNDEF(ir);
   548                     break;
   549                 case 10:
   550                     switch( (ir&0x00F0) >> 4 ) {
   551                         case 0: /* STS     MACH, Rn */
   552                             RN(ir) = sh4r.mac >> 32;
   553                             break;
   554                         case 1: /* STS     MACL, Rn */
   555                             RN(ir) = (uint32_t)sh4r.mac;
   556                             break;
   557                         case 2: /* STS     PR, Rn */
   558                             RN(ir) = sh4r.pr;
   559                             break;
   560                         case 3: /* STC     SGR, Rn */
   561                             CHECKPRIV();
   562                             RN(ir) = sh4r.sgr;
   563                             break;
   564                         case 5:/* STS      FPUL, Rn */
   565                             RN(ir) = sh4r.fpul;
   566                             break;
   567                         case 6: /* STS     FPSCR, Rn */
   568                             RN(ir) = sh4r.fpscr;
   569                             break;
   570                         case 15:/* STC     DBR, Rn */
   571                             CHECKPRIV();
   572                             RN(ir) = sh4r.dbr;
   573                             break;
   574                         default: UNDEF(ir);
   575                     }
   576                     break;
   577                 case 11:
   578                     switch( (ir&0x0FF0)>>4 ) {
   579                         case 0: /* RTS     */
   580                             CHECKDEST( sh4r.pr );
   581                             CHECKSLOTILLEGAL();
   582                             sh4r.in_delay_slot = 1;
   583                             sh4r.pc = sh4r.new_pc;
   584                             sh4r.new_pc = sh4r.pr;
   585                             TRACE_RETURN( pc, sh4r.new_pc );
   586                             return TRUE;
   587                         case 1: /* SLEEP   */
   588 			    if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   589 				sh4r.sh4_state = SH4_STATE_STANDBY;
   590 			    } else {
   591 				sh4r.sh4_state = SH4_STATE_SLEEP;
   592 			    }
   593 			    return FALSE; /* Halt CPU */
   594                         case 2: /* RTE     */
   595                             CHECKPRIV();
   596                             CHECKDEST( sh4r.spc );
   597                             CHECKSLOTILLEGAL();
   598                             sh4r.in_delay_slot = 1;
   599                             sh4r.pc = sh4r.new_pc;
   600                             sh4r.new_pc = sh4r.spc;
   601                             sh4_load_sr( sh4r.ssr );
   602                             return TRUE;
   603                         default:UNDEF(ir);
   604                     }
   605                     break;
   606                 case 12:/* MOV.B   [R0+R%d], R%d */
   607                     RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
   608                     break;
   609                 case 13:/* MOV.W   [R0+R%d], R%d */
   610 		    CHECKRALIGN16( R0 + RM(ir) );
   611                     RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
   612                     break;
   613                 case 14:/* MOV.L   [R0+R%d], R%d */
   614 		    CHECKRALIGN32( R0 + RM(ir) );
   615                     RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
   616                     break;
   617                 case 15:/* MAC.L   [Rm++], [Rn++] */
   618 		    CHECKRALIGN32( RM(ir) );
   619 		    CHECKRALIGN32( RN(ir) );
   620                     tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
   621                                   SIGNEXT32(MEM_READ_LONG(RN(ir))) );
   622                     if( sh4r.s ) {
   623                         /* 48-bit Saturation. Yuch */
   624                         tmpl += SIGNEXT48(sh4r.mac);
   625                         if( tmpl < 0xFFFF800000000000LL )
   626                             tmpl = 0xFFFF800000000000LL;
   627                         else if( tmpl > 0x00007FFFFFFFFFFFLL )
   628                             tmpl = 0x00007FFFFFFFFFFFLL;
   629                         sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
   630                             (tmpl&0x0000FFFFFFFFFFFFLL);
   631                     } else sh4r.mac = tmpl;
   633                     RM(ir) += 4;
   634                     RN(ir) += 4;
   636                     break;
   637                 default: UNDEF(ir);
   638             }
   639             break;
   640         case 1: /* 0001nnnnmmmmdddd */
   641             /* MOV.L   Rm, [Rn + disp4*4] */
   642 	    tmp = RN(ir) + (DISP4(ir)<<2);
   643 	    CHECKWALIGN32( tmp );
   644             MEM_WRITE_LONG( tmp, RM(ir) );
   645             break;
   646         case 2: /* 0010nnnnmmmmxxxx */
   647             switch( ir&0x000F ) {
   648                 case 0: /* MOV.B   Rm, [Rn] */
   649                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   650                     break;
   651                 case 1: /* MOV.W   Rm, [Rn] */
   652                	    CHECKWALIGN16( RN(ir) );
   653 		    MEM_WRITE_WORD( RN(ir), RM(ir) );
   654                     break;
   655                 case 2: /* MOV.L   Rm, [Rn] */
   656 		    CHECKWALIGN32( RN(ir) );
   657                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   658                     break;
   659                 case 3: UNDEF(ir);
   660                     break;
   661                 case 4: /* MOV.B   Rm, [--Rn] */
   662                     RN(ir) --;
   663                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   664                     break;
   665                 case 5: /* MOV.W   Rm, [--Rn] */
   666                     RN(ir) -= 2;
   667 		    CHECKWALIGN16( RN(ir) );
   668                     MEM_WRITE_WORD( RN(ir), RM(ir) );
   669                     break;
   670                 case 6: /* MOV.L   Rm, [--Rn] */
   671                     RN(ir) -= 4;
   672 		    CHECKWALIGN32( RN(ir) );
   673                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   674                     break;
   675                 case 7: /* DIV0S   Rm, Rn */
   676                     sh4r.q = RN(ir)>>31;
   677                     sh4r.m = RM(ir)>>31;
   678                     sh4r.t = sh4r.q ^ sh4r.m;
   679                     break;
   680                 case 8: /* TST     Rm, Rn */
   681                     sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
   682                     break;
   683                 case 9: /* AND     Rm, Rn */
   684                     RN(ir) &= RM(ir);
   685                     break;
   686                 case 10:/* XOR     Rm, Rn */
   687                     RN(ir) ^= RM(ir);
   688                     break;
   689                 case 11:/* OR      Rm, Rn */
   690                     RN(ir) |= RM(ir);
   691                     break;
   692                 case 12:/* CMP/STR Rm, Rn */
   693                     /* set T = 1 if any byte in RM & RN is the same */
   694                     tmp = RM(ir) ^ RN(ir);
   695                     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   696                               (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   697                     break;
   698                 case 13:/* XTRCT   Rm, Rn */
   699                     RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
   700                     break;
   701                 case 14:/* MULU.W  Rm, Rn */
   702                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   703                         (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
   704                     break;
   705                 case 15:/* MULS.W  Rm, Rn */
   706                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   707                         (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
   708                     break;
   709             }
   710             break;
   711         case 3: /* 0011nnnnmmmmxxxx */
   712             switch( ir&0x000F ) {
   713                 case 0: /* CMP/EQ  Rm, Rn */
   714                     sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
   715                     break;
   716                 case 2: /* CMP/HS  Rm, Rn */
   717                     sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
   718                     break;
   719                 case 3: /* CMP/GE  Rm, Rn */
   720                     sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
   721                     break;
   722                 case 4: { /* DIV1    Rm, Rn */
   723                     /* This is just from the sh4p manual with some
   724                      * simplifications (someone want to check it's correct? :)
   725                      * Why they couldn't just provide a real DIV instruction...
   726                      * Please oh please let the translator batch these things
   727                      * up into a single DIV... */
   728                     uint32_t tmp0, tmp1, tmp2, dir;
   730                     dir = sh4r.q ^ sh4r.m;
   731                     sh4r.q = (RN(ir) >> 31);
   732                     tmp2 = RM(ir);
   733                     RN(ir) = (RN(ir) << 1) | sh4r.t;
   734                     tmp0 = RN(ir);
   735                     if( dir ) {
   736                         RN(ir) += tmp2;
   737                         tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
   738                     } else {
   739                         RN(ir) -= tmp2;
   740                         tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
   741                     }
   742                     sh4r.q ^= sh4r.m ^ tmp1;
   743                     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   744                     break; }
   745                 case 5: /* DMULU.L Rm, Rn */
   746                     sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
   747                     break;
   748                 case 6: /* CMP/HI  Rm, Rn */
   749                     sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
   750                     break;
   751                 case 7: /* CMP/GT  Rm, Rn */
   752                     sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
   753                     break;
   754                 case 8: /* SUB     Rm, Rn */
   755                     RN(ir) -= RM(ir);
   756                     break;
   757                 case 10:/* SUBC    Rm, Rn */
   758                     tmp = RN(ir);
   759                     RN(ir) = RN(ir) - RM(ir) - sh4r.t;
   760                     sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
   761                     break;
   762                 case 11:/* SUBV    Rm, Rn */
   763                     UNIMP(ir);
   764                     break;
   765                 case 12:/* ADD     Rm, Rn */
   766                     RN(ir) += RM(ir);
   767                     break;
   768                 case 13:/* DMULS.L Rm, Rn */
   769                     sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
   770                     break;
   771                 case 14:/* ADDC    Rm, Rn */
   772                     tmp = RN(ir);
   773                     RN(ir) += RM(ir) + sh4r.t;
   774                     sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
   775                     break;
   776                 case 15:/* ADDV    Rm, Rn */
   777 		    tmp = RN(ir) + RM(ir);
   778 		    sh4r.t = ( (RN(ir)>>31) == (RM(ir)>>31) && ((RN(ir)>>31) != (tmp>>31)) );
   779 		    RN(ir) = tmp;
   780                     break;
   781                 default: UNDEF(ir);
   782             }
   783             break;
   784         case 4: /* 0100nnnnxxxxxxxx */
   785             switch( ir&0x00FF ) {
   786                 case 0x00: /* SHLL    Rn */
   787                     sh4r.t = RN(ir) >> 31;
   788                     RN(ir) <<= 1;
   789                     break;
   790                 case 0x01: /* SHLR    Rn */
   791                     sh4r.t = RN(ir) & 0x00000001;
   792                     RN(ir) >>= 1;
   793                     break;
   794                 case 0x02: /* STS.L   MACH, [--Rn] */
   795                     RN(ir) -= 4;
   796 		    CHECKWALIGN32( RN(ir) );
   797                     MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
   798                     break;
   799                 case 0x03: /* STC.L   SR, [--Rn] */
   800                     CHECKPRIV();
   801                     RN(ir) -= 4;
   802 		    CHECKWALIGN32( RN(ir) );
   803                     MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
   804                     break;
   805                 case 0x04: /* ROTL    Rn */
   806                     sh4r.t = RN(ir) >> 31;
   807                     RN(ir) <<= 1;
   808                     RN(ir) |= sh4r.t;
   809                     break;
   810                 case 0x05: /* ROTR    Rn */
   811                     sh4r.t = RN(ir) & 0x00000001;
   812                     RN(ir) >>= 1;
   813                     RN(ir) |= (sh4r.t << 31);
   814                     break;
   815                 case 0x06: /* LDS.L   [Rn++], MACH */
   816 		    CHECKRALIGN32( RN(ir) );
   817                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   818                         (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
   819                     RN(ir) += 4;
   820                     break;
   821                 case 0x07: /* LDC.L   [Rn++], SR */
   822                     CHECKPRIV();
   823 		    CHECKWALIGN32( RN(ir) );
   824                     sh4_load_sr( MEM_READ_LONG(RN(ir)) );
   825                     RN(ir) +=4;
   826                     break;
   827                 case 0x08: /* SHLL2   Rn */
   828                     RN(ir) <<= 2;
   829                     break;
   830                 case 0x09: /* SHLR2   Rn */
   831                     RN(ir) >>= 2;
   832                     break;
   833                 case 0x0A: /* LDS     Rn, MACH */
   834                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   835                         (((uint64_t)RN(ir))<<32);
   836                     break;
   837                 case 0x0B: /* JSR     [Rn] */
   838                     CHECKDEST( RN(ir) );
   839                     CHECKSLOTILLEGAL();
   840                     sh4r.in_delay_slot = 1;
   841                     sh4r.pc = sh4r.new_pc;
   842                     sh4r.new_pc = RN(ir);
   843                     sh4r.pr = pc + 4;
   844 		    TRACE_CALL( pc, sh4r.new_pc );
   845                     return TRUE;
   846                 case 0x0E: /* LDC     Rn, SR */
   847                     CHECKPRIV();
   848                     sh4_load_sr( RN(ir) );
   849                     break;
   850                 case 0x10: /* DT      Rn */
   851                     RN(ir) --;
   852                     sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
   853                     break;
   854                 case 0x11: /* CMP/PZ  Rn */
   855                     sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
   856                     break;
   857                 case 0x12: /* STS.L   MACL, [--Rn] */
   858                     RN(ir) -= 4;
   859 		    CHECKWALIGN32( RN(ir) );
   860                     MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
   861                     break;
   862                 case 0x13: /* STC.L   GBR, [--Rn] */
   863                     RN(ir) -= 4;
   864 		    CHECKWALIGN32( RN(ir) );
   865                     MEM_WRITE_LONG( RN(ir), sh4r.gbr );
   866                     break;
   867                 case 0x15: /* CMP/PL  Rn */
   868                     sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
   869                     break;
   870                 case 0x16: /* LDS.L   [Rn++], MACL */
   871 		    CHECKRALIGN32( RN(ir) );
   872                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   873                         (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
   874                     RN(ir) += 4;
   875                     break;
   876                 case 0x17: /* LDC.L   [Rn++], GBR */
   877 		    CHECKRALIGN32( RN(ir) );
   878                     sh4r.gbr = MEM_READ_LONG(RN(ir));
   879                     RN(ir) +=4;
   880                     break;
   881                 case 0x18: /* SHLL8   Rn */
   882                     RN(ir) <<= 8;
   883                     break;
   884                 case 0x19: /* SHLR8   Rn */
   885                     RN(ir) >>= 8;
   886                     break;
   887                 case 0x1A: /* LDS     Rn, MACL */
   888                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   889                         (uint64_t)((uint32_t)(RN(ir)));
   890                     break;
   891                 case 0x1B: /* TAS.B   [Rn] */
   892                     tmp = MEM_READ_BYTE( RN(ir) );
   893                     sh4r.t = ( tmp == 0 ? 1 : 0 );
   894                     MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
   895                     break;
   896                 case 0x1E: /* LDC     Rn, GBR */
   897                     sh4r.gbr = RN(ir);
   898                     break;
   899                 case 0x20: /* SHAL    Rn */
   900                     sh4r.t = RN(ir) >> 31;
   901                     RN(ir) <<= 1;
   902                     break;
   903                 case 0x21: /* SHAR    Rn */
   904                     sh4r.t = RN(ir) & 0x00000001;
   905                     RN(ir) = ((int32_t)RN(ir)) >> 1;
   906                     break;
   907                 case 0x22: /* STS.L   PR, [--Rn] */
   908                     RN(ir) -= 4;
   909 		    CHECKWALIGN32( RN(ir) );
   910                     MEM_WRITE_LONG( RN(ir), sh4r.pr );
   911                     break;
   912                 case 0x23: /* STC.L   VBR, [--Rn] */
   913                     CHECKPRIV();
   914                     RN(ir) -= 4;
   915 		    CHECKWALIGN32( RN(ir) );
   916                     MEM_WRITE_LONG( RN(ir), sh4r.vbr );
   917                     break;
   918                 case 0x24: /* ROTCL   Rn */
   919                     tmp = RN(ir) >> 31;
   920                     RN(ir) <<= 1;
   921                     RN(ir) |= sh4r.t;
   922                     sh4r.t = tmp;
   923                     break;
   924                 case 0x25: /* ROTCR   Rn */
   925                     tmp = RN(ir) & 0x00000001;
   926                     RN(ir) >>= 1;
   927                     RN(ir) |= (sh4r.t << 31 );
   928                     sh4r.t = tmp;
   929                     break;
   930                 case 0x26: /* LDS.L   [Rn++], PR */
   931 		    CHECKRALIGN32( RN(ir) );
   932                     sh4r.pr = MEM_READ_LONG( RN(ir) );
   933                     RN(ir) += 4;
   934                     break;
   935                 case 0x27: /* LDC.L   [Rn++], VBR */
   936                     CHECKPRIV();
   937 		    CHECKRALIGN32( RN(ir) );
   938                     sh4r.vbr = MEM_READ_LONG(RN(ir));
   939                     RN(ir) +=4;
   940                     break;
   941                 case 0x28: /* SHLL16  Rn */
   942                     RN(ir) <<= 16;
   943                     break;
   944                 case 0x29: /* SHLR16  Rn */
   945                     RN(ir) >>= 16;
   946                     break;
   947                 case 0x2A: /* LDS     Rn, PR */
   948                     sh4r.pr = RN(ir);
   949                     break;
   950                 case 0x2B: /* JMP     [Rn] */
   951                     CHECKDEST( RN(ir) );
   952                     CHECKSLOTILLEGAL();
   953                     sh4r.in_delay_slot = 1;
   954                     sh4r.pc = sh4r.new_pc;
   955                     sh4r.new_pc = RN(ir);
   956                     return TRUE;
   957                 case 0x2E: /* LDC     Rn, VBR */
   958                     CHECKPRIV();
   959                     sh4r.vbr = RN(ir);
   960                     break;
   961                 case 0x32: /* STC.L   SGR, [--Rn] */
   962                     CHECKPRIV();
   963                     RN(ir) -= 4;
   964 		    CHECKWALIGN32( RN(ir) );
   965                     MEM_WRITE_LONG( RN(ir), sh4r.sgr );
   966                     break;
   967                 case 0x33: /* STC.L   SSR, [--Rn] */
   968                     CHECKPRIV();
   969                     RN(ir) -= 4;
   970 		    CHECKWALIGN32( RN(ir) );
   971                     MEM_WRITE_LONG( RN(ir), sh4r.ssr );
   972                     break;
   973                 case 0x37: /* LDC.L   [Rn++], SSR */
   974                     CHECKPRIV();
   975 		    CHECKRALIGN32( RN(ir) );
   976                     sh4r.ssr = MEM_READ_LONG(RN(ir));
   977                     RN(ir) +=4;
   978                     break;
   979                 case 0x3E: /* LDC     Rn, SSR */
   980                     CHECKPRIV();
   981                     sh4r.ssr = RN(ir);
   982                     break;
   983                 case 0x43: /* STC.L   SPC, [--Rn] */
   984                     CHECKPRIV();
   985                     RN(ir) -= 4;
   986 		    CHECKWALIGN32( RN(ir) );
   987                     MEM_WRITE_LONG( RN(ir), sh4r.spc );
   988                     break;
   989                 case 0x47: /* LDC.L   [Rn++], SPC */
   990                     CHECKPRIV();
   991 		    CHECKRALIGN32( RN(ir) );
   992                     sh4r.spc = MEM_READ_LONG(RN(ir));
   993                     RN(ir) +=4;
   994                     break;
   995                 case 0x4E: /* LDC     Rn, SPC */
   996                     CHECKPRIV();
   997                     sh4r.spc = RN(ir);
   998                     break;
   999                 case 0x52: /* STS.L   FPUL, [--Rn] */
  1000                     RN(ir) -= 4;
  1001 		    CHECKWALIGN32( RN(ir) );
  1002                     MEM_WRITE_LONG( RN(ir), sh4r.fpul );
  1003                     break;
  1004                 case 0x56: /* LDS.L   [Rn++], FPUL */
  1005 		    CHECKRALIGN32( RN(ir) );
  1006                     sh4r.fpul = MEM_READ_LONG(RN(ir));
  1007                     RN(ir) +=4;
  1008                     break;
  1009                 case 0x5A: /* LDS     Rn, FPUL */
  1010                     sh4r.fpul = RN(ir);
  1011                     break;
  1012                 case 0x62: /* STS.L   FPSCR, [--Rn] */
  1013                     RN(ir) -= 4;
  1014 		    CHECKWALIGN32( RN(ir) );
  1015                     MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
  1016                     break;
  1017                 case 0x66: /* LDS.L   [Rn++], FPSCR */
  1018 		    CHECKRALIGN32( RN(ir) );
  1019                     sh4r.fpscr = MEM_READ_LONG(RN(ir));
  1020                     RN(ir) +=4;
  1021                     break;
  1022                 case 0x6A: /* LDS     Rn, FPSCR */
  1023                     sh4r.fpscr = RN(ir);
  1024                     break;
  1025                 case 0xF2: /* STC.L   DBR, [--Rn] */
  1026                     CHECKPRIV();
  1027                     RN(ir) -= 4;
  1028 		    CHECKWALIGN32( RN(ir) );
  1029                     MEM_WRITE_LONG( RN(ir), sh4r.dbr );
  1030                     break;
  1031                 case 0xF6: /* LDC.L   [Rn++], DBR */
  1032                     CHECKPRIV();
  1033 		    CHECKRALIGN32( RN(ir) );
  1034                     sh4r.dbr = MEM_READ_LONG(RN(ir));
  1035                     RN(ir) +=4;
  1036                     break;
  1037                 case 0xFA: /* LDC     Rn, DBR */
  1038                     CHECKPRIV();
  1039                     sh4r.dbr = RN(ir);
  1040                     break;
  1041                 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
  1042                 case 0xD3: case 0xE3: case 0xF3: /* STC.L   Rn_BANK, [--Rn] */
  1043                     CHECKPRIV();
  1044                     RN(ir) -= 4;
  1045 		    CHECKWALIGN32( RN(ir) );
  1046                     MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
  1047                     break;
  1048                 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
  1049                 case 0xD7: case 0xE7: case 0xF7: /* LDC.L   [Rn++], Rn_BANK */
  1050                     CHECKPRIV();
  1051 		    CHECKRALIGN32( RN(ir) );
  1052                     RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
  1053                     RN(ir) += 4;
  1054                     break;
  1055                 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
  1056                 case 0xDE: case 0xEE: case 0xFE: /* LDC     Rm, Rn_BANK */
  1057                     CHECKPRIV();
  1058                     RN_BANK(ir) = RM(ir);
  1059                     break;
  1060                 default:
  1061                     if( (ir&0x000F) == 0x0F ) {
  1062                         /* MAC.W   [Rm++], [Rn++] */
  1063 			CHECKRALIGN16( RN(ir) );
  1064 			CHECKRALIGN16( RM(ir) );
  1065                         tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
  1066                             SIGNEXT16(MEM_READ_WORD(RN(ir)));
  1067                         if( sh4r.s ) {
  1068                             /* FIXME */
  1069                             UNIMP(ir);
  1070                         } else sh4r.mac += SIGNEXT32(tmp);
  1071                         RM(ir) += 2;
  1072                         RN(ir) += 2;
  1073                     } else if( (ir&0x000F) == 0x0C ) {
  1074                         /* SHAD    Rm, Rn */
  1075                         tmp = RM(ir);
  1076                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
  1077                         else if( (tmp & 0x1F) == 0 )  
  1078 			  RN(ir) = ((int32_t)RN(ir)) >> 31;
  1079                         else 
  1080 			  RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
  1081                     } else if( (ir&0x000F) == 0x0D ) {
  1082                         /* SHLD    Rm, Rn */
  1083                         tmp = RM(ir);
  1084                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
  1085                         else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
  1086                         else RN(ir) >>= (((~tmp) & 0x1F)+1);
  1087                     } else UNDEF(ir);
  1089             break;
  1090         case 5: /* 0101nnnnmmmmdddd */
  1091             /* MOV.L   [Rm + disp4*4], Rn */
  1092 	    tmp = RM(ir) + (DISP4(ir)<<2);
  1093 	    CHECKRALIGN32( tmp );
  1094             RN(ir) = MEM_READ_LONG( tmp );
  1095             break;
  1096         case 6: /* 0110xxxxxxxxxxxx */
  1097             switch( ir&0x000f ) {
  1098                 case 0: /* MOV.B   [Rm], Rn */
  1099                     RN(ir) = MEM_READ_BYTE( RM(ir) );
  1100                     break;
  1101                 case 1: /* MOV.W   [Rm], Rn */
  1102 		    CHECKRALIGN16( RM(ir) );
  1103                     RN(ir) = MEM_READ_WORD( RM(ir) );
  1104                     break;
  1105                 case 2: /* MOV.L   [Rm], Rn */
  1106 		    CHECKRALIGN32( RM(ir) );
  1107                     RN(ir) = MEM_READ_LONG( RM(ir) );
  1108                     break;
  1109                 case 3: /* MOV     Rm, Rn */
  1110                     RN(ir) = RM(ir);
  1111                     break;
  1112                 case 4: /* MOV.B   [Rm++], Rn */
  1113                     RN(ir) = MEM_READ_BYTE( RM(ir) );
  1114                     RM(ir) ++;
  1115                     break;
  1116                 case 5: /* MOV.W   [Rm++], Rn */
  1117 		    CHECKRALIGN16( RM(ir) );
  1118                     RN(ir) = MEM_READ_WORD( RM(ir) );
  1119                     RM(ir) += 2;
  1120                     break;
  1121                 case 6: /* MOV.L   [Rm++], Rn */
  1122 		    CHECKRALIGN32( RM(ir) );
  1123                     RN(ir) = MEM_READ_LONG( RM(ir) );
  1124                     RM(ir) += 4;
  1125                     break;
  1126                 case 7: /* NOT     Rm, Rn */
  1127                     RN(ir) = ~RM(ir);
  1128                     break;
  1129                 case 8: /* SWAP.B  Rm, Rn */
  1130                     RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
  1131                         ((RM(ir)&0x000000FF)<<8);
  1132                     break;
  1133                 case 9: /* SWAP.W  Rm, Rn */
  1134                     RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
  1135                     break;
  1136                 case 10:/* NEGC    Rm, Rn */
  1137                     tmp = 0 - RM(ir);
  1138                     RN(ir) = tmp - sh4r.t;
  1139                     sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
  1140                     break;
  1141                 case 11:/* NEG     Rm, Rn */
  1142                     RN(ir) = 0 - RM(ir);
  1143                     break;
  1144                 case 12:/* EXTU.B  Rm, Rn */
  1145                     RN(ir) = RM(ir)&0x000000FF;
  1146                     break;
  1147                 case 13:/* EXTU.W  Rm, Rn */
  1148                     RN(ir) = RM(ir)&0x0000FFFF;
  1149                     break;
  1150                 case 14:/* EXTS.B  Rm, Rn */
  1151                     RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
  1152                     break;
  1153                 case 15:/* EXTS.W  Rm, Rn */
  1154                     RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
  1155                     break;
  1157             break;
  1158         case 7: /* 0111nnnniiiiiiii */
  1159             /* ADD    imm8, Rn */
  1160             RN(ir) += IMM8(ir);
  1161             break;
  1162         case 8: /* 1000xxxxxxxxxxxx */
  1163             switch( (ir&0x0F00) >> 8 ) {
  1164                 case 0: /* MOV.B   R0, [Rm + disp4] */
  1165                     MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
  1166                     break;
  1167                 case 1: /* MOV.W   R0, [Rm + disp4*2] */
  1168 		    tmp = RM(ir) + (DISP4(ir)<<1);
  1169 		    CHECKWALIGN16( tmp );
  1170                     MEM_WRITE_WORD( tmp, R0 );
  1171                     break;
  1172                 case 4: /* MOV.B   [Rm + disp4], R0 */
  1173                     R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
  1174                     break;
  1175                 case 5: /* MOV.W   [Rm + disp4*2], R0 */
  1176 		    tmp = RM(ir) + (DISP4(ir)<<1);
  1177 		    CHECKRALIGN16( tmp );
  1178                     R0 = MEM_READ_WORD( tmp );
  1179                     break;
  1180                 case 8: /* CMP/EQ  imm, R0 */
  1181                     sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
  1182                     break;
  1183                 case 9: /* BT      disp8 */
  1184                     CHECKSLOTILLEGAL()
  1185                     if( sh4r.t ) {
  1186                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1187                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
  1188                         sh4r.new_pc = sh4r.pc + 2;
  1189                         return TRUE;
  1191                     break;
  1192                 case 11:/* BF      disp8 */
  1193                     CHECKSLOTILLEGAL()
  1194                     if( !sh4r.t ) {
  1195                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1196                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
  1197                         sh4r.new_pc = sh4r.pc + 2;
  1198                         return TRUE;
  1200                     break;
  1201                 case 13:/* BT/S    disp8 */
  1202                     CHECKSLOTILLEGAL()
  1203                     if( sh4r.t ) {
  1204                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1205                         sh4r.in_delay_slot = 1;
  1206                         sh4r.pc = sh4r.new_pc;
  1207                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
  1208                         sh4r.in_delay_slot = 1;
  1209                         return TRUE;
  1211                     break;
  1212                 case 15:/* BF/S    disp8 */
  1213                     CHECKSLOTILLEGAL()
  1214                     if( !sh4r.t ) {
  1215                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1216                         sh4r.in_delay_slot = 1;
  1217                         sh4r.pc = sh4r.new_pc;
  1218                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
  1219                         return TRUE;
  1221                     break;
  1222                 default: UNDEF(ir);
  1224             break;
  1225         case 9: /* 1001xxxxxxxxxxxx */
  1226             /* MOV.W   [disp8*2 + pc + 4], Rn */
  1227 	    tmp = pc + 4 + (DISP8(ir)<<1);
  1228 	    CHECKRALIGN16( tmp );
  1229             RN(ir) = MEM_READ_WORD( tmp );
  1230             break;
  1231         case 10:/* 1010dddddddddddd */
  1232             /* BRA     disp12 */
  1233             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
  1234             CHECKSLOTILLEGAL()
  1235             sh4r.in_delay_slot = 1;
  1236             sh4r.pc = sh4r.new_pc;
  1237             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
  1238             return TRUE;
  1239         case 11:/* 1011dddddddddddd */
  1240             /* BSR     disp12 */
  1241             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
  1242             CHECKSLOTILLEGAL()
  1243             sh4r.in_delay_slot = 1;
  1244             sh4r.pr = pc + 4;
  1245             sh4r.pc = sh4r.new_pc;
  1246             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
  1247 	    TRACE_CALL( pc, sh4r.new_pc );
  1248             return TRUE;
  1249         case 12:/* 1100xxxxdddddddd */
  1250         switch( (ir&0x0F00)>>8 ) {
  1251                 case 0: /* MOV.B  R0, [GBR + disp8] */
  1252                     MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
  1253                     break;
  1254                 case 1: /* MOV.W  R0, [GBR + disp8*2] */
  1255 		    tmp = sh4r.gbr + (DISP8(ir)<<1);
  1256 		    CHECKWALIGN16( tmp );
  1257                     MEM_WRITE_WORD( tmp, R0 );
  1258                     break;
  1259                 case  2: /*MOV.L   R0, [GBR + disp8*4] */
  1260 		    tmp = sh4r.gbr + (DISP8(ir)<<2);
  1261 		    CHECKWALIGN32( tmp );
  1262                     MEM_WRITE_LONG( tmp, R0 );
  1263                     break;
  1264                 case 3: /* TRAPA   imm8 */
  1265                     CHECKSLOTILLEGAL()
  1266                     sh4r.in_delay_slot = 1;
  1267                     MMIO_WRITE( MMU, TRA, UIMM8(ir)<<2 );
  1268                     RAISE( EXC_TRAP, EXV_TRAP );
  1269                     break;
  1270                 case 4: /* MOV.B   [GBR + disp8], R0 */
  1271                     R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
  1272                     break;
  1273                 case 5: /* MOV.W   [GBR + disp8*2], R0 */
  1274 		    tmp = sh4r.gbr + (DISP8(ir)<<1);
  1275 		    CHECKRALIGN16( tmp );
  1276                     R0 = MEM_READ_WORD( tmp );
  1277                     break;
  1278                 case 6: /* MOV.L   [GBR + disp8*4], R0 */
  1279 		    tmp = sh4r.gbr + (DISP8(ir)<<2);
  1280 		    CHECKRALIGN32( tmp );
  1281                     R0 = MEM_READ_LONG( tmp );
  1282                     break;
  1283                 case 7: /* MOVA    disp8 + pc&~3 + 4, R0 */
  1284                     R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
  1285                     break;
  1286                 case 8: /* TST     imm8, R0 */
  1287                     sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
  1288                     break;
  1289                 case 9: /* AND     imm8, R0 */
  1290                     R0 &= UIMM8(ir);
  1291                     break;
  1292                 case 10:/* XOR     imm8, R0 */
  1293                     R0 ^= UIMM8(ir);
  1294                     break;
  1295                 case 11:/* OR      imm8, R0 */
  1296                     R0 |= UIMM8(ir);
  1297                     break;
  1298                 case 12:/* TST.B   imm8, [R0+GBR] */		    
  1299                     sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
  1300                     break;
  1301                 case 13:/* AND.B   imm8, [R0+GBR] */
  1302                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1303                                     UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
  1304                     break;
  1305                 case 14:/* XOR.B   imm8, [R0+GBR] */
  1306                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1307                                     UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
  1308                     break;
  1309                 case 15:/* OR.B    imm8, [R0+GBR] */
  1310                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1311                                     UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
  1312                     break;
  1314             break;
  1315         case 13:/* 1101nnnndddddddd */
  1316             /* MOV.L   [disp8*4 + pc&~3 + 4], Rn */
  1317 	    tmp = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
  1318 	    CHECKRALIGN32( tmp );
  1319             RN(ir) = MEM_READ_LONG( tmp );
  1320             break;
  1321         case 14:/* 1110nnnniiiiiiii */
  1322             /* MOV     imm8, Rn */
  1323             RN(ir) = IMM8(ir);
  1324             break;
  1325         case 15:/* 1111xxxxxxxxxxxx */
  1326             CHECKFPUEN();
  1327 	    if( IS_FPU_DOUBLEPREC() ) {
  1328 		switch( ir&0x000F ) {
  1329                 case 0: /* FADD    FRm, FRn */
  1330                     DRN(ir) += DRM(ir);
  1331                     break;
  1332                 case 1: /* FSUB    FRm, FRn */
  1333                     DRN(ir) -= DRM(ir);
  1334                     break;
  1335                 case 2: /* FMUL    FRm, FRn */
  1336                     DRN(ir) = DRN(ir) * DRM(ir);
  1337                     break;
  1338                 case 3: /* FDIV    FRm, FRn */
  1339                     DRN(ir) = DRN(ir) / DRM(ir);
  1340                     break;
  1341                 case 4: /* FCMP/EQ FRm, FRn */
  1342                     sh4r.t = ( DRN(ir) == DRM(ir) ? 1 : 0 );
  1343                     break;
  1344                 case 5: /* FCMP/GT FRm, FRn */
  1345                     sh4r.t = ( DRN(ir) > DRM(ir) ? 1 : 0 );
  1346                     break;
  1347                 case 6: /* FMOV.S  [Rm+R0], FRn */
  1348                     MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
  1349                     break;
  1350                 case 7: /* FMOV.S  FRm, [Rn+R0] */
  1351                     MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
  1352                     break;
  1353                 case 8: /* FMOV.S  [Rm], FRn */
  1354                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1355                     break;
  1356                 case 9: /* FMOV.S  [Rm++], FRn */
  1357                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1358                     RM(ir) += FP_WIDTH;
  1359                     break;
  1360                 case 10:/* FMOV.S  FRm, [Rn] */
  1361                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1362                     break;
  1363                 case 11:/* FMOV.S  FRm, [--Rn] */
  1364                     RN(ir) -= FP_WIDTH;
  1365                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1366                     break;
  1367                 case 12:/* FMOV    FRm, FRn */
  1368 		    if( IS_FPU_DOUBLESIZE() )
  1369 			DRN(ir) = DRM(ir);
  1370 		    else
  1371 			FRN(ir) = FRM(ir);
  1372                     break;
  1373                 case 13:
  1374                     switch( (ir&0x00F0) >> 4 ) {
  1375 		    case 0: /* FSTS    FPUL, FRn */
  1376 			FRN(ir) = FPULf;
  1377 			break;
  1378 		    case 1: /* FLDS    FRn,FPUL */
  1379 			FPULf = FRN(ir);
  1380 			break;
  1381 		    case 2: /* FLOAT   FPUL, FRn */
  1382 			DRN(ir) = (float)FPULi;
  1383 			break;
  1384 		    case 3: /* FTRC    FRn, FPUL */
  1385 			dtmp = DRN(ir);
  1386 			if( dtmp >= MAX_INTF )
  1387 			    FPULi = MAX_INT;
  1388 			else if( dtmp <= MIN_INTF )
  1389 			    FPULi = MIN_INT;
  1390 			else 
  1391 			    FPULi = (int32_t)dtmp;
  1392 			break;
  1393 		    case 4: /* FNEG    FRn */
  1394 			DRN(ir) = -DRN(ir);
  1395 			break;
  1396 		    case 5: /* FABS    FRn */
  1397 			DRN(ir) = fabs(DRN(ir));
  1398 			break;
  1399 		    case 6: /* FSQRT   FRn */
  1400 			DRN(ir) = sqrt(DRN(ir));
  1401 			break;
  1402 		    case 7: /* FSRRA FRn */
  1403 			/* NO-OP when PR=1 */
  1404 			break;
  1405 		    case 8: /* FLDI0   FRn */
  1406 			DRN(ir) = 0.0;
  1407 			break;
  1408 		    case 9: /* FLDI1   FRn */
  1409 			DRN(ir) = 1.0;
  1410 			break;
  1411 		    case 10: /* FCNVSD FPUL, DRn */
  1412 			if( ! IS_FPU_DOUBLESIZE() )
  1413 			    DRN(ir) = (double)FPULf;
  1414 			break;
  1415 		    case 11: /* FCNVDS DRn, FPUL */
  1416 			if( ! IS_FPU_DOUBLESIZE() )
  1417 			    FPULf = (float)DRN(ir);
  1418 			break;
  1419 		    case 14:/* FIPR    FVm, FVn */
  1420 			/* NO-OP when PR=1 */
  1421 			break;
  1422 		    case 15:
  1423 			if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
  1424 			    /* NO-OP when PR=1 */
  1425 			    break;
  1427 			else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */	
  1428 			    /* NO-OP when PR=1 */
  1429 			    break;
  1431 			else if( ir == 0xFBFD ) {
  1432 			    /* FRCHG   */
  1433 			    sh4r.fpscr ^= FPSCR_FR;
  1434 			    break;
  1436 			else if( ir == 0xF3FD ) {
  1437 			    /* FSCHG   */
  1438 			    sh4r.fpscr ^= FPSCR_SZ;
  1439 			    break;
  1441 		    default: UNDEF(ir);
  1443                     break;
  1444                 case 14:/* FMAC    FR0, FRm, FRn */
  1445                     DRN(ir) += DRM(ir)*DR0;
  1446                     break;
  1447                 default: UNDEF(ir);
  1449 	    } else { /* Single precision */
  1450 		switch( ir&0x000F ) {
  1451                 case 0: /* FADD    FRm, FRn */
  1452                     FRN(ir) += FRM(ir);
  1453                     break;
  1454                 case 1: /* FSUB    FRm, FRn */
  1455                     FRN(ir) -= FRM(ir);
  1456                     break;
  1457                 case 2: /* FMUL    FRm, FRn */
  1458                     FRN(ir) = FRN(ir) * FRM(ir);
  1459                     break;
  1460                 case 3: /* FDIV    FRm, FRn */
  1461                     FRN(ir) = FRN(ir) / FRM(ir);
  1462                     break;
  1463                 case 4: /* FCMP/EQ FRm, FRn */
  1464                     sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
  1465                     break;
  1466                 case 5: /* FCMP/GT FRm, FRn */
  1467                     sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
  1468                     break;
  1469                 case 6: /* FMOV.S  [Rm+R0], FRn */
  1470                     MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
  1471                     break;
  1472                 case 7: /* FMOV.S  FRm, [Rn+R0] */
  1473                     MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
  1474                     break;
  1475                 case 8: /* FMOV.S  [Rm], FRn */
  1476                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1477                     break;
  1478                 case 9: /* FMOV.S  [Rm++], FRn */
  1479                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1480                     RM(ir) += FP_WIDTH;
  1481                     break;
  1482                 case 10:/* FMOV.S  FRm, [Rn] */
  1483                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1484                     break;
  1485                 case 11:/* FMOV.S  FRm, [--Rn] */
  1486                     RN(ir) -= FP_WIDTH;
  1487                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1488                     break;
  1489                 case 12:/* FMOV    FRm, FRn */
  1490 		    if( IS_FPU_DOUBLESIZE() )
  1491 			DRN(ir) = DRM(ir);
  1492 		    else
  1493 			FRN(ir) = FRM(ir);
  1494                     break;
  1495                 case 13:
  1496                     switch( (ir&0x00F0) >> 4 ) {
  1497 		    case 0: /* FSTS    FPUL, FRn */
  1498 			FRN(ir) = FPULf;
  1499 			break;
  1500 		    case 1: /* FLDS    FRn,FPUL */
  1501 			FPULf = FRN(ir);
  1502 			break;
  1503 		    case 2: /* FLOAT   FPUL, FRn */
  1504 			FRN(ir) = (float)FPULi;
  1505 			break;
  1506 		    case 3: /* FTRC    FRn, FPUL */
  1507 			ftmp = FRN(ir);
  1508 			if( ftmp >= MAX_INTF )
  1509 			    FPULi = MAX_INT;
  1510 			else if( ftmp <= MIN_INTF )
  1511 			    FPULi = MIN_INT;
  1512 			else
  1513 			    FPULi = (int32_t)ftmp;
  1514 			break;
  1515 		    case 4: /* FNEG    FRn */
  1516 			FRN(ir) = -FRN(ir);
  1517 			break;
  1518 		    case 5: /* FABS    FRn */
  1519 			FRN(ir) = fabsf(FRN(ir));
  1520 			break;
  1521 		    case 6: /* FSQRT   FRn */
  1522 			FRN(ir) = sqrtf(FRN(ir));
  1523 			break;
  1524 		    case 7: /* FSRRA FRn */
  1525 			FRN(ir) = 1.0/sqrtf(FRN(ir));
  1526 			break;
  1527 		    case 8: /* FLDI0   FRn */
  1528 			FRN(ir) = 0.0;
  1529 			break;
  1530 		    case 9: /* FLDI1   FRn */
  1531 			FRN(ir) = 1.0;
  1532 			break;
  1533 		    case 10: /* FCNVSD FPUL, DRn */
  1534 			break;
  1535 		    case 11: /* FCNVDS DRn, FPUL */
  1536 			break;
  1537 		    case 14:/* FIPR    FVm, FVn */
  1538                             /* FIXME: This is not going to be entirely accurate
  1539                              * as the SH4 instruction is less precise. Also
  1540                              * need to check for 0s and infinities.
  1541                              */
  1543                             int tmp2 = FVN(ir);
  1544                             tmp = FVM(ir);
  1545                             FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  1546                                 FR(tmp+1)*FR(tmp2+1) +
  1547                                 FR(tmp+2)*FR(tmp2+2) +
  1548                                 FR(tmp+3)*FR(tmp2+3);
  1549                             break;
  1551 		    case 15:
  1552 			if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
  1553 			    tmp = FVN(ir);
  1554 			    float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
  1555 			    FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
  1556 				XF(8)*fv[2] + XF(12)*fv[3];
  1557 			    FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
  1558 				XF(9)*fv[2] + XF(13)*fv[3];
  1559 			    FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
  1560 				XF(10)*fv[2] + XF(14)*fv[3];
  1561 			    FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
  1562 				XF(11)*fv[2] + XF(15)*fv[3];
  1563 			    break;
  1565 			else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */
  1566 			    float angle = (((float)(short)(FPULi>>16)) +
  1567 					   (((float)(FPULi&0xFFFF))/65536.0)) *
  1568 				2 * M_PI;
  1569 			    int reg = FRNn(ir);
  1570 			    FR(reg) = sinf(angle);
  1571 			    FR(reg+1) = cosf(angle);
  1572 			    break;
  1574 			else if( ir == 0xFBFD ) {
  1575 			    /* FRCHG   */
  1576 			    sh4r.fpscr ^= FPSCR_FR;
  1577 			    break;
  1579 			else if( ir == 0xF3FD ) {
  1580 			    /* FSCHG   */
  1581 			    sh4r.fpscr ^= FPSCR_SZ;
  1582 			    break;
  1584 		    default: UNDEF(ir);
  1586                     break;
  1587                 case 14:/* FMAC    FR0, FRm, FRn */
  1588                     FRN(ir) += FRM(ir)*FR0;
  1589                     break;
  1590                 default: UNDEF(ir);
  1593 	    break;
  1595     sh4r.pc = sh4r.new_pc;
  1596     sh4r.new_pc += 2;
  1597     sh4r.in_delay_slot = 0;
.