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lxdream.org :: lxdream/src/sh4/mmu.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/mmu.c
changeset 963:1c3a0f67c603
prev960:2f0819278fdb
next968:6fb1481859a4
author nkeynes
date Thu Jan 15 03:54:21 2009 +0000 (13 years ago)
permissions -rw-r--r--
last change Fix missing prototype for mmu_vma_to_phys_disasm
Fix missing return value in mmu_ext_page_remapped
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     1 /**
     2  * $Id$
     3  *
     4  * SH4 MMU implementation based on address space page maps. This module
     5  * is responsible for all address decoding functions. 
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    19 #define MODULE sh4_module
    21 #include <stdio.h>
    22 #include <assert.h>
    23 #include "sh4/sh4mmio.h"
    24 #include "sh4/sh4core.h"
    25 #include "sh4/sh4trans.h"
    26 #include "dreamcast.h"
    27 #include "mem.h"
    28 #include "mmu.h"
    30 #define RAISE_TLB_ERROR(code, vpn) sh4_raise_tlb_exception(code, vpn)
    31 #define RAISE_MEM_ERROR(code, vpn) \
    32     MMIO_WRITE(MMU, TEA, vpn); \
    33     MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
    34     sh4_raise_exception(code);
    35 #define RAISE_TLB_MULTIHIT_ERROR(vpn) sh4_raise_tlb_multihit(vpn)
    37 /* An entry is a 1K entry if it's one of the mmu_utlb_1k_pages entries */
    38 #define IS_1K_PAGE_ENTRY(ent)  ( ((uintptr_t)(((struct utlb_1k_entry *)ent) - &mmu_utlb_1k_pages[0])) < UTLB_ENTRY_COUNT )
    40 /* Primary address space (used directly by SH4 cores) */
    41 mem_region_fn_t *sh4_address_space;
    42 mem_region_fn_t *sh4_user_address_space;
    44 /* Accessed from the UTLB accessor methods */
    45 uint32_t mmu_urc;
    46 uint32_t mmu_urb;
    47 static gboolean mmu_urc_overflow; /* If true, urc was set >= urb */  
    49 /* Module globals */
    50 static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT];
    51 static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT];
    52 static struct utlb_page_entry mmu_utlb_pages[UTLB_ENTRY_COUNT];
    53 static uint32_t mmu_lrui;
    54 static uint32_t mmu_asid; // current asid
    55 static struct utlb_default_regions *mmu_user_storequeue_regions;
    57 /* Structures for 1K page handling */
    58 static struct utlb_1k_entry mmu_utlb_1k_pages[UTLB_ENTRY_COUNT];
    59 static int mmu_utlb_1k_free_list[UTLB_ENTRY_COUNT];
    60 static int mmu_utlb_1k_free_index;
    63 /* Function prototypes */
    64 static void mmu_invalidate_tlb();
    65 static void mmu_utlb_register_all();
    66 static void mmu_utlb_remove_entry(int);
    67 static void mmu_utlb_insert_entry(int);
    68 static void mmu_register_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn );
    69 static void mmu_register_user_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn );
    70 static void mmu_set_tlb_enabled( int tlb_on );
    71 static void mmu_set_tlb_asid( uint32_t asid );
    72 static void mmu_set_storequeue_protected( int protected, int tlb_on );
    73 static gboolean mmu_utlb_map_pages( mem_region_fn_t priv_page, mem_region_fn_t user_page, sh4addr_t start_addr, int npages );
    74 static void mmu_utlb_remap_pages( gboolean remap_priv, gboolean remap_user, int entryNo );
    75 static gboolean mmu_utlb_unmap_pages( gboolean unmap_priv, gboolean unmap_user, sh4addr_t start_addr, int npages );
    76 static gboolean mmu_ext_page_remapped( sh4addr_t page, mem_region_fn_t fn, void *user_data );
    77 static void mmu_utlb_1k_init();
    78 static struct utlb_1k_entry *mmu_utlb_1k_alloc();
    79 static void mmu_utlb_1k_free( struct utlb_1k_entry *entry );
    80 static int mmu_read_urc();
    82 static void FASTCALL tlb_miss_read( sh4addr_t addr, void *exc );
    83 static int32_t FASTCALL tlb_protected_read( sh4addr_t addr, void *exc );
    84 static void FASTCALL tlb_protected_write( sh4addr_t addr, uint32_t val, void *exc );
    85 static void FASTCALL tlb_initial_write( sh4addr_t addr, uint32_t val, void *exc );
    86 static uint32_t get_tlb_size_mask( uint32_t flags );
    87 static uint32_t get_tlb_size_pages( uint32_t flags );
    89 #define DEFAULT_REGIONS 0
    90 #define DEFAULT_STOREQUEUE_REGIONS 1
    91 #define DEFAULT_STOREQUEUE_SQMD_REGIONS 2
    93 static struct utlb_default_regions mmu_default_regions[3] = {
    94         { &mem_region_tlb_miss, &mem_region_tlb_protected, &mem_region_tlb_multihit },
    95         { &p4_region_storequeue_miss, &p4_region_storequeue_protected, &p4_region_storequeue_multihit },
    96         { &p4_region_storequeue_sqmd_miss, &p4_region_storequeue_sqmd_protected, &p4_region_storequeue_sqmd_multihit } };
    98 #define IS_STOREQUEUE_PROTECTED() (mmu_user_storequeue_regions == &mmu_default_regions[DEFAULT_STOREQUEUE_SQMD_REGIONS])
   100 /*********************** Module public functions ****************************/
   102 /**
   103  * Allocate memory for the address space maps, and initialize them according
   104  * to the default (reset) values. (TLB is disabled by default)
   105  */
   107 void MMU_init()
   108 {
   109     sh4_address_space = mem_alloc_pages( sizeof(mem_region_fn_t) * 256 );
   110     sh4_user_address_space = mem_alloc_pages( sizeof(mem_region_fn_t) * 256 );
   111     mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
   113     mmu_set_tlb_enabled(0);
   114     mmu_register_user_mem_region( 0x80000000, 0x00000000, &mem_region_address_error );
   115     mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );                                
   117     /* Setup P4 tlb/cache access regions */
   118     mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
   119     mmu_register_mem_region( 0xE4000000, 0xF0000000, &mem_region_unmapped );
   120     mmu_register_mem_region( 0xF0000000, 0xF1000000, &p4_region_icache_addr );
   121     mmu_register_mem_region( 0xF1000000, 0xF2000000, &p4_region_icache_data );
   122     mmu_register_mem_region( 0xF2000000, 0xF3000000, &p4_region_itlb_addr );
   123     mmu_register_mem_region( 0xF3000000, 0xF4000000, &p4_region_itlb_data );
   124     mmu_register_mem_region( 0xF4000000, 0xF5000000, &p4_region_ocache_addr );
   125     mmu_register_mem_region( 0xF5000000, 0xF6000000, &p4_region_ocache_data );
   126     mmu_register_mem_region( 0xF6000000, 0xF7000000, &p4_region_utlb_addr );
   127     mmu_register_mem_region( 0xF7000000, 0xF8000000, &p4_region_utlb_data );
   128     mmu_register_mem_region( 0xF8000000, 0x00000000, &mem_region_unmapped );
   130     /* Setup P4 control region */
   131     mmu_register_mem_region( 0xFF000000, 0xFF001000, &mmio_region_MMU.fn );
   132     mmu_register_mem_region( 0xFF100000, 0xFF101000, &mmio_region_PMM.fn );
   133     mmu_register_mem_region( 0xFF200000, 0xFF201000, &mmio_region_UBC.fn );
   134     mmu_register_mem_region( 0xFF800000, 0xFF801000, &mmio_region_BSC.fn );
   135     mmu_register_mem_region( 0xFF900000, 0xFFA00000, &mem_region_unmapped ); // SDMR2 + SDMR3
   136     mmu_register_mem_region( 0xFFA00000, 0xFFA01000, &mmio_region_DMAC.fn );
   137     mmu_register_mem_region( 0xFFC00000, 0xFFC01000, &mmio_region_CPG.fn );
   138     mmu_register_mem_region( 0xFFC80000, 0xFFC81000, &mmio_region_RTC.fn );
   139     mmu_register_mem_region( 0xFFD00000, 0xFFD01000, &mmio_region_INTC.fn );
   140     mmu_register_mem_region( 0xFFD80000, 0xFFD81000, &mmio_region_TMU.fn );
   141     mmu_register_mem_region( 0xFFE00000, 0xFFE01000, &mmio_region_SCI.fn );
   142     mmu_register_mem_region( 0xFFE80000, 0xFFE81000, &mmio_region_SCIF.fn );
   143     mmu_register_mem_region( 0xFFF00000, 0xFFF01000, &mem_region_unmapped ); // H-UDI
   145     register_mem_page_remapped_hook( mmu_ext_page_remapped, NULL );
   146     mmu_utlb_1k_init();
   148     /* Ensure the code regions are executable (64-bit only). Although it might
   149      * be more portable to mmap these at runtime rather than using static decls
   150      */
   151 #if SIZEOF_VOID_P == 8
   152     mem_unprotect( mmu_utlb_pages, sizeof(mmu_utlb_pages) );
   153     mem_unprotect( mmu_utlb_1k_pages, sizeof(mmu_utlb_1k_pages) );
   154 #endif
   155 }
   157 void MMU_reset()
   158 {
   159     mmio_region_MMU_write( CCR, 0 );
   160     mmio_region_MMU_write( MMUCR, 0 );
   161 }
   163 void MMU_save_state( FILE *f )
   164 {
   165     mmu_read_urc();   
   166     fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f );
   167     fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f );
   168     fwrite( &mmu_urc, sizeof(mmu_urc), 1, f );
   169     fwrite( &mmu_urb, sizeof(mmu_urb), 1, f );
   170     fwrite( &mmu_lrui, sizeof(mmu_lrui), 1, f );
   171     fwrite( &mmu_asid, sizeof(mmu_asid), 1, f );
   172 }
   174 int MMU_load_state( FILE *f )
   175 {
   176     if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) {
   177         return 1;
   178     }
   179     if( fread( &mmu_utlb, sizeof(mmu_utlb), 1, f ) != 1 ) {
   180         return 1;
   181     }
   182     if( fread( &mmu_urc, sizeof(mmu_urc), 1, f ) != 1 ) {
   183         return 1;
   184     }
   185     if( fread( &mmu_urc, sizeof(mmu_urb), 1, f ) != 1 ) {
   186         return 1;
   187     }
   188     if( fread( &mmu_lrui, sizeof(mmu_lrui), 1, f ) != 1 ) {
   189         return 1;
   190     }
   191     if( fread( &mmu_asid, sizeof(mmu_asid), 1, f ) != 1 ) {
   192         return 1;
   193     }
   195     uint32_t mmucr = MMIO_READ(MMU,MMUCR);
   196     mmu_urc_overflow = mmu_urc >= mmu_urb;
   197     mmu_set_tlb_enabled(mmucr&MMUCR_AT);
   198     mmu_set_storequeue_protected(mmucr&MMUCR_SQMD, mmucr&MMUCR_AT);
   199     return 0;
   200 }
   202 /**
   203  * LDTLB instruction implementation. Copies PTEH, PTEL and PTEA into the UTLB
   204  * entry identified by MMUCR.URC. Does not modify MMUCR or the ITLB.
   205  */
   206 void MMU_ldtlb()
   207 {
   208     int urc = mmu_read_urc();
   209     if( mmu_utlb[urc].flags & TLB_VALID )
   210         mmu_utlb_remove_entry( urc );
   211     mmu_utlb[urc].vpn = MMIO_READ(MMU, PTEH) & 0xFFFFFC00;
   212     mmu_utlb[urc].asid = MMIO_READ(MMU, PTEH) & 0x000000FF;
   213     mmu_utlb[urc].ppn = MMIO_READ(MMU, PTEL) & 0x1FFFFC00;
   214     mmu_utlb[urc].flags = MMIO_READ(MMU, PTEL) & 0x00001FF;
   215     mmu_utlb[urc].pcmcia = MMIO_READ(MMU, PTEA);
   216     mmu_utlb[urc].mask = get_tlb_size_mask(mmu_utlb[urc].flags);
   217     if( mmu_utlb[urc].flags & TLB_VALID )
   218         mmu_utlb_insert_entry( urc );
   219 }
   222 MMIO_REGION_READ_FN( MMU, reg )
   223 {
   224     reg &= 0xFFF;
   225     switch( reg ) {
   226     case MMUCR:
   227         return MMIO_READ( MMU, MMUCR) | (mmu_read_urc()<<10) | ((mmu_urb&0x3F)<<18) | (mmu_lrui<<26);
   228     default:
   229         return MMIO_READ( MMU, reg );
   230     }
   231 }
   233 MMIO_REGION_WRITE_FN( MMU, reg, val )
   234 {
   235     uint32_t tmp;
   236     reg &= 0xFFF;
   237     switch(reg) {
   238     case SH4VER:
   239         return;
   240     case PTEH:
   241         val &= 0xFFFFFCFF;
   242         if( (val & 0xFF) != mmu_asid ) {
   243             mmu_set_tlb_asid( val&0xFF );
   244             sh4_icache.page_vma = -1; // invalidate icache as asid has changed
   245         }
   246         break;
   247     case PTEL:
   248         val &= 0x1FFFFDFF;
   249         break;
   250     case PTEA:
   251         val &= 0x0000000F;
   252         break;
   253     case TRA:
   254         val &= 0x000003FC;
   255         break;
   256     case EXPEVT:
   257     case INTEVT:
   258         val &= 0x00000FFF;
   259         break;
   260     case MMUCR:
   261         if( val & MMUCR_TI ) {
   262             mmu_invalidate_tlb();
   263         }
   264         mmu_urc = (val >> 10) & 0x3F;
   265         mmu_urb = (val >> 18) & 0x3F;
   266         if( mmu_urb == 0 ) {
   267             mmu_urb = 0x40;
   268         } else if( mmu_urc >= mmu_urb ) {
   269             mmu_urc_overflow = TRUE;
   270         }
   271         mmu_lrui = (val >> 26) & 0x3F;
   272         val &= 0x00000301;
   273         tmp = MMIO_READ( MMU, MMUCR );
   274         if( (val ^ tmp) & (MMUCR_SQMD) ) {
   275             mmu_set_storequeue_protected( val & MMUCR_SQMD, val&MMUCR_AT );
   276         }
   277         if( (val ^ tmp) & (MMUCR_AT) ) {
   278             // AT flag has changed state - flush the xlt cache as all bets
   279             // are off now. We also need to force an immediate exit from the
   280             // current block
   281             mmu_set_tlb_enabled( val & MMUCR_AT );
   282             MMIO_WRITE( MMU, MMUCR, val );
   283             sh4_core_exit( CORE_EXIT_FLUSH_ICACHE );
   284             xlat_flush_cache(); // If we're not running, flush the cache anyway
   285         }
   286         break;
   287     case CCR:
   288         CCN_set_cache_control( val );
   289         val &= 0x81A7;
   290         break;
   291     case MMUUNK1:
   292         /* Note that if the high bit is set, this appears to reset the machine.
   293          * Not emulating this behaviour yet until we know why...
   294          */
   295         val &= 0x00010007;
   296         break;
   297     case QACR0:
   298     case QACR1:
   299         val &= 0x0000001C;
   300         break;
   301     case PMCR1:
   302         PMM_write_control(0, val);
   303         val &= 0x0000C13F;
   304         break;
   305     case PMCR2:
   306         PMM_write_control(1, val);
   307         val &= 0x0000C13F;
   308         break;
   309     default:
   310         break;
   311     }
   312     MMIO_WRITE( MMU, reg, val );
   313 }
   315 /********************** 1K Page handling ***********************/
   316 /* Since we use 4K pages as our native page size, 1K pages need a bit of extra
   317  * effort to manage - we justify this on the basis that most programs won't
   318  * actually use 1K pages, so we may as well optimize for the common case.
   319  * 
   320  * Implementation uses an intermediate page entry (the utlb_1k_entry) that
   321  * redirects requests to the 'real' page entry. These are allocated on an
   322  * as-needed basis, and returned to the pool when all subpages are empty.
   323  */ 
   324 static void mmu_utlb_1k_init()
   325 {
   326     int i;
   327     for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   328         mmu_utlb_1k_free_list[i] = i;
   329         mmu_utlb_1k_init_vtable( &mmu_utlb_1k_pages[i] );
   330     }
   331     mmu_utlb_1k_free_index = 0;
   332 }
   334 static struct utlb_1k_entry *mmu_utlb_1k_alloc()
   335 {
   336     assert( mmu_utlb_1k_free_index < UTLB_ENTRY_COUNT );
   337     struct utlb_1k_entry *entry = &mmu_utlb_1k_pages[mmu_utlb_1k_free_index++];
   338     return entry;
   339 }    
   341 static void mmu_utlb_1k_free( struct utlb_1k_entry *ent )
   342 {
   343     unsigned int entryNo = ent - &mmu_utlb_1k_pages[0];
   344     assert( entryNo < UTLB_ENTRY_COUNT );
   345     assert( mmu_utlb_1k_free_index > 0 );
   346     mmu_utlb_1k_free_list[--mmu_utlb_1k_free_index] = entryNo;
   347 }
   350 /********************** Address space maintenance *************************/
   352 /**
   353  * MMU accessor functions just increment URC - fixup here if necessary
   354  */
   355 static int mmu_read_urc()
   356 {
   357     if( mmu_urc_overflow ) {
   358         if( mmu_urc >= 0x40 ) {
   359             mmu_urc_overflow = FALSE;
   360             mmu_urc -= 0x40;
   361             mmu_urc %= mmu_urb;
   362         }
   363     } else {
   364         mmu_urc %= mmu_urb;
   365     }
   366     return mmu_urc;
   367 }
   369 static void mmu_register_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn )
   370 {
   371     int count = (end - start) >> 12;
   372     mem_region_fn_t *ptr = &sh4_address_space[start>>12];
   373     while( count-- > 0 ) {
   374         *ptr++ = fn;
   375     }
   376 }
   377 static void mmu_register_user_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn )
   378 {
   379     int count = (end - start) >> 12;
   380     mem_region_fn_t *ptr = &sh4_user_address_space[start>>12];
   381     while( count-- > 0 ) {
   382         *ptr++ = fn;
   383     }
   384 }
   386 static gboolean mmu_ext_page_remapped( sh4addr_t page, mem_region_fn_t fn, void *user_data )
   387 {
   388     int i;
   389     if( (MMIO_READ(MMU,MMUCR)) & MMUCR_AT ) {
   390         /* TLB on */
   391         sh4_address_space[(page|0x80000000)>>12] = fn; /* Direct map to P1 and P2 */
   392         sh4_address_space[(page|0xA0000000)>>12] = fn;
   393         /* Scan UTLB and update any direct-referencing entries */
   394     } else {
   395         /* Direct map to U0, P0, P1, P2, P3 */
   396         for( i=0; i<= 0xC0000000; i+= 0x20000000 ) {
   397             sh4_address_space[(page|i)>>12] = fn;
   398         }
   399         for( i=0; i < 0x80000000; i+= 0x20000000 ) {
   400             sh4_user_address_space[(page|i)>>12] = fn;
   401         }
   402     }
   403     return TRUE;
   404 }
   406 static void mmu_set_tlb_enabled( int tlb_on )
   407 {
   408     mem_region_fn_t *ptr, *uptr;
   409     int i;
   411     /* Reset the storequeue area */
   413     if( tlb_on ) {
   414         mmu_register_mem_region(0x00000000, 0x80000000, &mem_region_tlb_miss );
   415         mmu_register_mem_region(0xC0000000, 0xE0000000, &mem_region_tlb_miss );
   416         mmu_register_user_mem_region(0x00000000, 0x80000000, &mem_region_tlb_miss );
   418         /* Default SQ prefetch goes to TLB miss (?) */
   419         mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue_miss );
   420         mmu_register_user_mem_region( 0xE0000000, 0xE4000000, mmu_user_storequeue_regions->tlb_miss );
   421         mmu_utlb_register_all();
   422     } else {
   423         for( i=0, ptr = sh4_address_space; i<7; i++, ptr += LXDREAM_PAGE_TABLE_ENTRIES ) {
   424             memcpy( ptr, ext_address_space, sizeof(mem_region_fn_t) * LXDREAM_PAGE_TABLE_ENTRIES );
   425         }
   426         for( i=0, ptr = sh4_user_address_space; i<4; i++, ptr += LXDREAM_PAGE_TABLE_ENTRIES ) {
   427             memcpy( ptr, ext_address_space, sizeof(mem_region_fn_t) * LXDREAM_PAGE_TABLE_ENTRIES );
   428         }
   430         mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
   431         if( IS_STOREQUEUE_PROTECTED() ) {
   432             mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue_sqmd );
   433         } else {
   434             mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
   435         }
   436     }
   438 }
   440 /**
   441  * Flip the SQMD switch - this is rather expensive, so will need to be changed if
   442  * anything expects to do this frequently.
   443  */
   444 static void mmu_set_storequeue_protected( int protected, int tlb_on ) 
   445 {
   446     mem_region_fn_t nontlb_region;
   447     int i;
   449     if( protected ) {
   450         mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_SQMD_REGIONS];
   451         nontlb_region = &p4_region_storequeue_sqmd;
   452     } else {
   453         mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
   454         nontlb_region = &p4_region_storequeue; 
   455     }
   457     if( tlb_on ) {
   458         mmu_register_user_mem_region( 0xE0000000, 0xE4000000, mmu_user_storequeue_regions->tlb_miss );
   459         for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   460             if( (mmu_utlb[i].vpn & 0xFC000000) == 0xE0000000 ) {
   461                 mmu_utlb_insert_entry(i);
   462             }
   463         }
   464     } else {
   465         mmu_register_user_mem_region( 0xE0000000, 0xE4000000, nontlb_region ); 
   466     }
   468 }
   470 static void mmu_set_tlb_asid( uint32_t asid )
   471 {
   472     /* Scan for pages that need to be remapped */
   473     int i;
   474     if( IS_SV_ENABLED() ) {
   475         for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   476             if( mmu_utlb[i].flags & TLB_VALID ) {
   477                 if( (mmu_utlb[i].flags & TLB_SHARE) == 0 ) {
   478                     if( mmu_utlb[i].asid == mmu_asid ) { // Matches old ASID - unmap out
   479                         if( !mmu_utlb_unmap_pages( FALSE, TRUE, mmu_utlb[i].vpn&mmu_utlb[i].mask,
   480                                 get_tlb_size_pages(mmu_utlb[i].flags) ) )
   481                             mmu_utlb_remap_pages( FALSE, TRUE, i );
   482                     } else if( mmu_utlb[i].asid == asid ) { // Matches new ASID - map in
   483                         mmu_utlb_map_pages( NULL, mmu_utlb_pages[i].user_fn, 
   484                                 mmu_utlb[i].vpn&mmu_utlb[i].mask, 
   485                                 get_tlb_size_pages(mmu_utlb[i].flags) );  
   486                     }
   487                 }
   488             }
   489         }
   490     } else {
   491         // Remap both Priv+user pages
   492         for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   493             if( mmu_utlb[i].flags & TLB_VALID ) {
   494                 if( (mmu_utlb[i].flags & TLB_SHARE) == 0 ) {
   495                     if( mmu_utlb[i].asid == mmu_asid ) { // Matches old ASID - unmap out
   496                         if( !mmu_utlb_unmap_pages( TRUE, TRUE, mmu_utlb[i].vpn&mmu_utlb[i].mask,
   497                                 get_tlb_size_pages(mmu_utlb[i].flags) ) )
   498                             mmu_utlb_remap_pages( TRUE, TRUE, i );
   499                     } else if( mmu_utlb[i].asid == asid ) { // Matches new ASID - map in
   500                         mmu_utlb_map_pages( &mmu_utlb_pages[i].fn, mmu_utlb_pages[i].user_fn, 
   501                                 mmu_utlb[i].vpn&mmu_utlb[i].mask, 
   502                                 get_tlb_size_pages(mmu_utlb[i].flags) );  
   503                     }
   504                 }
   505             }
   506         }
   507     }
   509     mmu_asid = asid;
   510 }
   512 static uint32_t get_tlb_size_mask( uint32_t flags )
   513 {
   514     switch( flags & TLB_SIZE_MASK ) {
   515     case TLB_SIZE_1K: return MASK_1K;
   516     case TLB_SIZE_4K: return MASK_4K;
   517     case TLB_SIZE_64K: return MASK_64K;
   518     case TLB_SIZE_1M: return MASK_1M;
   519     default: return 0; /* Unreachable */
   520     }
   521 }
   522 static uint32_t get_tlb_size_pages( uint32_t flags )
   523 {
   524     switch( flags & TLB_SIZE_MASK ) {
   525     case TLB_SIZE_1K: return 0;
   526     case TLB_SIZE_4K: return 1;
   527     case TLB_SIZE_64K: return 16;
   528     case TLB_SIZE_1M: return 256;
   529     default: return 0; /* Unreachable */
   530     }
   531 }
   533 /**
   534  * Add a new TLB entry mapping to the address space table. If any of the pages
   535  * are already mapped, they are mapped to the TLB multi-hit page instead.
   536  * @return FALSE if a TLB multihit situation was detected, otherwise TRUE.
   537  */ 
   538 static gboolean mmu_utlb_map_pages( mem_region_fn_t priv_page, mem_region_fn_t user_page, sh4addr_t start_addr, int npages )
   539 {
   540     mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
   541     mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
   542     struct utlb_default_regions *privdefs = &mmu_default_regions[DEFAULT_REGIONS];
   543     struct utlb_default_regions *userdefs = privdefs;    
   545     gboolean mapping_ok = TRUE;
   546     int i;
   548     if( (start_addr & 0xFC000000) == 0xE0000000 ) {
   549         /* Storequeue mapping */
   550         privdefs = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
   551         userdefs = mmu_user_storequeue_regions;
   552     } else if( (start_addr & 0xE0000000) == 0xC0000000 ) {
   553         user_page = NULL; /* No user access to P3 region */
   554     } else if( start_addr >= 0x80000000 ) {
   555         return TRUE; // No mapping - legal but meaningless
   556     }
   558     if( npages == 0 ) {
   559         struct utlb_1k_entry *ent;
   560         int i, idx = (start_addr >> 10) & 0x03;
   561         if( IS_1K_PAGE_ENTRY(*ptr) ) {
   562             ent = (struct utlb_1k_entry *)*ptr;
   563         } else {
   564             ent = mmu_utlb_1k_alloc();
   565             /* New 1K struct - init to previous contents of region */
   566             for( i=0; i<4; i++ ) {
   567                 ent->subpages[i] = *ptr;
   568                 ent->user_subpages[i] = *uptr;
   569             }
   570             *ptr = &ent->fn;
   571             *uptr = &ent->user_fn;
   572         }
   574         if( priv_page != NULL ) {
   575             if( ent->subpages[idx] == privdefs->tlb_miss ) {
   576                 ent->subpages[idx] = priv_page;
   577             } else {
   578                 mapping_ok = FALSE;
   579                 ent->subpages[idx] = privdefs->tlb_multihit;
   580             }
   581         }
   582         if( user_page != NULL ) {
   583             if( ent->user_subpages[idx] == userdefs->tlb_miss ) {
   584                 ent->user_subpages[idx] = user_page;
   585             } else {
   586                 mapping_ok = FALSE;
   587                 ent->user_subpages[idx] = userdefs->tlb_multihit;
   588             }
   589         }
   591     } else {
   592         if( priv_page != NULL ) {
   593             /* Privileged mapping only */
   594             for( i=0; i<npages; i++ ) {
   595                 if( *ptr == privdefs->tlb_miss ) {
   596                     *ptr++ = priv_page;
   597                 } else {
   598                     mapping_ok = FALSE;
   599                     *ptr++ = privdefs->tlb_multihit;
   600                 }
   601             }
   602         }
   603         if( user_page != NULL ) {
   604             /* User mapping only (eg ASID change remap w/ SV=1) */
   605             for( i=0; i<npages; i++ ) {
   606                 if( *uptr == userdefs->tlb_miss ) {
   607                     *uptr++ = user_page;
   608                 } else {
   609                     mapping_ok = FALSE;
   610                     *uptr++ = userdefs->tlb_multihit;
   611                 }
   612             }        
   613         }
   614     }
   616     return mapping_ok;
   617 }
   619 /**
   620  * Remap any pages within the region covered by entryNo, but not including 
   621  * entryNo itself. This is used to reestablish pages that were previously
   622  * covered by a multi-hit exception region when one of the pages is removed.
   623  */
   624 static void mmu_utlb_remap_pages( gboolean remap_priv, gboolean remap_user, int entryNo )
   625 {
   626     int mask = mmu_utlb[entryNo].mask;
   627     uint32_t remap_addr = mmu_utlb[entryNo].vpn & mask;
   628     int i;
   630     for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   631         if( i != entryNo && (mmu_utlb[i].vpn & mask) == remap_addr && (mmu_utlb[i].flags & TLB_VALID) ) {
   632             /* Overlapping region */
   633             mem_region_fn_t priv_page = (remap_priv ? &mmu_utlb_pages[i].fn : NULL);
   634             mem_region_fn_t user_page = (remap_priv ? mmu_utlb_pages[i].user_fn : NULL);
   635             uint32_t start_addr;
   636             int npages;
   638             if( mmu_utlb[i].mask >= mask ) {
   639                 /* entry is no larger than the area we're replacing - map completely */
   640                 start_addr = mmu_utlb[i].vpn & mmu_utlb[i].mask;
   641                 npages = get_tlb_size_pages( mmu_utlb[i].flags );
   642             } else {
   643                 /* Otherwise map subset - region covered by removed page */
   644                 start_addr = remap_addr;
   645                 npages = get_tlb_size_pages( mmu_utlb[entryNo].flags );
   646             }
   648             if( (mmu_utlb[i].flags & TLB_SHARE) || mmu_utlb[i].asid == mmu_asid ) { 
   649                 mmu_utlb_map_pages( priv_page, user_page, start_addr, npages );
   650             } else if( IS_SV_ENABLED() ) {
   651                 mmu_utlb_map_pages( priv_page, NULL, start_addr, npages );
   652             }
   654         }
   655     }
   656 }
   658 /**
   659  * Remove a previous TLB mapping (replacing them with the TLB miss region).
   660  * @return FALSE if any pages were previously mapped to the TLB multihit page, 
   661  * otherwise TRUE. In either case, all pages in the region are cleared to TLB miss.
   662  */
   663 static gboolean mmu_utlb_unmap_pages( gboolean unmap_priv, gboolean unmap_user, sh4addr_t start_addr, int npages )
   664 {
   665     mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
   666     mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
   667     struct utlb_default_regions *privdefs = &mmu_default_regions[DEFAULT_REGIONS];
   668     struct utlb_default_regions *userdefs = privdefs;
   670     gboolean unmapping_ok = TRUE;
   671     int i;
   673     if( (start_addr & 0xFC000000) == 0xE0000000 ) {
   674         /* Storequeue mapping */
   675         privdefs = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
   676         userdefs = mmu_user_storequeue_regions;
   677     } else if( (start_addr & 0xE0000000) == 0xC0000000 ) {
   678         unmap_user = FALSE;
   679     } else if( start_addr >= 0x80000000 ) {
   680         return TRUE; // No mapping - legal but meaningless
   681     }
   683     if( npages == 0 ) { // 1K page
   684         assert( IS_1K_PAGE_ENTRY( *ptr ) );
   685         struct utlb_1k_entry *ent = (struct utlb_1k_entry *)*ptr;
   686         int i, idx = (start_addr >> 10) & 0x03, mergeable=1;
   687         if( ent->subpages[idx] == privdefs->tlb_multihit ) {
   688             unmapping_ok = FALSE;
   689         }
   690         if( unmap_priv )
   691             ent->subpages[idx] = privdefs->tlb_miss;
   692         if( unmap_user )
   693             ent->user_subpages[idx] = userdefs->tlb_miss;
   695         /* If all 4 subpages have the same content, merge them together and
   696          * release the 1K entry
   697          */
   698         mem_region_fn_t priv_page = ent->subpages[0];
   699         mem_region_fn_t user_page = ent->user_subpages[0];
   700         for( i=1; i<4; i++ ) {
   701             if( priv_page != ent->subpages[i] || user_page != ent->user_subpages[i] ) {
   702                 mergeable = 0;
   703                 break;
   704             }
   705         }
   706         if( mergeable ) {
   707             mmu_utlb_1k_free(ent);
   708             *ptr = priv_page;
   709             *uptr = user_page;
   710         }
   711     } else {
   712         if( unmap_priv ) {
   713             /* Privileged (un)mapping */
   714             for( i=0; i<npages; i++ ) {
   715                 if( *ptr == privdefs->tlb_multihit ) {
   716                     unmapping_ok = FALSE;
   717                 }
   718                 *ptr++ = privdefs->tlb_miss;
   719             }
   720         }
   721         if( unmap_user ) {
   722             /* User (un)mapping */
   723             for( i=0; i<npages; i++ ) {
   724                 if( *uptr == userdefs->tlb_multihit ) {
   725                     unmapping_ok = FALSE;
   726                 }
   727                 *uptr++ = userdefs->tlb_miss;
   728             }            
   729         }
   730     }
   732     return unmapping_ok;
   733 }
   735 static void mmu_utlb_insert_entry( int entry )
   736 {
   737     struct utlb_entry *ent = &mmu_utlb[entry];
   738     mem_region_fn_t page = &mmu_utlb_pages[entry].fn;
   739     mem_region_fn_t upage;
   740     sh4addr_t start_addr = ent->vpn & ent->mask;
   741     int npages = get_tlb_size_pages(ent->flags);
   743     if( (start_addr & 0xFC000000) == 0xE0000000 ) {
   744         /* Store queue mappings are a bit different - normal access is fixed to
   745          * the store queue register block, and we only map prefetches through
   746          * the TLB 
   747          */
   748         mmu_utlb_init_storequeue_vtable( ent, &mmu_utlb_pages[entry] );
   750         if( (ent->flags & TLB_USERMODE) == 0 ) {
   751             upage = mmu_user_storequeue_regions->tlb_prot;
   752         } else if( IS_STOREQUEUE_PROTECTED() ) {
   753             upage = &p4_region_storequeue_sqmd;
   754         } else {
   755             upage = page;
   756         }
   758     }  else {
   760         if( (ent->flags & TLB_USERMODE) == 0 ) {
   761             upage = &mem_region_tlb_protected;
   762         } else {        
   763             upage = page;
   764         }
   766         if( (ent->flags & TLB_WRITABLE) == 0 ) {
   767             page->write_long = (mem_write_fn_t)tlb_protected_write;
   768             page->write_word = (mem_write_fn_t)tlb_protected_write;
   769             page->write_byte = (mem_write_fn_t)tlb_protected_write;
   770             page->write_burst = (mem_write_burst_fn_t)tlb_protected_write;
   771             mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], FALSE );
   772         } else if( (ent->flags & TLB_DIRTY) == 0 ) {
   773             page->write_long = (mem_write_fn_t)tlb_initial_write;
   774             page->write_word = (mem_write_fn_t)tlb_initial_write;
   775             page->write_byte = (mem_write_fn_t)tlb_initial_write;
   776             page->write_burst = (mem_write_burst_fn_t)tlb_initial_write;
   777             mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], FALSE );
   778         } else {
   779             mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], TRUE );
   780         }
   781     }
   783     mmu_utlb_pages[entry].user_fn = upage;
   785     /* Is page visible? */
   786     if( (ent->flags & TLB_SHARE) || ent->asid == mmu_asid ) { 
   787         mmu_utlb_map_pages( page, upage, start_addr, npages );
   788     } else if( IS_SV_ENABLED() ) {
   789         mmu_utlb_map_pages( page, NULL, start_addr, npages );
   790     }
   791 }
   793 static void mmu_utlb_remove_entry( int entry )
   794 {
   795     int i, j;
   796     struct utlb_entry *ent = &mmu_utlb[entry];
   797     sh4addr_t start_addr = ent->vpn&ent->mask;
   798     mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
   799     mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
   800     gboolean unmap_user;
   801     int npages = get_tlb_size_pages(ent->flags);
   803     if( (ent->flags & TLB_SHARE) || ent->asid == mmu_asid ) {
   804         unmap_user = TRUE;
   805     } else if( IS_SV_ENABLED() ) {
   806         unmap_user = FALSE;
   807     } else {
   808         return; // Not mapped
   809     }
   811     gboolean clean_unmap = mmu_utlb_unmap_pages( TRUE, unmap_user, start_addr, npages );
   813     if( !clean_unmap ) {
   814         mmu_utlb_remap_pages( TRUE, unmap_user, entry );
   815     }
   816 }
   818 static void mmu_utlb_register_all()
   819 {
   820     int i;
   821     for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   822         if( mmu_utlb[i].flags & TLB_VALID ) 
   823             mmu_utlb_insert_entry( i );
   824     }
   825 }
   827 static void mmu_invalidate_tlb()
   828 {
   829     int i;
   830     for( i=0; i<ITLB_ENTRY_COUNT; i++ ) {
   831         mmu_itlb[i].flags &= (~TLB_VALID);
   832     }
   833     if( IS_TLB_ENABLED() ) {
   834         for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   835             if( mmu_utlb[i].flags & TLB_VALID ) {
   836                 mmu_utlb_remove_entry( i );
   837             }
   838         }
   839     }
   840     for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   841         mmu_utlb[i].flags &= (~TLB_VALID);
   842     }
   843 }
   845 /******************************************************************************/
   846 /*                        MMU TLB address translation                         */
   847 /******************************************************************************/
   849 /**
   850  * Translate a 32-bit address into a UTLB entry number. Does not check for
   851  * page protection etc.
   852  * @return the entryNo if found, -1 if not found, and -2 for a multi-hit.
   853  */
   854 int mmu_utlb_entry_for_vpn( uint32_t vpn )
   855 {
   856     mem_region_fn_t fn = sh4_address_space[vpn>>12];
   857     if( fn >= &mmu_utlb_pages[0].fn && fn < &mmu_utlb_pages[UTLB_ENTRY_COUNT].fn ) {
   858         return ((struct utlb_page_entry *)fn) - &mmu_utlb_pages[0];
   859     } else if( fn == &mem_region_tlb_multihit ) {
   860         return -2;
   861     } else {
   862         return -1;
   863     }
   864 }
   867 /**
   868  * Perform the actual utlb lookup w/ asid matching.
   869  * Possible utcomes are:
   870  *   0..63 Single match - good, return entry found
   871  *   -1 No match - raise a tlb data miss exception
   872  *   -2 Multiple matches - raise a multi-hit exception (reset)
   873  * @param vpn virtual address to resolve
   874  * @return the resultant UTLB entry, or an error.
   875  */
   876 static inline int mmu_utlb_lookup_vpn_asid( uint32_t vpn )
   877 {
   878     int result = -1;
   879     unsigned int i;
   881     mmu_urc++;
   882     if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
   883         mmu_urc = 0;
   884     }
   886     for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
   887         if( (mmu_utlb[i].flags & TLB_VALID) &&
   888                 ((mmu_utlb[i].flags & TLB_SHARE) || mmu_asid == mmu_utlb[i].asid) &&
   889                 ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
   890             if( result != -1 ) {
   891                 return -2;
   892             }
   893             result = i;
   894         }
   895     }
   896     return result;
   897 }
   899 /**
   900  * Perform the actual utlb lookup matching on vpn only
   901  * Possible utcomes are:
   902  *   0..63 Single match - good, return entry found
   903  *   -1 No match - raise a tlb data miss exception
   904  *   -2 Multiple matches - raise a multi-hit exception (reset)
   905  * @param vpn virtual address to resolve
   906  * @return the resultant UTLB entry, or an error.
   907  */
   908 static inline int mmu_utlb_lookup_vpn( uint32_t vpn )
   909 {
   910     int result = -1;
   911     unsigned int i;
   913     mmu_urc++;
   914     if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
   915         mmu_urc = 0;
   916     }
   918     for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
   919         if( (mmu_utlb[i].flags & TLB_VALID) &&
   920                 ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
   921             if( result != -1 ) {
   922                 return -2;
   923             }
   924             result = i;
   925         }
   926     }
   928     return result;
   929 }
   931 /**
   932  * Update the ITLB by replacing the LRU entry with the specified UTLB entry.
   933  * @return the number (0-3) of the replaced entry.
   934  */
   935 static int inline mmu_itlb_update_from_utlb( int entryNo )
   936 {
   937     int replace;
   938     /* Determine entry to replace based on lrui */
   939     if( (mmu_lrui & 0x38) == 0x38 ) {
   940         replace = 0;
   941         mmu_lrui = mmu_lrui & 0x07;
   942     } else if( (mmu_lrui & 0x26) == 0x06 ) {
   943         replace = 1;
   944         mmu_lrui = (mmu_lrui & 0x19) | 0x20;
   945     } else if( (mmu_lrui & 0x15) == 0x01 ) {
   946         replace = 2;
   947         mmu_lrui = (mmu_lrui & 0x3E) | 0x14;
   948     } else { // Note - gets invalid entries too
   949         replace = 3;
   950         mmu_lrui = (mmu_lrui | 0x0B);
   951     }
   953     mmu_itlb[replace].vpn = mmu_utlb[entryNo].vpn;
   954     mmu_itlb[replace].mask = mmu_utlb[entryNo].mask;
   955     mmu_itlb[replace].ppn = mmu_utlb[entryNo].ppn;
   956     mmu_itlb[replace].asid = mmu_utlb[entryNo].asid;
   957     mmu_itlb[replace].flags = mmu_utlb[entryNo].flags & 0x01DA;
   958     return replace;
   959 }
   961 /**
   962  * Perform the actual itlb lookup w/ asid protection
   963  * Possible utcomes are:
   964  *   0..63 Single match - good, return entry found
   965  *   -1 No match - raise a tlb data miss exception
   966  *   -2 Multiple matches - raise a multi-hit exception (reset)
   967  * @param vpn virtual address to resolve
   968  * @return the resultant ITLB entry, or an error.
   969  */
   970 static inline int mmu_itlb_lookup_vpn_asid( uint32_t vpn )
   971 {
   972     int result = -1;
   973     unsigned int i;
   975     for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
   976         if( (mmu_itlb[i].flags & TLB_VALID) &&
   977                 ((mmu_itlb[i].flags & TLB_SHARE) || mmu_asid == mmu_itlb[i].asid) &&
   978                 ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
   979             if( result != -1 ) {
   980                 return -2;
   981             }
   982             result = i;
   983         }
   984     }
   986     if( result == -1 ) {
   987         int utlbEntry = mmu_utlb_entry_for_vpn( vpn );
   988         if( utlbEntry < 0 ) {
   989             return utlbEntry;
   990         } else {
   991             return mmu_itlb_update_from_utlb( utlbEntry );
   992         }
   993     }
   995     switch( result ) {
   996     case 0: mmu_lrui = (mmu_lrui & 0x07); break;
   997     case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
   998     case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
   999     case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
  1002     return result;
  1005 /**
  1006  * Perform the actual itlb lookup on vpn only
  1007  * Possible utcomes are:
  1008  *   0..63 Single match - good, return entry found
  1009  *   -1 No match - raise a tlb data miss exception
  1010  *   -2 Multiple matches - raise a multi-hit exception (reset)
  1011  * @param vpn virtual address to resolve
  1012  * @return the resultant ITLB entry, or an error.
  1013  */
  1014 static inline int mmu_itlb_lookup_vpn( uint32_t vpn )
  1016     int result = -1;
  1017     unsigned int i;
  1019     for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
  1020         if( (mmu_itlb[i].flags & TLB_VALID) &&
  1021                 ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
  1022             if( result != -1 ) {
  1023                 return -2;
  1025             result = i;
  1029     if( result == -1 ) {
  1030         int utlbEntry = mmu_utlb_lookup_vpn( vpn );
  1031         if( utlbEntry < 0 ) {
  1032             return utlbEntry;
  1033         } else {
  1034             return mmu_itlb_update_from_utlb( utlbEntry );
  1038     switch( result ) {
  1039     case 0: mmu_lrui = (mmu_lrui & 0x07); break;
  1040     case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
  1041     case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
  1042     case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
  1045     return result;
  1048 /**
  1049  * Update the icache for an untranslated address
  1050  */
  1051 static inline void mmu_update_icache_phys( sh4addr_t addr )
  1053     if( (addr & 0x1C000000) == 0x0C000000 ) {
  1054         /* Main ram */
  1055         sh4_icache.page_vma = addr & 0xFF000000;
  1056         sh4_icache.page_ppa = 0x0C000000;
  1057         sh4_icache.mask = 0xFF000000;
  1058         sh4_icache.page = dc_main_ram;
  1059     } else if( (addr & 0x1FE00000) == 0 ) {
  1060         /* BIOS ROM */
  1061         sh4_icache.page_vma = addr & 0xFFE00000;
  1062         sh4_icache.page_ppa = 0;
  1063         sh4_icache.mask = 0xFFE00000;
  1064         sh4_icache.page = dc_boot_rom;
  1065     } else {
  1066         /* not supported */
  1067         sh4_icache.page_vma = -1;
  1071 /**
  1072  * Update the sh4_icache structure to describe the page(s) containing the
  1073  * given vma. If the address does not reference a RAM/ROM region, the icache
  1074  * will be invalidated instead.
  1075  * If AT is on, this method will raise TLB exceptions normally
  1076  * (hence this method should only be used immediately prior to execution of
  1077  * code), and otherwise will set the icache according to the matching TLB entry.
  1078  * If AT is off, this method will set the entire referenced RAM/ROM region in
  1079  * the icache.
  1080  * @return TRUE if the update completed (successfully or otherwise), FALSE
  1081  * if an exception was raised.
  1082  */
  1083 gboolean FASTCALL mmu_update_icache( sh4vma_t addr )
  1085     int entryNo;
  1086     if( IS_SH4_PRIVMODE()  ) {
  1087         if( addr & 0x80000000 ) {
  1088             if( addr < 0xC0000000 ) {
  1089                 /* P1, P2 and P4 regions are pass-through (no translation) */
  1090                 mmu_update_icache_phys(addr);
  1091                 return TRUE;
  1092             } else if( addr >= 0xE0000000 && addr < 0xFFFFFF00 ) {
  1093                 RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
  1094                 return FALSE;
  1098         uint32_t mmucr = MMIO_READ(MMU,MMUCR);
  1099         if( (mmucr & MMUCR_AT) == 0 ) {
  1100             mmu_update_icache_phys(addr);
  1101             return TRUE;
  1104         if( (mmucr & MMUCR_SV) == 0 )
  1105         	entryNo = mmu_itlb_lookup_vpn_asid( addr );
  1106         else
  1107         	entryNo = mmu_itlb_lookup_vpn( addr );
  1108     } else {
  1109         if( addr & 0x80000000 ) {
  1110             RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
  1111             return FALSE;
  1114         uint32_t mmucr = MMIO_READ(MMU,MMUCR);
  1115         if( (mmucr & MMUCR_AT) == 0 ) {
  1116             mmu_update_icache_phys(addr);
  1117             return TRUE;
  1120         entryNo = mmu_itlb_lookup_vpn_asid( addr );
  1122         if( entryNo != -1 && (mmu_itlb[entryNo].flags & TLB_USERMODE) == 0 ) {
  1123             RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
  1124             return FALSE;
  1128     switch(entryNo) {
  1129     case -1:
  1130     RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
  1131     return FALSE;
  1132     case -2:
  1133     RAISE_TLB_MULTIHIT_ERROR(addr);
  1134     return FALSE;
  1135     default:
  1136         sh4_icache.page_ppa = mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask;
  1137         sh4_icache.page = mem_get_region( sh4_icache.page_ppa );
  1138         if( sh4_icache.page == NULL ) {
  1139             sh4_icache.page_vma = -1;
  1140         } else {
  1141             sh4_icache.page_vma = mmu_itlb[entryNo].vpn & mmu_itlb[entryNo].mask;
  1142             sh4_icache.mask = mmu_itlb[entryNo].mask;
  1144         return TRUE;
  1148 /**
  1149  * Translate address for disassembly purposes (ie performs an instruction
  1150  * lookup) - does not raise exceptions or modify any state, and ignores
  1151  * protection bits. Returns the translated address, or MMU_VMA_ERROR
  1152  * on translation failure.
  1153  */
  1154 sh4addr_t FASTCALL mmu_vma_to_phys_disasm( sh4vma_t vma )
  1156     if( vma & 0x80000000 ) {
  1157         if( vma < 0xC0000000 ) {
  1158             /* P1, P2 and P4 regions are pass-through (no translation) */
  1159             return VMA_TO_EXT_ADDR(vma);
  1160         } else if( vma >= 0xE0000000 && vma < 0xFFFFFF00 ) {
  1161             /* Not translatable */
  1162             return MMU_VMA_ERROR;
  1166     uint32_t mmucr = MMIO_READ(MMU,MMUCR);
  1167     if( (mmucr & MMUCR_AT) == 0 ) {
  1168         return VMA_TO_EXT_ADDR(vma);
  1171     int entryNo = mmu_itlb_lookup_vpn( vma );
  1172     if( entryNo == -2 ) {
  1173         entryNo = mmu_itlb_lookup_vpn_asid( vma );
  1175     if( entryNo < 0 ) {
  1176         return MMU_VMA_ERROR;
  1177     } else {
  1178         return (mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask) |
  1179         (vma & (~mmu_itlb[entryNo].mask));
  1183 /********************** TLB Direct-Access Regions ***************************/
  1184 #ifdef HAVE_FRAME_ADDRESS
  1185 #define EXCEPTION_EXIT() do{ *(((void **)__builtin_frame_address(0))+1) = exc; return; } while(0)
  1186 #else
  1187 #define EXCEPTION_EXIT() sh4_core_exit(CORE_EXIT_EXCEPTION)
  1188 #endif
  1191 #define ITLB_ENTRY(addr) ((addr>>7)&0x03)
  1193 int32_t FASTCALL mmu_itlb_addr_read( sh4addr_t addr )
  1195     struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
  1196     return ent->vpn | ent->asid | (ent->flags & TLB_VALID);
  1199 void FASTCALL mmu_itlb_addr_write( sh4addr_t addr, uint32_t val )
  1201     struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
  1202     ent->vpn = val & 0xFFFFFC00;
  1203     ent->asid = val & 0x000000FF;
  1204     ent->flags = (ent->flags & ~(TLB_VALID)) | (val&TLB_VALID);
  1207 int32_t FASTCALL mmu_itlb_data_read( sh4addr_t addr )
  1209     struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
  1210     return (ent->ppn & 0x1FFFFC00) | ent->flags;
  1213 void FASTCALL mmu_itlb_data_write( sh4addr_t addr, uint32_t val )
  1215     struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
  1216     ent->ppn = val & 0x1FFFFC00;
  1217     ent->flags = val & 0x00001DA;
  1218     ent->mask = get_tlb_size_mask(val);
  1219     if( ent->ppn >= 0x1C000000 )
  1220         ent->ppn |= 0xE0000000;
  1223 #define UTLB_ENTRY(addr) ((addr>>8)&0x3F)
  1224 #define UTLB_ASSOC(addr) (addr&0x80)
  1225 #define UTLB_DATA2(addr) (addr&0x00800000)
  1227 int32_t FASTCALL mmu_utlb_addr_read( sh4addr_t addr )
  1229     struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
  1230     return ent->vpn | ent->asid | (ent->flags & TLB_VALID) |
  1231     ((ent->flags & TLB_DIRTY)<<7);
  1233 int32_t FASTCALL mmu_utlb_data_read( sh4addr_t addr )
  1235     struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
  1236     if( UTLB_DATA2(addr) ) {
  1237         return ent->pcmcia;
  1238     } else {
  1239         return (ent->ppn&0x1FFFFC00) | ent->flags;
  1243 /**
  1244  * Find a UTLB entry for the associative TLB write - same as the normal
  1245  * lookup but ignores the valid bit.
  1246  */
  1247 static inline int mmu_utlb_lookup_assoc( uint32_t vpn, uint32_t asid )
  1249     int result = -1;
  1250     unsigned int i;
  1251     for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
  1252         if( (mmu_utlb[i].flags & TLB_VALID) &&
  1253                 ((mmu_utlb[i].flags & TLB_SHARE) || asid == mmu_utlb[i].asid) &&
  1254                 ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
  1255             if( result != -1 ) {
  1256                 fprintf( stderr, "TLB Multi hit: %d %d\n", result, i );
  1257                 return -2;
  1259             result = i;
  1262     return result;
  1265 /**
  1266  * Find a ITLB entry for the associative TLB write - same as the normal
  1267  * lookup but ignores the valid bit.
  1268  */
  1269 static inline int mmu_itlb_lookup_assoc( uint32_t vpn, uint32_t asid )
  1271     int result = -1;
  1272     unsigned int i;
  1273     for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
  1274         if( (mmu_itlb[i].flags & TLB_VALID) &&
  1275                 ((mmu_itlb[i].flags & TLB_SHARE) || asid == mmu_itlb[i].asid) &&
  1276                 ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
  1277             if( result != -1 ) {
  1278                 return -2;
  1280             result = i;
  1283     return result;
  1286 void FASTCALL mmu_utlb_addr_write( sh4addr_t addr, uint32_t val, void *exc )
  1288     if( UTLB_ASSOC(addr) ) {
  1289         int utlb = mmu_utlb_lookup_assoc( val, mmu_asid );
  1290         if( utlb >= 0 ) {
  1291             struct utlb_entry *ent = &mmu_utlb[utlb];
  1292             uint32_t old_flags = ent->flags;
  1293             ent->flags = ent->flags & ~(TLB_DIRTY|TLB_VALID);
  1294             ent->flags |= (val & TLB_VALID);
  1295             ent->flags |= ((val & 0x200)>>7);
  1296             if( ((old_flags^ent->flags) & (TLB_VALID|TLB_DIRTY)) != 0 ) {
  1297                 if( old_flags & TLB_VALID )
  1298                     mmu_utlb_remove_entry( utlb );
  1299                 if( ent->flags & TLB_VALID )
  1300                     mmu_utlb_insert_entry( utlb );
  1304         int itlb = mmu_itlb_lookup_assoc( val, mmu_asid );
  1305         if( itlb >= 0 ) {
  1306             struct itlb_entry *ent = &mmu_itlb[itlb];
  1307             ent->flags = (ent->flags & (~TLB_VALID)) | (val & TLB_VALID);
  1310         if( itlb == -2 || utlb == -2 ) {
  1311             RAISE_TLB_MULTIHIT_ERROR(addr);
  1312             EXCEPTION_EXIT();
  1313             return;
  1315     } else {
  1316         struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
  1317         if( ent->flags & TLB_VALID ) 
  1318             mmu_utlb_remove_entry( UTLB_ENTRY(addr) );
  1319         ent->vpn = (val & 0xFFFFFC00);
  1320         ent->asid = (val & 0xFF);
  1321         ent->flags = (ent->flags & ~(TLB_DIRTY|TLB_VALID));
  1322         ent->flags |= (val & TLB_VALID);
  1323         ent->flags |= ((val & 0x200)>>7);
  1324         if( ent->flags & TLB_VALID ) 
  1325             mmu_utlb_insert_entry( UTLB_ENTRY(addr) );
  1329 void FASTCALL mmu_utlb_data_write( sh4addr_t addr, uint32_t val )
  1331     struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
  1332     if( UTLB_DATA2(addr) ) {
  1333         ent->pcmcia = val & 0x0000000F;
  1334     } else {
  1335         if( ent->flags & TLB_VALID ) 
  1336             mmu_utlb_remove_entry( UTLB_ENTRY(addr) );
  1337         ent->ppn = (val & 0x1FFFFC00);
  1338         ent->flags = (val & 0x000001FF);
  1339         ent->mask = get_tlb_size_mask(val);
  1340         if( ent->flags & TLB_VALID ) 
  1341             mmu_utlb_insert_entry( UTLB_ENTRY(addr) );
  1345 struct mem_region_fn p4_region_itlb_addr = {
  1346         mmu_itlb_addr_read, mmu_itlb_addr_write,
  1347         mmu_itlb_addr_read, mmu_itlb_addr_write,
  1348         mmu_itlb_addr_read, mmu_itlb_addr_write,
  1349         unmapped_read_burst, unmapped_write_burst,
  1350         unmapped_prefetch };
  1351 struct mem_region_fn p4_region_itlb_data = {
  1352         mmu_itlb_data_read, mmu_itlb_data_write,
  1353         mmu_itlb_data_read, mmu_itlb_data_write,
  1354         mmu_itlb_data_read, mmu_itlb_data_write,
  1355         unmapped_read_burst, unmapped_write_burst,
  1356         unmapped_prefetch };
  1357 struct mem_region_fn p4_region_utlb_addr = {
  1358         mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
  1359         mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
  1360         mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
  1361         unmapped_read_burst, unmapped_write_burst,
  1362         unmapped_prefetch };
  1363 struct mem_region_fn p4_region_utlb_data = {
  1364         mmu_utlb_data_read, mmu_utlb_data_write,
  1365         mmu_utlb_data_read, mmu_utlb_data_write,
  1366         mmu_utlb_data_read, mmu_utlb_data_write,
  1367         unmapped_read_burst, unmapped_write_burst,
  1368         unmapped_prefetch };
  1370 /********************** Error regions **************************/
  1372 static void FASTCALL address_error_read( sh4addr_t addr, void *exc ) 
  1374     RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
  1375     EXCEPTION_EXIT();
  1378 static void FASTCALL address_error_read_burst( unsigned char *dest, sh4addr_t addr, void *exc ) 
  1380     RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
  1381     EXCEPTION_EXIT();
  1384 static void FASTCALL address_error_write( sh4addr_t addr, uint32_t val, void *exc )
  1386     RAISE_MEM_ERROR(EXC_DATA_ADDR_WRITE, addr);
  1387     EXCEPTION_EXIT();
  1390 static void FASTCALL tlb_miss_read( sh4addr_t addr, void *exc )
  1392     RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
  1393     EXCEPTION_EXIT();
  1396 static void FASTCALL tlb_miss_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
  1398     RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
  1399     EXCEPTION_EXIT();
  1402 static void FASTCALL tlb_miss_write( sh4addr_t addr, uint32_t val, void *exc )
  1404     RAISE_TLB_ERROR(EXC_TLB_MISS_WRITE, addr);
  1405     EXCEPTION_EXIT();
  1408 static int32_t FASTCALL tlb_protected_read( sh4addr_t addr, void *exc )
  1410     RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
  1411     EXCEPTION_EXIT();
  1414 static int32_t FASTCALL tlb_protected_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
  1416     RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
  1417     EXCEPTION_EXIT();
  1420 static void FASTCALL tlb_protected_write( sh4addr_t addr, uint32_t val, void *exc )
  1422     RAISE_MEM_ERROR(EXC_TLB_PROT_WRITE, addr);
  1423     EXCEPTION_EXIT();
  1426 static void FASTCALL tlb_initial_write( sh4addr_t addr, uint32_t val, void *exc )
  1428     RAISE_MEM_ERROR(EXC_INIT_PAGE_WRITE, addr);
  1429     EXCEPTION_EXIT();
  1432 static int32_t FASTCALL tlb_multi_hit_read( sh4addr_t addr, void *exc )
  1434     sh4_raise_tlb_multihit(addr);
  1435     EXCEPTION_EXIT();
  1438 static int32_t FASTCALL tlb_multi_hit_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
  1440     sh4_raise_tlb_multihit(addr);
  1441     EXCEPTION_EXIT();
  1443 static void FASTCALL tlb_multi_hit_write( sh4addr_t addr, uint32_t val, void *exc )
  1445     sh4_raise_tlb_multihit(addr);
  1446     EXCEPTION_EXIT();
  1449 /**
  1450  * Note: Per sec 4.6.4 of the SH7750 manual, SQ 
  1451  */
  1452 struct mem_region_fn mem_region_address_error = {
  1453         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1454         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1455         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1456         (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
  1457         unmapped_prefetch };
  1459 struct mem_region_fn mem_region_tlb_miss = {
  1460         (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
  1461         (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
  1462         (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
  1463         (mem_read_burst_fn_t)tlb_miss_read_burst, (mem_write_burst_fn_t)tlb_miss_write,
  1464         unmapped_prefetch };
  1466 struct mem_region_fn mem_region_tlb_protected = {
  1467         (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
  1468         (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
  1469         (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
  1470         (mem_read_burst_fn_t)tlb_protected_read_burst, (mem_write_burst_fn_t)tlb_protected_write,
  1471         unmapped_prefetch };
  1473 struct mem_region_fn mem_region_tlb_multihit = {
  1474         (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
  1475         (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
  1476         (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
  1477         (mem_read_burst_fn_t)tlb_multi_hit_read_burst, (mem_write_burst_fn_t)tlb_multi_hit_write,
  1478         (mem_prefetch_fn_t)tlb_multi_hit_read };
  1481 /* Store-queue regions */
  1482 /* These are a bit of a pain - the first 8 fields are controlled by SQMD, while 
  1483  * the final (prefetch) is controlled by the actual TLB settings (plus SQMD in
  1484  * some cases), in contrast to the ordinary fields above.
  1486  * There is probably a simpler way to do this.
  1487  */
  1489 struct mem_region_fn p4_region_storequeue = { 
  1490         ccn_storequeue_read_long, ccn_storequeue_write_long,
  1491         unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
  1492         unmapped_read_long, unmapped_write_long,
  1493         unmapped_read_burst, unmapped_write_burst,
  1494         ccn_storequeue_prefetch }; 
  1496 struct mem_region_fn p4_region_storequeue_miss = { 
  1497         ccn_storequeue_read_long, ccn_storequeue_write_long,
  1498         unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
  1499         unmapped_read_long, unmapped_write_long,
  1500         unmapped_read_burst, unmapped_write_burst,
  1501         (mem_prefetch_fn_t)tlb_miss_read }; 
  1503 struct mem_region_fn p4_region_storequeue_multihit = { 
  1504         ccn_storequeue_read_long, ccn_storequeue_write_long,
  1505         unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
  1506         unmapped_read_long, unmapped_write_long,
  1507         unmapped_read_burst, unmapped_write_burst,
  1508         (mem_prefetch_fn_t)tlb_multi_hit_read }; 
  1510 struct mem_region_fn p4_region_storequeue_protected = {
  1511         ccn_storequeue_read_long, ccn_storequeue_write_long,
  1512         unmapped_read_long, unmapped_write_long,
  1513         unmapped_read_long, unmapped_write_long,
  1514         unmapped_read_burst, unmapped_write_burst,
  1515         (mem_prefetch_fn_t)tlb_protected_read };
  1517 struct mem_region_fn p4_region_storequeue_sqmd = {
  1518         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1519         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1520         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1521         (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
  1522         (mem_prefetch_fn_t)address_error_read };        
  1524 struct mem_region_fn p4_region_storequeue_sqmd_miss = { 
  1525         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1526         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1527         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1528         (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
  1529         (mem_prefetch_fn_t)tlb_miss_read }; 
  1531 struct mem_region_fn p4_region_storequeue_sqmd_multihit = {
  1532         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1533         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1534         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1535         (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
  1536         (mem_prefetch_fn_t)tlb_multi_hit_read };        
  1538 struct mem_region_fn p4_region_storequeue_sqmd_protected = {
  1539         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1540         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1541         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1542         (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
  1543         (mem_prefetch_fn_t)tlb_protected_read };
.