Search
lxdream.org :: lxdream/src/aica/aica.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/aica/aica.c
changeset 37:1d84f4c18816
prev35:21a4be098304
next43:0cf3e339cc59
author nkeynes
date Mon Dec 26 06:38:51 2005 +0000 (15 years ago)
permissions -rw-r--r--
last change More ARM work-in-progress - idle loop works now :)
view annotate diff log raw
     1 /**
     2  * $Id: aica.c,v 1.7 2005-12-26 06:38:51 nkeynes Exp $
     3  * 
     4  * This is the core sound system (ie the bit which does the actual work)
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    19 #define MODULE aica_module
    21 #include "dream.h"
    22 #include "mem.h"
    23 #include "aica.h"
    24 #define MMIO_IMPL
    25 #include "aica.h"
    27 MMIO_REGION_READ_DEFFN( AICA0 )
    28 MMIO_REGION_READ_DEFFN( AICA1 )
    29 MMIO_REGION_READ_DEFFN( AICA2 )
    31 void aica_init( void );
    32 void aica_reset( void );
    33 void aica_start( void );
    34 void aica_stop( void );
    35 void aica_save_state( FILE *f );
    36 int aica_load_state( FILE *f );
    37 uint32_t aica_run_slice( uint32_t );
    40 struct dreamcast_module aica_module = { "AICA", aica_init, aica_reset, 
    41 					aica_start, aica_run_slice, aica_stop,
    42 					aica_save_state, aica_load_state };
    44 /**
    45  * Initialize the AICA subsystem. Note requires that 
    46  */
    47 void aica_init( void )
    48 {
    49     register_io_regions( mmio_list_spu );
    50     MMIO_NOTRACE(AICA0);
    51     MMIO_NOTRACE(AICA1);
    52     arm_mem_init();
    53     arm_reset();
    54 }
    56 void aica_reset( void )
    57 {
    58     arm_reset();
    59 }
    61 void aica_start( void )
    62 {
    64 }
    66 uint32_t aica_run_slice( uint32_t nanosecs )
    67 {
    68     /* Run arm instructions */
    69     int reset = MMIO_READ( AICA2, AICA_RESET );
    70     if( reset & 1 == 0 ) { 
    71 	/* Running */
    72 	/* nanosecs = arm_run_slice( nanosecs ); */
    73     }
    74     /* Generate audio buffer */
    75 }
    77 void aica_stop( void )
    78 {
    80 }
    82 void aica_save_state( FILE *f )
    83 {
    84     arm_save_state( f );
    85 }
    87 int aica_load_state( FILE *f )
    88 {
    89     return arm_load_state( f );
    90 }
    92 /** Channel register structure:
    93  * 00
    94  * 04
    95  * 08  4  Loop start address
    96  * 0C  4  Loop end address
    97  * 10  4  Volume envelope
    98  * 14
    99  * 18  4  Frequency (floating point 
   100  * 1C
   101  * 20
   102  * 24  1  Pan
   103  * 25  1  ??
   104  * 26  
   105  * 27  
   106  * 28  1  ??
   107  * 29  1  Volume
   108  * 2C
   109  * 30
   110  * 
   112 /* Write to channels 0-31 */
   113 void mmio_region_AICA0_write( uint32_t reg, uint32_t val )
   114 {
   115     //    aica_write_channel( reg >> 7, reg % 128, val );
   116     MMIO_WRITE( AICA0, reg, val );
   117     //    DEBUG( "AICA0 Write %08X => %08X", val, reg );
   118 }
   120 /* Write to channels 32-64 */
   121 void mmio_region_AICA1_write( uint32_t reg, uint32_t val )
   122 {
   123     //    aica_write_channel( (reg >> 7) + 32, reg % 128, val );
   124     MMIO_WRITE( AICA1, reg, val );
   125     // DEBUG( "AICA1 Write %08X => %08X", val, reg );
   126 }
   128 /* General registers */
   129 void mmio_region_AICA2_write( uint32_t reg, uint32_t val )
   130 {
   131     uint32_t tmp;
   132     switch( reg ) {
   133     case AICA_RESET:
   134 	tmp = MMIO_READ( AICA2, AICA_RESET );
   135 	if( (tmp & 1) == 1 && (val & 1) == 0 ) {
   136 	    /* ARM enabled - execute a core reset */
   137 	    DEBUG( "ARM enabled" );
   138 	    arm_reset();
   139 	} else if( (tmp&1) == 0 && (val&1) == 1 ) {
   140 	    DEBUG( "ARM disabled" );
   141 	}
   142 	MMIO_WRITE( AICA2, AICA_RESET, val );
   143 	break;
   144     default:
   145 	MMIO_WRITE( AICA2, reg, val );
   146 	break;
   147     }
   148 }
.