lxdream.org :: lxdream/src/aica/armcore.c r431:248dd77a9e44

tree revision 490:1e0f9940e064

filename	src/aica/armcore.c
changeset	431:248dd77a9e44
prev	86:f151e63f9754
next	536:d3a65d75b5ae
author	nkeynes
date	Sun Nov 04 08:49:18 2007 +0000 (16 years ago)
permissions	-rw-r--r--
last change	Fix pointer=>int conversions to use intptr_t types

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     1 /**

     2  * $Id: armcore.c,v 1.21 2007-10-09 08:11:51 nkeynes Exp $

     3  *

     4  * ARM7TDMI CPU emulation core.

     5  *

     6  * Copyright (c) 2005 Nathan Keynes.

     7  *

     8  * This program is free software; you can redistribute it and/or modify

     9  * it under the terms of the GNU General Public License as published by

    10  * the Free Software Foundation; either version 2 of the License, or

    11  * (at your option) any later version.

    12  *

    13  * This program is distributed in the hope that it will be useful,

    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    16  * GNU General Public License for more details.

    17  */

    19 #define MODULE aica_module

    20 #include "dream.h"

    21 #include "dreamcast.h"

    22 #include "mem.h"

    23 #include "aica/armcore.h"

    24 #include "aica/aica.h"

    26 #define STM_R15_OFFSET 12

    28 struct arm_registers armr;

    30 void arm_set_mode( int mode );

    32 uint32_t arm_exceptions[][2] = {{ MODE_SVC, 0x00000000 },

    33 				{ MODE_UND, 0x00000004 },

    34 				{ MODE_SVC, 0x00000008 },

    35 				{ MODE_ABT, 0x0000000C },

    36 				{ MODE_ABT, 0x00000010 },

    37 				{ MODE_IRQ, 0x00000018 },

    38 				{ MODE_FIQ, 0x0000001C } };

    40 #define EXC_RESET 0

    41 #define EXC_UNDEFINED 1

    42 #define EXC_SOFTWARE 2

    43 #define EXC_PREFETCH_ABORT 3

    44 #define EXC_DATA_ABORT 4

    45 #define EXC_IRQ 5

    46 #define EXC_FAST_IRQ 6

    48 uint32_t arm_cpu_freq = ARM_BASE_RATE;

    49 uint32_t arm_cpu_period = 1000 / ARM_BASE_RATE;

    51 #define CYCLES_PER_SAMPLE ((ARM_BASE_RATE * 1000000) / AICA_SAMPLE_RATE)

    53 static struct breakpoint_struct arm_breakpoints[MAX_BREAKPOINTS];

    54 static int arm_breakpoint_count = 0;

    56 void arm_set_breakpoint( uint32_t pc, int type )

    57 {

    58     arm_breakpoints[arm_breakpoint_count].address = pc;

    59     arm_breakpoints[arm_breakpoint_count].type = type;

    60     arm_breakpoint_count++;

    61 }

    63 gboolean arm_clear_breakpoint( uint32_t pc, int type )

    64 {

    65     int i;

    67     for( i=0; i<arm_breakpoint_count; i++ ) {

    68 	if( arm_breakpoints[i].address == pc &&

    69 	    arm_breakpoints[i].type == type ) {

    70 	    while( ++i < arm_breakpoint_count ) {

    71 		arm_breakpoints[i-1].address = arm_breakpoints[i].address;

    72 		arm_breakpoints[i-1].type = arm_breakpoints[i].type;

    73 	    }

    74 	    arm_breakpoint_count--;

    75 	    return TRUE;

    76 	}

    77     }

    78     return FALSE;

    79 }

    81 int arm_get_breakpoint( uint32_t pc )

    82 {

    83     int i;

    84     for( i=0; i<arm_breakpoint_count; i++ ) {

    85 	if( arm_breakpoints[i].address == pc )

    86 	    return arm_breakpoints[i].type;

    87     }

    88     return 0;

    89 }

    91 uint32_t arm_run_slice( uint32_t num_samples )

    92 {

    93     int i,j,k;

    95     if( !armr.running )

    96 	return num_samples;

    98     for( i=0; i<num_samples; i++ ) {

    99 	for( j=0; j < CYCLES_PER_SAMPLE; j++ ) {

   100 	    armr.icount++;

   101 	    if( !arm_execute_instruction() )

   102 		return i;

   103 #ifdef ENABLE_DEBUG_MODE

   104 	    for( k=0; k<arm_breakpoint_count; k++ ) {

   105 		if( arm_breakpoints[k].address == armr.r[15] ) {

   106 		    dreamcast_stop();

   107 		    if( arm_breakpoints[k].type == BREAK_ONESHOT )

   108 			arm_clear_breakpoint( armr.r[15], BREAK_ONESHOT );

   109 		    return i;

   110 		}

   111 	    }

   112 #endif

   113 	}

   115 	k = MMIO_READ( AICA2, AICA_TCR );

   116 	if( k & 0x40 ) {

   117 	    uint8_t val = MMIO_READ( AICA2, AICA_TIMER );

   118 	    val++;

   119 	    if( val == 0 ) {

   120 		aica_event( AICA_EVENT_TIMER );

   121 		MMIO_WRITE( AICA2, AICA_TCR, k & ~0x40 );

   122 	    }

   123 	    MMIO_WRITE( AICA2, AICA_TIMER, val );

   124 	}

   125 	if( !dreamcast_is_running() )

   126 	    break;

   127     }

   129     return i;

   130 }

   132 void arm_save_state( FILE *f )

   133 {

   134     fwrite( &armr, sizeof(armr), 1, f );

   135 }

   137 int arm_load_state( FILE *f )

   138 {

   139     fread( &armr, sizeof(armr), 1, f );

   140     return 0;

   141 }

   143 /* Exceptions */

   144 void arm_reset( void )

   145 {

   146     /* Wipe all processor state */

   147     memset( &armr, 0, sizeof(armr) );

   149     armr.cpsr = MODE_SVC | CPSR_I | CPSR_F;

   150     armr.r[15] = 0x00000000;

   151     armr.running = TRUE;

   152 }

   154 #define SET_CPSR_CONTROL   0x00010000

   155 #define SET_CPSR_EXTENSION 0x00020000

   156 #define SET_CPSR_STATUS    0x00040000

   157 #define SET_CPSR_FLAGS     0x00080000

   159 uint32_t arm_get_cpsr( void )

   160 {

   161     /* write back all flags to the cpsr */

   162     armr.cpsr = armr.cpsr & CPSR_COMPACT_MASK;

   163     if( armr.n ) armr.cpsr |= CPSR_N;

   164     if( armr.z ) armr.cpsr |= CPSR_Z;

   165     if( armr.c ) armr.cpsr |= CPSR_C;

   166     if( armr.v ) armr.cpsr |= CPSR_V;

   167     if( armr.t ) armr.cpsr |= CPSR_T;

   168     return armr.cpsr;

   169 }

   171 /**

   172  * Return a pointer to the specified register in the user bank,

   173  * regardless of the active bank

   174  */

   175 static uint32_t *arm_user_reg( int reg )

   176 {

   177     if( IS_EXCEPTION_MODE() ) {

   178 	if( reg == 13 || reg == 14 )

   179 	    return &armr.user_r[reg-8];

   180 	if( IS_FIQ_MODE() ) {

   181 	    if( reg >= 8 || reg <= 12 )

   182 		return &armr.user_r[reg-8];

   183 	}

   184     }

   185     return &armr.r[reg];

   186 }

   188 #define USER_R(n) *arm_user_reg(n)

   190 /**

   191  * Set the CPSR to the specified value.

   192  *

   193  * @param value values to set in CPSR

   194  * @param fields set of mask values to define which sections of the

   195  *   CPSR to set (one of the SET_CPSR_* values above)

   196  */

   197 void arm_set_cpsr( uint32_t value, uint32_t fields )

   198 {

   199     if( IS_PRIVILEGED_MODE() ) {

   200 	if( fields & SET_CPSR_CONTROL ) {

   201 	    int mode = value & CPSR_MODE;

   202 	    arm_set_mode( mode );

   203 	    armr.t = ( value & CPSR_T ); /* Technically illegal to change */

   204 	    armr.cpsr = (armr.cpsr & 0xFFFFFF00) | (value & 0x000000FF);

   205 	}

   207 	/* Middle 16 bits not currently defined */

   208     }

   209     if( fields & SET_CPSR_FLAGS ) {

   210 	/* Break flags directly out of given value - don't bother writing

   211 	 * back to CPSR

   212 	 */

   213 	armr.n = ( value & CPSR_N );

   214 	armr.z = ( value & CPSR_Z );

   215 	armr.c = ( value & CPSR_C );

   216 	armr.v = ( value & CPSR_V );

   217     }

   218 }

   220 void arm_set_spsr( uint32_t value, uint32_t fields )

   221 {

   222     /* Only defined if we actually have an SPSR register */

   223     if( IS_EXCEPTION_MODE() ) {

   224 	if( fields & SET_CPSR_CONTROL ) {

   225 	    armr.spsr = (armr.spsr & 0xFFFFFF00) | (value & 0x000000FF);

   226 	}

   228 	/* Middle 16 bits not currently defined */

   230 	if( fields & SET_CPSR_FLAGS ) {

   231 	    armr.spsr = (armr.spsr & 0x00FFFFFF) | (value & 0xFF000000);

   232 	}

   233     }

   234 }

   236 /**

   237  * Raise an ARM exception (other than reset, which uses arm_reset().

   238  * @param exception one of the EXC_* exception codes defined above.

   239  */

   240 void arm_raise_exception( int exception )

   241 {

   242     int mode = arm_exceptions[exception][0];

   243     uint32_t spsr = arm_get_cpsr();

   244     arm_set_mode( mode );

   245     armr.spsr = spsr;

   246     armr.r[14] = armr.r[15] + 4;

   247     armr.cpsr = (spsr & 0xFFFFFF00) | mode | CPSR_I;

   248     if( mode == MODE_FIQ )

   249 	armr.cpsr |= CPSR_F;

   250     armr.r[15] = arm_exceptions[exception][1];

   251 }

   253 void arm_restore_cpsr( void )

   254 {

   255     int spsr = armr.spsr;

   256     int mode = spsr & CPSR_MODE;

   257     arm_set_mode( mode );

   258     armr.cpsr = spsr;

   259     armr.n = ( spsr & CPSR_N );

   260     armr.z = ( spsr & CPSR_Z );

   261     armr.c = ( spsr & CPSR_C );

   262     armr.v = ( spsr & CPSR_V );

   263     armr.t = ( spsr & CPSR_T );

   264 }

   268 /**

   269  * Change the current executing ARM mode to the requested mode.

   270  * Saves any required registers to banks and restores those for the

   271  * correct mode. (Note does not actually update CPSR at the moment).

   272  */

   273 void arm_set_mode( int targetMode )

   274 {

   275     int currentMode = armr.cpsr & CPSR_MODE;

   276     if( currentMode == targetMode )

   277 	return;

   279     switch( currentMode ) {

   280     case MODE_USER:

   281     case MODE_SYS:

   282 	armr.user_r[5] = armr.r[13];

   283 	armr.user_r[6] = armr.r[14];

   284 	break;

   285     case MODE_SVC:

   286 	armr.svc_r[0] = armr.r[13];

   287 	armr.svc_r[1] = armr.r[14];

   288 	armr.svc_r[2] = armr.spsr;

   289 	break;

   290     case MODE_ABT:

   291 	armr.abt_r[0] = armr.r[13];

   292 	armr.abt_r[1] = armr.r[14];

   293 	armr.abt_r[2] = armr.spsr;

   294 	break;

   295     case MODE_UND:

   296 	armr.und_r[0] = armr.r[13];

   297 	armr.und_r[1] = armr.r[14];

   298 	armr.und_r[2] = armr.spsr;

   299 	break;

   300     case MODE_IRQ:

   301 	armr.irq_r[0] = armr.r[13];

   302 	armr.irq_r[1] = armr.r[14];

   303 	armr.irq_r[2] = armr.spsr;

   304 	break;

   305     case MODE_FIQ:

   306 	armr.fiq_r[0] = armr.r[8];

   307 	armr.fiq_r[1] = armr.r[9];

   308 	armr.fiq_r[2] = armr.r[10];

   309 	armr.fiq_r[3] = armr.r[11];

   310 	armr.fiq_r[4] = armr.r[12];

   311 	armr.fiq_r[5] = armr.r[13];

   312 	armr.fiq_r[6] = armr.r[14];

   313 	armr.fiq_r[7] = armr.spsr;

   314 	armr.r[8] = armr.user_r[0];

   315 	armr.r[9] = armr.user_r[1];

   316 	armr.r[10] = armr.user_r[2];

   317 	armr.r[11] = armr.user_r[3];

   318 	armr.r[12] = armr.user_r[4];

   319 	break;

   320     }

   322     switch( targetMode ) {

   323     case MODE_USER:

   324     case MODE_SYS:

   325 	armr.r[13] = armr.user_r[5];

   326 	armr.r[14] = armr.user_r[6];

   327 	break;

   328     case MODE_SVC:

   329 	armr.r[13] = armr.svc_r[0];

   330 	armr.r[14] = armr.svc_r[1];

   331 	armr.spsr = armr.svc_r[2];

   332 	break;

   333     case MODE_ABT:

   334 	armr.r[13] = armr.abt_r[0];

   335 	armr.r[14] = armr.abt_r[1];

   336 	armr.spsr = armr.abt_r[2];

   337 	break;

   338     case MODE_UND:

   339 	armr.r[13] = armr.und_r[0];

   340 	armr.r[14] = armr.und_r[1];

   341 	armr.spsr = armr.und_r[2];

   342 	break;

   343     case MODE_IRQ:

   344 	armr.r[13] = armr.irq_r[0];

   345 	armr.r[14] = armr.irq_r[1];

   346 	armr.spsr = armr.irq_r[2];

   347 	break;

   348     case MODE_FIQ:

   349 	armr.user_r[0] = armr.r[8];

   350 	armr.user_r[1] = armr.r[9];

   351 	armr.user_r[2] = armr.r[10];

   352 	armr.user_r[3] = armr.r[11];

   353 	armr.user_r[4] = armr.r[12];

   354 	armr.r[8] = armr.fiq_r[0];

   355 	armr.r[9] = armr.fiq_r[1];

   356 	armr.r[10] = armr.fiq_r[2];

   357 	armr.r[11] = armr.fiq_r[3];

   358 	armr.r[12] = armr.fiq_r[4];

   359 	armr.r[13] = armr.fiq_r[5];

   360 	armr.r[14] = armr.fiq_r[6];

   361 	armr.spsr = armr.fiq_r[7];

   362 	break;

   363     }

   364 }

   366 /* Page references are as per ARM DDI 0100E (June 2000) */

   368 #define MEM_READ_BYTE( addr ) arm_read_byte(addr)

   369 #define MEM_READ_WORD( addr ) arm_read_word(addr)

   370 #define MEM_READ_LONG( addr ) arm_read_long(addr)

   371 #define MEM_WRITE_BYTE( addr, val ) arm_write_byte(addr, val)

   372 #define MEM_WRITE_WORD( addr, val ) arm_write_word(addr, val)

   373 #define MEM_WRITE_LONG( addr, val ) arm_write_long(addr, val)

   376 #define IS_NOTBORROW( result, op1, op2 ) (op2 > op1 ? 0 : 1)

   377 #define IS_CARRY( result, op1, op2 ) (result < op1 ? 1 : 0)

   378 #define IS_SUBOVERFLOW( result, op1, op2 ) (((op1^op2) & (result^op1)) >> 31)

   379 #define IS_ADDOVERFLOW( result, op1, op2 ) (((op1&op2) & (result^op1)) >> 31)

   381 #define PC armr.r[15]

   383 /* Instruction fields */

   384 #define COND(ir) (ir>>28)

   385 #define GRP(ir) ((ir>>26)&0x03)

   386 #define OPCODE(ir) ((ir>>20)&0x1F)

   387 #define IFLAG(ir) (ir&0x02000000)

   388 #define SFLAG(ir) (ir&0x00100000)

   389 #define PFLAG(ir) (ir&0x01000000)

   390 #define UFLAG(ir) (ir&0x00800000)

   391 #define BFLAG(ir) (ir&0x00400000)

   392 #define WFLAG(ir) (ir&0x00200000)

   393 #define LFLAG(ir) SFLAG(ir)

   394 #define RN(ir) (armr.r[((ir>>16)&0x0F)] + (((ir>>16)&0x0F) == 0x0F ? 4 : 0))

   395 #define RD(ir) (armr.r[((ir>>12)&0x0F)] + (((ir>>12)&0x0F) == 0x0F ? 4 : 0))

   396 #define RDn(ir) ((ir>>12)&0x0F)

   397 #define RS(ir) (armr.r[((ir>>8)&0x0F)] + (((ir>>8)&0x0F) == 0x0F ? 4 : 0))

   398 #define RM(ir) (armr.r[(ir&0x0F)] + (((ir&0x0F) == 0x0F ? 4 : 0)) )

   399 #define LRN(ir) armr.r[((ir>>16)&0x0F)]

   400 #define LRD(ir) armr.r[((ir>>12)&0x0F)]

   401 #define LRS(ir) armr.r[((ir>>8)&0x0F)]

   402 #define LRM(ir) armr.r[(ir&0x0F)]

   404 #define IMM8(ir) (ir&0xFF)

   405 #define IMM12(ir) (ir&0xFFF)

   406 #define SHIFTIMM(ir) ((ir>>7)&0x1F)

   407 #define IMMROT(ir) ((ir>>7)&0x1E)

   408 #define ROTIMM12(ir) ROTATE_RIGHT_LONG(IMM8(ir),IMMROT(ir))

   409 #define SIGNEXT24(n) (((n)&0x00800000) ? ((n)|0xFF000000) : ((n)&0x00FFFFFF))

   410 #define SHIFT(ir) ((ir>>4)&0x07)

   411 #define DISP24(ir) ((ir&0x00FFFFFF))

   412 #define UNDEF(ir) do{ arm_raise_exception( EXC_UNDEFINED ); return TRUE; } while(0)

   413 #define UNIMP(ir) do{ PC-=4; ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", PC, ir ); dreamcast_stop(); return FALSE; }while(0)

   415 /**

   416  * Determine the value of the shift-operand for a data processing instruction,

   417  * without determing a value for shift_C (optimized form for instructions that

   418  * don't require shift_C ).

   419  * @see s5.1 Addressing Mode 1 - Data-processing operands (p A5-2, 218)

   420  */

   421 static uint32_t arm_get_shift_operand( uint32_t ir )

   422 {

   423 	uint32_t operand, tmp;

   424 	if( IFLAG(ir) == 0 ) {

   425 		operand = RM(ir);

   426 		switch(SHIFT(ir)) {

   427 		case 0: /* (Rm << imm) */

   428 			operand = operand << SHIFTIMM(ir);

   429 			break;

   430 		case 1: /* (Rm << Rs) */

   431 			tmp = RS(ir)&0xFF;

   432 			if( tmp > 31 ) operand = 0;

   433 			else operand = operand << tmp;

   434 			break;

   435 		case 2: /* (Rm >> imm) */

   436 			operand = operand >> SHIFTIMM(ir);

   437 			break;

   438 		case 3: /* (Rm >> Rs) */

   439 			tmp = RS(ir) & 0xFF;

   440 			if( tmp > 31 ) operand = 0;

   441 			else operand = operand >> ir;

   442 			break;

   443 		case 4: /* (Rm >>> imm) */

   444 			tmp = SHIFTIMM(ir);

   445 			if( tmp == 0 ) operand = ((int32_t)operand) >> 31;

   446 			else operand = ((int32_t)operand) >> tmp;

   447 			break;

   448 		case 5: /* (Rm >>> Rs) */

   449 			tmp = RS(ir) & 0xFF;

   450 			if( tmp > 31 ) operand = ((int32_t)operand) >> 31;

   451 			else operand = ((int32_t)operand) >> tmp;

   452 			break;

   453 		case 6:

   454 			tmp = SHIFTIMM(ir);

   455 			if( tmp == 0 ) /* RRX aka rotate with carry */

   456 				operand = (operand >> 1) | (armr.c<<31);

   457 			else

   458 				operand = ROTATE_RIGHT_LONG(operand,tmp);

   459 			break;

   460 		case 7:

   461 			tmp = RS(ir)&0x1F;

   462 			operand = ROTATE_RIGHT_LONG(operand,tmp);

   463 			break;

   464 		}

   465 	} else {

   466 		operand = IMM8(ir);

   467 		tmp = IMMROT(ir);

   468 		operand = ROTATE_RIGHT_LONG(operand, tmp);

   469 	}

   470 	return operand;

   471 }

   473 /**

   474  * Determine the value of the shift-operand for a data processing instruction,

   475  * and set armr.shift_c accordingly.

   476  * @see s5.1 Addressing Mode 1 - Data-processing operands (p A5-2, 218)

   477  */

   478 static uint32_t arm_get_shift_operand_s( uint32_t ir )

   479 {

   480 	uint32_t operand, tmp;

   481 	if( IFLAG(ir) == 0 ) {

   482 		operand = RM(ir);

   483 		switch(SHIFT(ir)) {

   484 		case 0: /* (Rm << imm) */

   485 			tmp = SHIFTIMM(ir);

   486 			if( tmp == 0 ) { /* Rm */

   487 				armr.shift_c = armr.c;

   488 			} else { /* Rm << imm */

   489 				armr.shift_c = (operand >> (32-tmp)) & 0x01;

   490 				operand = operand << tmp;

   491 			}

   492 			break;

   493 		case 1: /* (Rm << Rs) */

   494 			tmp = RS(ir)&0xFF;

   495 			if( tmp == 0 ) {

   496 				armr.shift_c = armr.c;

   497 			} else {

   498 				if( tmp <= 32 )

   499 					armr.shift_c = (operand >> (32-tmp)) & 0x01;

   500 				else armr.shift_c = 0;

   501 				if( tmp < 32 )

   502 					operand = operand << tmp;

   503 				else operand = 0;

   504 			}

   505 			break;

   506 		case 2: /* (Rm >> imm) */

   507 			tmp = SHIFTIMM(ir);

   508 			if( tmp == 0 ) {

   509 				armr.shift_c = operand >> 31;

   510 				operand = 0;

   511 			} else {

   512 				armr.shift_c = (operand >> (tmp-1)) & 0x01;

   513 				operand = RM(ir) >> tmp;

   514 			}

   515 			break;

   516 		case 3: /* (Rm >> Rs) */

   517 			tmp = RS(ir) & 0xFF;

   518 			if( tmp == 0 ) {

   519 				armr.shift_c = armr.c;

   520 			} else {

   521 				if( tmp <= 32 )

   522 					armr.shift_c = (operand >> (tmp-1))&0x01;

   523 				else armr.shift_c = 0;

   524 				if( tmp < 32 )

   525 					operand = operand >> tmp;

   526 				else operand = 0;

   527 			}

   528 			break;

   529 		case 4: /* (Rm >>> imm) */

   530 			tmp = SHIFTIMM(ir);

   531 			if( tmp == 0 ) {

   532 				armr.shift_c = operand >> 31;

   533 				operand = -armr.shift_c;

   534 			} else {

   535 				armr.shift_c = (operand >> (tmp-1)) & 0x01;

   536 				operand = ((int32_t)operand) >> tmp;

   537 			}

   538 			break;

   539 		case 5: /* (Rm >>> Rs) */

   540 			tmp = RS(ir) & 0xFF;

   541 			if( tmp == 0 ) {

   542 				armr.shift_c = armr.c;

   543 			} else {

   544 				if( tmp < 32 ) {

   545 					armr.shift_c = (operand >> (tmp-1))&0x01;

   546 					operand = ((int32_t)operand) >> tmp;

   547 				} else {

   548 					armr.shift_c = operand >> 31;

   549 					operand = ((int32_t)operand) >> 31;

   550 				}

   551 			}

   552 			break;

   553 		case 6:

   554 			tmp = SHIFTIMM(ir);

   555 			if( tmp == 0 ) { /* RRX aka rotate with carry */

   556 				armr.shift_c = operand&0x01;

   557 				operand = (operand >> 1) | (armr.c<<31);

   558 			} else {

   559 				armr.shift_c = operand>>(tmp-1);

   560 				operand = ROTATE_RIGHT_LONG(operand,tmp);

   561 			}

   562 			break;

   563 		case 7:

   564 			tmp = RS(ir)&0xFF;

   565 			if( tmp == 0 ) {

   566 				armr.shift_c = armr.c;

   567 			} else {

   568 				tmp &= 0x1F;

   569 				if( tmp == 0 ) {

   570 					armr.shift_c = operand>>31;

   571 				} else {

   572 					armr.shift_c = (operand>>(tmp-1))&0x1;

   573 					operand = ROTATE_RIGHT_LONG(operand,tmp);

   574 				}

   575 			}

   576 			break;

   577 		}

   578 	} else {

   579 		operand = IMM8(ir);

   580 		tmp = IMMROT(ir);

   581 		if( tmp == 0 ) {

   582 			armr.shift_c = armr.c;

   583 		} else {

   584 			operand = ROTATE_RIGHT_LONG(operand, tmp);

   585 			armr.shift_c = operand>>31;

   586 		}

   587 	}

   588 	return operand;

   589 }

   591 /**

   592  * Another variant of the shifter code for index-based memory addressing.

   593  * Distinguished by the fact that it doesn't support register shifts, and

   594  * ignores the I flag (WTF do the load/store instructions use the I flag to

   595  * mean the _exact opposite_ of what it means for the data processing

   596  * instructions ???)

   597  */

   598 static uint32_t arm_get_address_index( uint32_t ir )

   599 {

   600 	uint32_t operand = RM(ir);

   601 	uint32_t tmp;

   603 	switch(SHIFT(ir)) {

   604 	case 0: /* (Rm << imm) */

   605 		operand = operand << SHIFTIMM(ir);

   606 		break;

   607 	case 2: /* (Rm >> imm) */

   608 		operand = operand >> SHIFTIMM(ir);

   609 		break;

   610 	case 4: /* (Rm >>> imm) */

   611 		tmp = SHIFTIMM(ir);

   612 		if( tmp == 0 ) operand = ((int32_t)operand) >> 31;

   613 		else operand = ((int32_t)operand) >> tmp;

   614 		break;

   615 	case 6:

   616 		tmp = SHIFTIMM(ir);

   617 		if( tmp == 0 ) /* RRX aka rotate with carry */

   618 			operand = (operand >> 1) | (armr.c<<31);

   619 		else

   620 			operand = ROTATE_RIGHT_LONG(operand,tmp);

   621 		break;

   622 	default: UNIMP(ir);

   623 	}

   624 	return operand;

   625 }

   627 /**

   628  * Determine the address operand of a load/store instruction, including

   629  * applying any pre/post adjustments to the address registers.

   630  * @see s5.2 Addressing Mode 2 - Load and Store Word or Unsigned Byte

   631  * @param The instruction word.

   632  * @return The calculated address

   633  */

   634 static uint32_t arm_get_address_operand( uint32_t ir )

   635 {

   636 	uint32_t addr=0;

   638 	/* I P U . W */

   639 	switch( (ir>>21)&0x1D ) {

   640 	case 0: /* Rn -= imm offset (post-indexed) [5.2.8 A5-28] */

   641 	case 1:

   642 		addr = RN(ir);

   643 		LRN(ir) = addr - IMM12(ir);

   644 		break;

   645 	case 4: /* Rn += imm offsett (post-indexed) [5.2.8 A5-28] */

   646 	case 5:

   647 		addr = RN(ir);

   648 		LRN(ir) = addr + IMM12(ir);

   649 		break;

   650 	case 8: /* Rn - imm offset  [5.2.2 A5-20] */

   651 		addr = RN(ir) - IMM12(ir);

   652 		break;

   653 	case 9: /* Rn -= imm offset (pre-indexed)  [5.2.5 A5-24] */

   654 		addr = RN(ir) - IMM12(ir);

   655 		LRN(ir) = addr;

   656 		break;

   657 	case 12: /* Rn + imm offset  [5.2.2 A5-20] */

   658 		addr = RN(ir) + IMM12(ir);

   659 		break;

   660 	case 13: /* Rn += imm offset  [5.2.5 A5-24 ] */

   661 		addr = RN(ir) + IMM12(ir);

   662 		LRN(ir) = addr;

   663 		break;

   664 	case 16: /* Rn -= Rm (post-indexed)  [5.2.10 A5-32 ] */

   665 	case 17:

   666 		addr = RN(ir);

   667 		LRN(ir) = addr - arm_get_address_index(ir);

   668 		break;

   669 	case 20: /* Rn += Rm (post-indexed)  [5.2.10 A5-32 ] */

   670 	case 21:

   671 		addr = RN(ir);

   672 		LRN(ir) = addr - arm_get_address_index(ir);

   673 		break;

   674 	case 24: /* Rn - Rm  [5.2.4 A5-23] */

   675 		addr = RN(ir) - arm_get_address_index(ir);

   676 		break;

   677 	case 25: /* RN -= Rm (pre-indexed)  [5.2.7 A5-26] */

   678 		addr = RN(ir) - arm_get_address_index(ir);

   679 		LRN(ir) = addr;

   680 		break;

   681 	case 28: /* Rn + Rm  [5.2.4 A5-23] */

   682 		addr = RN(ir) + arm_get_address_index(ir);

   683 		break;

   684 	case 29: /* RN += Rm (pre-indexed) [5.2.7 A5-26] */

   685 		addr = RN(ir) + arm_get_address_index(ir);

   686 		LRN(ir) = addr;

   687 		break;

   688 	}

   689 	return addr;

   690 }

   692 gboolean arm_execute_instruction( void )

   693 {

   694     uint32_t pc;

   695     uint32_t ir;

   696     uint32_t operand, operand2, tmp, tmp2, cond;

   697     int i;

   699     tmp = armr.int_pending & (~armr.cpsr);

   700     if( tmp ) {

   701 	if( tmp & CPSR_F ) {

   702 	    arm_raise_exception( EXC_FAST_IRQ );

   703 	} else {

   704 	    arm_raise_exception( EXC_IRQ );

   705 	}

   706     }

   708     ir = MEM_READ_LONG(PC);

   709     pc = PC + 4;

   710     PC = pc;

   712     /**

   713      * Check the condition bits first - if the condition fails return

   714      * immediately without actually looking at the rest of the instruction.

   715      */

   716     switch( COND(ir) ) {

   717     case 0: /* EQ */

   718 	cond = armr.z;

   719 	break;

   720     case 1: /* NE */

   721 	cond = !armr.z;

   722 	break;

   723     case 2: /* CS/HS */

   724 	cond = armr.c;

   725 	break;

   726     case 3: /* CC/LO */

   727 	cond = !armr.c;

   728 	break;

   729     case 4: /* MI */

   730 	cond = armr.n;

   731 	break;

   732     case 5: /* PL */

   733 	cond = !armr.n;

   734 	break;

   735     case 6: /* VS */

   736 	cond = armr.v;

   737 	break;

   738     case 7: /* VC */

   739 	cond = !armr.v;

   740 	break;

   741     case 8: /* HI */

   742 	cond = armr.c && !armr.z;

   743 	break;

   744     case 9: /* LS */

   745 	cond = (!armr.c) || armr.z;

   746 	break;

   747     case 10: /* GE */

   748 	cond = (armr.n == armr.v);

   749 	break;

   750     case 11: /* LT */

   751 	cond = (armr.n != armr.v);

   752 	break;

   753     case 12: /* GT */

   754 	cond = (!armr.z) && (armr.n == armr.v);

   755 	break;

   756     case 13: /* LE */

   757 	cond = armr.z || (armr.n != armr.v);

   758 	break;

   759     case 14: /* AL */

   760 	cond = 1;

   761 	break;

   762     case 15: /* (NV) */

   763     default:

   764 	cond = 0;

   765 	UNDEF(ir);

   766     }

   767     if( cond ) {

   769     /**

   770      * Condition passed, now for the actual instructions...

   771      */

   772     switch( GRP(ir) ) {

   773     case 0:

   774 	if( (ir & 0x0D900000) == 0x01000000 ) {

   775 	    /* Instructions that aren't actual data processing even though

   776 	     * they sit in the DP instruction block.

   777 	     */

   778 	    switch( ir & 0x0FF000F0 ) {

   779 	    case 0x01200010: /* BX Rd */

   780 		armr.t = ir & 0x01;

   781 		armr.r[15] = RM(ir) & 0xFFFFFFFE;

   782 		break;

   783 	    case 0x01000000: /* MRS Rd, CPSR */

   784 		LRD(ir) = arm_get_cpsr();

   785 		break;

   786 	    case 0x01400000: /* MRS Rd, SPSR */

   787 		LRD(ir) = armr.spsr;

   788 		break;

   789 	    case 0x01200000: /* MSR CPSR, Rd */

   790 		arm_set_cpsr( RM(ir), ir );

   791 		break;

   792 	    case 0x01600000: /* MSR SPSR, Rd */

   793 		arm_set_spsr( RM(ir), ir );

   794 		break;

   795 	    case 0x03200000: /* MSR CPSR, imm */

   796 		arm_set_cpsr( ROTIMM12(ir), ir );

   797 		break;

   798 	    case 0x03600000: /* MSR SPSR, imm */

   799 		arm_set_spsr( ROTIMM12(ir), ir );

   800 		break;

   801 	    default:

   802 		UNIMP(ir);

   803 	    }

   804 	} else if( (ir & 0x0E000090) == 0x00000090 ) {

   805 	    /* Neither are these */

   806 	    switch( (ir>>5)&0x03 ) {

   807 	    case 0:

   808 		/* Arithmetic extension area */

   809 		switch(OPCODE(ir)) {

   810 		case 0: /* MUL */

   811 		    LRN(ir) = RM(ir) * RS(ir);

   812 		    break;

   813 		case 1: /* MULS */

   814 		    tmp = RM(ir) * RS(ir);

   815 		    LRN(ir) = tmp;

   816 		    armr.n = tmp>>31;

   817 		    armr.z = (tmp == 0);

   818 		    break;

   819 		case 2: /* MLA */

   820 		    LRN(ir) = RM(ir) * RS(ir) + RD(ir);

   821 		    break;

   822 		case 3: /* MLAS */

   823 		    tmp = RM(ir) * RS(ir) + RD(ir);

   824 		    LRN(ir) = tmp;

   825 		    armr.n = tmp>>31;

   826 		    armr.z = (tmp == 0);

   827 		    break;

   828 		case 8: /* UMULL */

   829 		case 9: /* UMULLS */

   830 		case 10: /* UMLAL */

   831 		case 11: /* UMLALS */

   832 		case 12: /* SMULL */

   833 		case 13: /* SMULLS */

   834 		case 14: /* SMLAL */

   835 		case 15: /* SMLALS */

   836 		    UNIMP(ir);

   837 		    break;

   838 		case 16: /* SWP */

   839 		    tmp = arm_read_long( RN(ir) );

   840 		    switch( RN(ir) & 0x03 ) {

   841 		    case 1:

   842 			tmp = ROTATE_RIGHT_LONG(tmp, 8);

   843 			break;

   844 		    case 2:

   845 			tmp = ROTATE_RIGHT_LONG(tmp, 16);

   846 			break;

   847 		    case 3:

   848 			tmp = ROTATE_RIGHT_LONG(tmp, 24);

   849 			break;

   850 		    }

   851 		    arm_write_long( RN(ir), RM(ir) );

   852 		    LRD(ir) = tmp;

   853 		    break;

   854 		case 20: /* SWPB */

   855 		    tmp = arm_read_byte( RN(ir) );

   856 		    arm_write_byte( RN(ir), RM(ir) );

   857 		    LRD(ir) = tmp;

   858 		    break;

   859 		default:

   860 		    UNIMP(ir);

   861 		}

   862 		break;

   863 	    case 1:

   864 		if( LFLAG(ir) ) {

   865 		    /* LDRH */

   866 		} else {

   867 		    /* STRH */

   868 		}

   869 		UNIMP(ir);

   870 		break;

   871 	    case 2:

   872 		if( LFLAG(ir) ) {

   873 		    /* LDRSB */

   874 		} else {

   875 		}

   876 		UNIMP(ir);

   877 		break;

   878 	    case 3:

   879 		if( LFLAG(ir) ) {

   880 		    /* LDRSH */

   881 		} else {

   882 		}

   883 		UNIMP(ir);

   884 		break;

   885 	    }

   886 	} else {

   887 	    /* Data processing */

   889 	    switch(OPCODE(ir)) {

   890 	    case 0: /* AND Rd, Rn, operand */

   891 		LRD(ir) = RN(ir) & arm_get_shift_operand(ir);

   892 		break;

   893 	    case 1: /* ANDS Rd, Rn, operand */

   894 		operand = arm_get_shift_operand_s(ir) & RN(ir);

   895 		LRD(ir) = operand;

   896 		if( RDn(ir) == 15 ) {

   897 		    arm_restore_cpsr();

   898 		} else {

   899 		    armr.n = operand>>31;

   900 		    armr.z = (operand == 0);

   901 		    armr.c = armr.shift_c;

   902 		}

   903 		break;

   904 	    case 2: /* EOR Rd, Rn, operand */

   905 		LRD(ir) = RN(ir) ^ arm_get_shift_operand(ir);

   906 		break;

   907 	    case 3: /* EORS Rd, Rn, operand */

   908 		operand = arm_get_shift_operand_s(ir) ^ RN(ir);

   909 		LRD(ir) = operand;

   910 		if( RDn(ir) == 15 ) {

   911 		    arm_restore_cpsr();

   912 		} else {

   913 		    armr.n = operand>>31;

   914 		    armr.z = (operand == 0);

   915 		    armr.c = armr.shift_c;

   916 		}

   917 		break;

   918 	    case 4: /* SUB Rd, Rn, operand */

   919 		LRD(ir) = RN(ir) - arm_get_shift_operand(ir);

   920 		break;

   921 	    case 5: /* SUBS Rd, Rn, operand */

   922 		operand = RN(ir);

   923 		operand2 = arm_get_shift_operand(ir);

   924 		tmp = operand - operand2;

   925 		LRD(ir) = tmp;

   926 		if( RDn(ir) == 15 ) {

   927 		    arm_restore_cpsr();

   928 		} else {

   929 		    armr.n = tmp>>31;

   930 		    armr.z = (tmp == 0);

   931 		    armr.c = IS_NOTBORROW(tmp,operand,operand2);

   932 		    armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);

   933 		}

   934 		break;

   935 	    case 6: /* RSB Rd, operand, Rn */

   936 		LRD(ir) = arm_get_shift_operand(ir) - RN(ir);

   937 		break;

   938 	    case 7: /* RSBS Rd, operand, Rn */

   939 		operand = arm_get_shift_operand(ir);

   940 		operand2 = RN(ir);

   941 		tmp = operand - operand2;

   942 		LRD(ir) = tmp;

   943 		if( RDn(ir) == 15 ) {

   944 		    arm_restore_cpsr();

   945 		} else {

   946 		    armr.n = tmp>>31;

   947 		    armr.z = (tmp == 0);

   948 		    armr.c = IS_NOTBORROW(tmp,operand,operand2);

   949 		    armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);

   950 		}

   951 		break;

   952 	    case 8: /* ADD Rd, Rn, operand */

   953 		LRD(ir) = RN(ir) + arm_get_shift_operand(ir);

   954 		break;

   955 	    case 9: /* ADDS Rd, Rn, operand */

   956 		operand = arm_get_shift_operand(ir);

   957 		operand2 = RN(ir);

   958 		tmp = operand + operand2;

   959 		LRD(ir) = tmp;

   960 		if( RDn(ir) == 15 ) {

   961 		    arm_restore_cpsr();

   962 		} else {

   963 		    armr.n = tmp>>31;

   964 		    armr.z = (tmp == 0);

   965 		    armr.c = IS_CARRY(tmp,operand,operand2);

   966 		    armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);

   967 		}

   968 		break;

   969 	    case 10: /* ADC */

   970 		LRD(ir) = RN(ir) + arm_get_shift_operand(ir) +

   971 		    (armr.c ? 1 : 0);

   972 		break;

   973 	    case 11: /* ADCS */

   974 		operand = arm_get_shift_operand(ir);

   975 		operand2 = RN(ir);

   976 		tmp = operand + operand2;

   977 		tmp2 = tmp + armr.c ? 1 : 0;

   978 		LRD(ir) = tmp2;

   979 		if( RDn(ir) == 15 ) {

   980 		    arm_restore_cpsr();

   981 		} else {

   982 		    armr.n = tmp >> 31;

   983 		    armr.z = (tmp == 0 );

   984 		    armr.c = IS_CARRY(tmp,operand,operand2) ||

   985 			(tmp2 < tmp);

   986 		    armr.v = IS_ADDOVERFLOW(tmp,operand, operand2) ||

   987 			((tmp&0x80000000) != (tmp2&0x80000000));

   988 		}

   989 		break;

   990 	    case 12: /* SBC */

   991 		LRD(ir) = RN(ir) - arm_get_shift_operand(ir) -

   992 		    (armr.c ? 0 : 1);

   993 		break;

   994 	    case 13: /* SBCS */

   995 		operand = RN(ir);

   996 		operand2 = arm_get_shift_operand(ir);

   997 		tmp = operand - operand2;

   998 		tmp2 = tmp - (armr.c ? 0 : 1);

   999 		if( RDn(ir) == 15 ) {

  1000 		    arm_restore_cpsr();

  1001 		} else {

  1002 		    armr.n = tmp >> 31;

  1003 		    armr.z = (tmp == 0 );

  1004 		    armr.c = IS_NOTBORROW(tmp,operand,operand2) &&

  1005 			(tmp2<tmp);

  1006 		    armr.v = IS_SUBOVERFLOW(tmp,operand,operand2) ||

  1007 			((tmp&0x80000000) != (tmp2&0x80000000));

  1008 		}

  1009 		break;

  1010 	    case 14: /* RSC */

  1011 		LRD(ir) = arm_get_shift_operand(ir) - RN(ir) -

  1012 		    (armr.c ? 0 : 1);

  1013 		break;

  1014 	    case 15: /* RSCS */

  1015 		operand = arm_get_shift_operand(ir);

  1016 		operand2 = RN(ir);

  1017 		tmp = operand - operand2;

  1018 		tmp2 = tmp - (armr.c ? 0 : 1);

  1019 		if( RDn(ir) == 15 ) {

  1020 		    arm_restore_cpsr();

  1021 		} else {

  1022 		    armr.n = tmp >> 31;

  1023 		    armr.z = (tmp == 0 );

  1024 		    armr.c = IS_NOTBORROW(tmp,operand,operand2) &&

  1025 			(tmp2<tmp);

  1026 		    armr.v = IS_SUBOVERFLOW(tmp,operand,operand2) ||

  1027 			((tmp&0x80000000) != (tmp2&0x80000000));

  1028 		}

  1029 		break;

  1030 	    case 17: /* TST Rn, operand */

  1031 		operand = arm_get_shift_operand_s(ir) & RN(ir);

  1032 		armr.n = operand>>31;

  1033 		armr.z = (operand == 0);

  1034 		armr.c = armr.shift_c;

  1035 		break;

  1036 	    case 19: /* TEQ Rn, operand */

  1037 		operand = arm_get_shift_operand_s(ir) ^ RN(ir);

  1038 		armr.n = operand>>31;

  1039 		armr.z = (operand == 0);

  1040 		armr.c = armr.shift_c;

  1041 		break;

  1042 	    case 21: /* CMP Rn, operand */

  1043 		operand = RN(ir);

  1044 		operand2 = arm_get_shift_operand(ir);

  1045 		tmp = operand - operand2;

  1046 		armr.n = tmp>>31;

  1047 		armr.z = (tmp == 0);

  1048 		armr.c = IS_NOTBORROW(tmp,operand,operand2);

  1049 		armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);

  1050 		break;

  1051 	    case 23: /* CMN Rn, operand */

  1052 		operand = RN(ir);

  1053 		operand2 = arm_get_shift_operand(ir);

  1054 		tmp = operand + operand2;

  1055 		armr.n = tmp>>31;

  1056 		armr.z = (tmp == 0);

  1057 		armr.c = IS_CARRY(tmp,operand,operand2);

  1058 		armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);

  1059 		break;

  1060 	    case 24: /* ORR Rd, Rn, operand */

  1061 		LRD(ir) = RN(ir) | arm_get_shift_operand(ir);

  1062 		break;

  1063 	    case 25: /* ORRS Rd, Rn, operand */

  1064 		operand = arm_get_shift_operand_s(ir) | RN(ir);

  1065 		LRD(ir) = operand;

  1066 		if( RDn(ir) == 15 ) {

  1067 		    arm_restore_cpsr();

  1068 		} else {

  1069 		    armr.n = operand>>31;

  1070 		    armr.z = (operand == 0);

  1071 		    armr.c = armr.shift_c;

  1072 		}

  1073 		break;

  1074 	    case 26: /* MOV Rd, operand */

  1075 		LRD(ir) = arm_get_shift_operand(ir);

  1076 		break;

  1077 	    case 27: /* MOVS Rd, operand */

  1078 		operand = arm_get_shift_operand_s(ir);

  1079 		LRD(ir) = operand;

  1080 		if( RDn(ir) == 15 ) {

  1081 		    arm_restore_cpsr();

  1082 		} else {

  1083 		    armr.n = operand>>31;

  1084 		    armr.z = (operand == 0);

  1085 		    armr.c = armr.shift_c;

  1086 		}

  1087 		break;

  1088 	    case 28: /* BIC Rd, Rn, operand */

  1089 		LRD(ir) = RN(ir) & (~arm_get_shift_operand(ir));

  1090 		break;

  1091 	    case 29: /* BICS Rd, Rn, operand */

  1092 		operand = RN(ir) & (~arm_get_shift_operand_s(ir));

  1093 		LRD(ir) = operand;

  1094 		if( RDn(ir) == 15 ) {

  1095 		    arm_restore_cpsr();

  1096 		} else {

  1097 		    armr.n = operand>>31;

  1098 		    armr.z = (operand == 0);

  1099 		    armr.c = armr.shift_c;

  1100 		}

  1101 		break;

  1102 	    case 30: /* MVN Rd, operand */

  1103 		LRD(ir) = ~arm_get_shift_operand(ir);

  1104 		break;

  1105 	    case 31: /* MVNS Rd, operand */

  1106 		operand = ~arm_get_shift_operand_s(ir);

  1107 		LRD(ir) = operand;

  1108 		if( RDn(ir) == 15 ) {

  1109 		    arm_restore_cpsr();

  1110 		} else {

  1111 		    armr.n = operand>>31;

  1112 		    armr.z = (operand == 0);

  1113 		    armr.c = armr.shift_c;

  1114 		}

  1115 		break;

  1116 	    default:

  1117 		UNIMP(ir);

  1118 	    }

  1119 	}

  1120 	break;

  1121     case 1: /* Load/store */

  1122 	operand = arm_get_address_operand(ir);

  1123 	switch( (ir>>20)&0x17 ) {

  1124 	case 0: case 16: case 18: /* STR Rd, address */

  1125 	    arm_write_long( operand, RD(ir) );

  1126 	    break;

  1127 	case 1: case 17: case 19: /* LDR Rd, address */

  1128 	    LRD(ir) = arm_read_long(operand);

  1129 	    break;

  1130 	case 2: /* STRT Rd, address */

  1131 	    arm_write_long_user( operand, RD(ir) );

  1132 	    break;

  1133 	case 3: /* LDRT Rd, address */

  1134 	    LRD(ir) = arm_read_long_user( operand );

  1135 	    break;

  1136 	case 4: case 20: case 22: /* STRB Rd, address */

  1137 	    arm_write_byte( operand, RD(ir) );

  1138 	    break;

  1139 	case 5: case 21: case 23: /* LDRB Rd, address */

  1140 	    LRD(ir) = arm_read_byte( operand );

  1141 	    break;

  1142 	case 6: /* STRBT Rd, address */

  1143 	    arm_write_byte_user( operand, RD(ir) );

  1144 	    break;

  1145 	case 7: /* LDRBT Rd, address */

  1146 	    LRD(ir) = arm_read_byte_user( operand );

  1147 	    break;

  1148 	}

  1149 	break;

  1150     case 2: /* Load/store multiple, branch*/

  1151 	if( (ir & 0x02000000) == 0x02000000 ) { /* B[L] imm24 */

  1152 	    operand = (SIGNEXT24(ir&0x00FFFFFF) << 2);

  1153 	    if( (ir & 0x01000000) == 0x01000000 ) {

  1154 		armr.r[14] = pc; /* BL */

  1155 	    }

  1156 	    armr.r[15] = pc + 4 + operand;

  1157 	} else { /* Load/store multiple */

  1158 	    gboolean needRestore = FALSE;

  1159 	    operand = RN(ir);

  1161 	    switch( (ir & 0x01D00000) >> 20 ) {

  1162 	    case 0: /* STMDA */

  1163 		if( ir & 0x8000 ) {

  1164 		    arm_write_long( operand, armr.r[15]+4 );

  1165 		    operand -= 4;

  1166 		}

  1167 		for( i=14; i>= 0; i-- ) {

  1168 		    if( (ir & (1<<i)) ) {

  1169 			arm_write_long( operand, armr.r[i] );

  1170 			operand -= 4;

  1171 		    }

  1172 		}

  1173 		break;

  1174 	    case 1: /* LDMDA */

  1175 		for( i=15; i>= 0; i-- ) {

  1176 		    if( (ir & (1<<i)) ) {

  1177 			armr.r[i] = arm_read_long( operand );

  1178 			operand -= 4;

  1179 		    }

  1180 		}

  1181 		break;

  1182 	    case 4: /* STMDA (S) */

  1183 		if( ir & 0x8000 ) {

  1184 		    arm_write_long( operand, armr.r[15]+4 );

  1185 		    operand -= 4;

  1186 		}

  1187 		for( i=14; i>= 0; i-- ) {

  1188 		    if( (ir & (1<<i)) ) {

  1189 			arm_write_long( operand, USER_R(i) );

  1190 			operand -= 4;

  1191 		    }

  1192 		}

  1193 		break;

  1194 	    case 5: /* LDMDA (S) */

  1195 		if( (ir&0x00008000) ) { /* Load PC */

  1196 		    for( i=15; i>= 0; i-- ) {

  1197 			if( (ir & (1<<i)) ) {

  1198 			    armr.r[i] = arm_read_long( operand );

  1199 			    operand -= 4;

  1200 			}

  1201 		    }

  1202 		    needRestore = TRUE;

  1203 		} else {

  1204 		    for( i=15; i>= 0; i-- ) {

  1205 			if( (ir & (1<<i)) ) {

  1206 			    USER_R(i) = arm_read_long( operand );

  1207 			    operand -= 4;

  1208 			}

  1209 		    }

  1210 		}

  1211 		break;

  1212 	    case 8: /* STMIA */

  1213 		for( i=0; i< 15; i++ ) {

  1214 		    if( (ir & (1<<i)) ) {

  1215 			arm_write_long( operand, armr.r[i] );

  1216 			operand += 4;

  1217 		    }

  1218 		}

  1219 		if( ir & 0x8000 ) {

  1220 		    arm_write_long( operand, armr.r[15]+4 );

  1221 		    operand += 4;

  1222 		}

  1223 		break;

  1224 	    case 9: /* LDMIA */

  1225 		for( i=0; i< 16; i++ ) {

  1226 		    if( (ir & (1<<i)) ) {

  1227 			armr.r[i] = arm_read_long( operand );

  1228 			operand += 4;

  1229 		    }

  1230 		}

  1231 		break;

  1232 	    case 12: /* STMIA (S) */

  1233 		for( i=0; i< 15; i++ ) {

  1234 		    if( (ir & (1<<i)) ) {

  1235 			arm_write_long( operand, USER_R(i) );

  1236 			operand += 4;

  1237 		    }

  1238 		}

  1239 		if( ir & 0x8000 ) {

  1240 		    arm_write_long( operand, armr.r[15]+4 );

  1241 		    operand += 4;

  1242 		}

  1243 		break;

  1244 	    case 13: /* LDMIA (S) */

  1245 		if( (ir&0x00008000) ) { /* Load PC */

  1246 		    for( i=0; i < 16; i++ ) {

  1247 			if( (ir & (1<<i)) ) {

  1248 			    armr.r[i] = arm_read_long( operand );

  1249 			    operand += 4;

  1250 			}

  1251 		    }

  1252 		    needRestore = TRUE;

  1253 		} else {

  1254 		    for( i=0; i < 16; i++ ) {

  1255 			if( (ir & (1<<i)) ) {

  1256 			    USER_R(i) = arm_read_long( operand );

  1257 			    operand += 4;

  1258 			}

  1259 		    }

  1260 		}

  1261 		break;

  1262 	    case 16: /* STMDB */

  1263 		if( ir & 0x8000 ) {

  1264 		    operand -= 4;

  1265 		    arm_write_long( operand, armr.r[15]+4 );

  1266 		}

  1267 		for( i=14; i>= 0; i-- ) {

  1268 		    if( (ir & (1<<i)) ) {

  1269 			operand -= 4;

  1270 			arm_write_long( operand, armr.r[i] );

  1271 		    }

  1272 		}

  1273 		break;

  1274 	    case 17: /* LDMDB */

  1275 		for( i=15; i>= 0; i-- ) {

  1276 		    if( (ir & (1<<i)) ) {

  1277 			operand -= 4;

  1278 			armr.r[i] = arm_read_long( operand );

  1279 		    }

  1280 		}

  1281 		break;

  1282 	    case 20: /* STMDB (S) */

  1283 		if( ir & 0x8000 ) {

  1284 		    operand -= 4;

  1285 		    arm_write_long( operand, armr.r[15]+4 );

  1286 		}

  1287 		for( i=14; i>= 0; i-- ) {

  1288 		    if( (ir & (1<<i)) ) {

  1289 			operand -= 4;

  1290 			arm_write_long( operand, USER_R(i) );

  1291 		    }

  1292 		}

  1293 		break;

  1294 	    case 21: /* LDMDB (S) */

  1295 		if( (ir&0x00008000) ) { /* Load PC */

  1296 		    for( i=15; i>= 0; i-- ) {

  1297 			if( (ir & (1<<i)) ) {

  1298 			    operand -= 4;

  1299 			    armr.r[i] = arm_read_long( operand );

  1300 			}

  1301 		    }

  1302 		    needRestore = TRUE;

  1303 		} else {

  1304 		    for( i=15; i>= 0; i-- ) {

  1305 			if( (ir & (1<<i)) ) {

  1306 			    operand -= 4;

  1307 			    USER_R(i) = arm_read_long( operand );

  1308 			}

  1309 		    }

  1310 		}

  1311 		break;

  1312 	    case 24: /* STMIB */

  1313 		for( i=0; i< 15; i++ ) {

  1314 		    if( (ir & (1<<i)) ) {

  1315 			operand += 4;

  1316 			arm_write_long( operand, armr.r[i] );

  1317 		    }

  1318 		}

  1319 		if( ir & 0x8000 ) {

  1320 		    operand += 4;

  1321 		    arm_write_long( operand, armr.r[15]+4 );

  1322 		}

  1323 		break;

  1324 	    case 25: /* LDMIB */

  1325 		for( i=0; i< 16; i++ ) {

  1326 		    if( (ir & (1<<i)) ) {

  1327 			operand += 4;

  1328 			armr.r[i] = arm_read_long( operand );

  1329 		    }

  1330 		}

  1331 		break;

  1332 	    case 28: /* STMIB (S) */

  1333 		for( i=0; i< 15; i++ ) {

  1334 		    if( (ir & (1<<i)) ) {

  1335 			operand += 4;

  1336 			arm_write_long( operand, USER_R(i) );

  1337 		    }

  1338 		}

  1339 		if( ir & 0x8000 ) {

  1340 		    operand += 4;

  1341 		    arm_write_long( operand, armr.r[15]+4 );

  1342 		}

  1343 		break;

  1344 	    case 29: /* LDMIB (S) */

  1345 		if( (ir&0x00008000) ) { /* Load PC */

  1346 		    for( i=0; i < 16; i++ ) {

  1347 			if( (ir & (1<<i)) ) {

  1348 			    operand += 4;

  1349 			    armr.r[i] = arm_read_long( operand );

  1350 			}

  1351 		    }

  1352 		    needRestore = TRUE;

  1353 		} else {

  1354 		    for( i=0; i < 16; i++ ) {

  1355 			if( (ir & (1<<i)) ) {

  1356 			    operand += 4;

  1357 			    USER_R(i) = arm_read_long( operand );

  1358 			}

  1359 		    }

  1360 		}

  1361 		break;

  1362 	    }

  1364 	    if( WFLAG(ir) )

  1365 		LRN(ir) = operand;

  1366 	    if( needRestore )

  1367 		arm_restore_cpsr();

  1368 	}

  1369 	break;

  1370     case 3: /* Copro */

  1371 	if( (ir & 0x0F000000) == 0x0F000000 ) { /* SWI */

  1372 	    arm_raise_exception( EXC_SOFTWARE );

  1373 	} else {

  1374 	    UNIMP(ir);

  1375 	}

  1376 	break;

  1377     }

  1379     }

  1381     if( armr.r[15] >= 0x00200000 ) {

  1382 	armr.running = FALSE;

  1383 	ERROR( "ARM Halted: BRANCH to invalid address %08X at %08X", armr.r[15], pc );

  1384 	return FALSE;

  1385     }

  1386     return TRUE;

  1387 }