filename | src/asic.c |
changeset | 833:1ea87e0221f8 |
prev | 753:1fe39c3a9bbc |
next | 855:b937948d79d9 |
author | nkeynes |
date | Wed Aug 27 09:42:16 2008 +0000 (15 years ago) |
permissions | -rw-r--r-- |
last change | Raise IDE DMA event on end-of-dma, not end-of-transfer (*sigh*) (actually not 100% correct yet, but closer) |
view | annotate | diff | log | raw |
1 /**
2 * $Id$
3 *
4 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
5 * and DMA).
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #define MODULE asic_module
22 #include <assert.h>
23 #include <stdlib.h>
24 #include "dream.h"
25 #include "mem.h"
26 #include "sh4/intc.h"
27 #include "sh4/dmac.h"
28 #include "sh4/sh4.h"
29 #include "dreamcast.h"
30 #include "maple/maple.h"
31 #include "gdrom/ide.h"
32 #include "pvr2/pvr2.h"
33 #include "asic.h"
34 #define MMIO_IMPL
35 #include "asic.h"
36 /*
37 * Open questions:
38 * 1) Does changing the mask after event occurance result in the
39 * interrupt being delivered immediately?
40 * TODO: Logic diagram of ASIC event/interrupt logic.
41 *
42 * ... don't even get me started on the "EXTDMA" page, about which, apparently,
43 * practically nothing is publicly known...
44 */
46 static void asic_check_cleared_events( void );
47 static void asic_init( void );
48 static void asic_reset( void );
49 static uint32_t asic_run_slice( uint32_t nanosecs );
50 static void asic_save_state( FILE *f );
51 static int asic_load_state( FILE *f );
52 static uint32_t g2_update_fifo_status( uint32_t slice_cycle );
54 struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, asic_run_slice,
55 NULL, asic_save_state, asic_load_state };
57 #define G2_BIT5_TICKS 60
58 #define G2_BIT4_TICKS 160
59 #define G2_BIT0_ON_TICKS 120
60 #define G2_BIT0_OFF_TICKS 420
62 struct asic_g2_state {
63 int bit5_off_timer;
64 int bit4_on_timer;
65 int bit4_off_timer;
66 int bit0_on_timer;
67 int bit0_off_timer;
68 };
70 static struct asic_g2_state g2_state;
72 static uint32_t asic_run_slice( uint32_t nanosecs )
73 {
74 g2_update_fifo_status(nanosecs);
75 if( g2_state.bit5_off_timer <= (int32_t)nanosecs ) {
76 g2_state.bit5_off_timer = -1;
77 } else {
78 g2_state.bit5_off_timer -= nanosecs;
79 }
81 if( g2_state.bit4_off_timer <= (int32_t)nanosecs ) {
82 g2_state.bit4_off_timer = -1;
83 } else {
84 g2_state.bit4_off_timer -= nanosecs;
85 }
86 if( g2_state.bit4_on_timer <= (int32_t)nanosecs ) {
87 g2_state.bit4_on_timer = -1;
88 } else {
89 g2_state.bit4_on_timer -= nanosecs;
90 }
92 if( g2_state.bit0_off_timer <= (int32_t)nanosecs ) {
93 g2_state.bit0_off_timer = -1;
94 } else {
95 g2_state.bit0_off_timer -= nanosecs;
96 }
97 if( g2_state.bit0_on_timer <= (int32_t)nanosecs ) {
98 g2_state.bit0_on_timer = -1;
99 } else {
100 g2_state.bit0_on_timer -= nanosecs;
101 }
103 return nanosecs;
104 }
106 static void asic_init( void )
107 {
108 register_io_region( &mmio_region_ASIC );
109 register_io_region( &mmio_region_EXTDMA );
110 asic_reset();
111 }
113 static void asic_reset( void )
114 {
115 memset( &g2_state, 0xFF, sizeof(g2_state) );
116 }
118 static void asic_save_state( FILE *f )
119 {
120 fwrite( &g2_state, sizeof(g2_state), 1, f );
121 }
123 static int asic_load_state( FILE *f )
124 {
125 if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 )
126 return 1;
127 else
128 return 0;
129 }
132 /**
133 * Setup the timers for the 3 FIFO status bits following a write through the G2
134 * bus from the SH4 side. The timing is roughly as follows: (times are
135 * approximate based on software readings - I wouldn't take this as gospel but
136 * it seems to be enough to fool most programs).
137 * 0ns: Bit 5 (Input fifo?) goes high immediately on the write
138 * 40ns: Bit 5 goes low and bit 4 goes high
139 * 120ns: Bit 4 goes low, bit 0 goes high
140 * 240ns: Bit 0 goes low.
141 *
142 * Additional writes while the FIFO is in operation extend the time that the
143 * bits remain high as one might expect, without altering the time at which
144 * they initially go high.
145 */
146 void asic_g2_write_word()
147 {
148 if( g2_state.bit5_off_timer < (int32_t)sh4r.slice_cycle ) {
149 g2_state.bit5_off_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
150 } else {
151 g2_state.bit5_off_timer += G2_BIT5_TICKS;
152 }
154 if( g2_state.bit4_on_timer < (int32_t)sh4r.slice_cycle ) {
155 g2_state.bit4_on_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
156 }
158 if( g2_state.bit4_off_timer < (int32_t)sh4r.slice_cycle ) {
159 g2_state.bit4_off_timer = g2_state.bit4_on_timer + G2_BIT4_TICKS;
160 } else {
161 g2_state.bit4_off_timer += G2_BIT4_TICKS;
162 }
164 if( g2_state.bit0_on_timer < (int32_t)sh4r.slice_cycle ) {
165 g2_state.bit0_on_timer = sh4r.slice_cycle + G2_BIT0_ON_TICKS;
166 }
168 if( g2_state.bit0_off_timer < (int32_t)sh4r.slice_cycle ) {
169 g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
170 } else {
171 g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
172 }
174 MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
175 }
177 static uint32_t g2_update_fifo_status( uint32_t nanos )
178 {
179 uint32_t val = MMIO_READ( ASIC, G2STATUS );
180 if( ((uint32_t)g2_state.bit5_off_timer) <= nanos ) {
181 val = val & (~0x20);
182 g2_state.bit5_off_timer = -1;
183 }
184 if( ((uint32_t)g2_state.bit4_on_timer) <= nanos ) {
185 val = val | 0x10;
186 g2_state.bit4_on_timer = -1;
187 }
188 if( ((uint32_t)g2_state.bit4_off_timer) <= nanos ) {
189 val = val & (~0x10);
190 g2_state.bit4_off_timer = -1;
191 }
193 if( ((uint32_t)g2_state.bit0_on_timer) <= nanos ) {
194 val = val | 0x01;
195 g2_state.bit0_on_timer = -1;
196 }
197 if( ((uint32_t)g2_state.bit0_off_timer) <= nanos ) {
198 val = val & (~0x01);
199 g2_state.bit0_off_timer = -1;
200 }
202 MMIO_WRITE( ASIC, G2STATUS, val );
203 return val;
204 }
206 static int g2_read_status() {
207 return g2_update_fifo_status( sh4r.slice_cycle );
208 }
211 void asic_event( int event )
212 {
213 int offset = ((event&0x60)>>3);
214 int result = (MMIO_READ(ASIC, PIRQ0 + offset)) |= (1<<(event&0x1F));
216 if( result & MMIO_READ(ASIC, IRQA0 + offset) )
217 intc_raise_interrupt( INT_IRQ13 );
218 if( result & MMIO_READ(ASIC, IRQB0 + offset) )
219 intc_raise_interrupt( INT_IRQ11 );
220 if( result & MMIO_READ(ASIC, IRQC0 + offset) )
221 intc_raise_interrupt( INT_IRQ9 );
223 if( event >= 64 ) { /* Third word */
224 asic_event( EVENT_CASCADE2 );
225 } else if( event >= 32 ) { /* Second word */
226 asic_event( EVENT_CASCADE1 );
227 }
228 }
230 void asic_clear_event( int event ) {
231 int offset = ((event&0x60)>>3);
232 uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset) & (~(1<<(event&0x1F)));
233 MMIO_WRITE( ASIC, PIRQ0 + offset, result );
234 if( result == 0 ) {
235 /* clear cascades if necessary */
236 if( event >= 64 ) {
237 MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
238 } else if( event >= 32 ) {
239 MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0xBFFFFFFF );
240 }
241 }
243 asic_check_cleared_events();
244 }
246 void asic_check_cleared_events( )
247 {
248 int i, setA = 0, setB = 0, setC = 0;
249 uint32_t bits;
250 for( i=0; i<12; i+=4 ) {
251 bits = MMIO_READ( ASIC, PIRQ0 + i );
252 setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
253 setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
254 setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
255 }
256 if( setA == 0 )
257 intc_clear_interrupt( INT_IRQ13 );
258 if( setB == 0 )
259 intc_clear_interrupt( INT_IRQ11 );
260 if( setC == 0 )
261 intc_clear_interrupt( INT_IRQ9 );
262 }
264 void asic_event_mask_changed( )
265 {
266 int i, setA = 0, setB = 0, setC = 0;
267 uint32_t bits;
268 for( i=0; i<12; i+=4 ) {
269 bits = MMIO_READ( ASIC, PIRQ0 + i );
270 setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
271 setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
272 setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
273 }
274 if( setA == 0 )
275 intc_clear_interrupt( INT_IRQ13 );
276 else
277 intc_raise_interrupt( INT_IRQ13 );
278 if( setB == 0 )
279 intc_clear_interrupt( INT_IRQ11 );
280 else
281 intc_raise_interrupt( INT_IRQ11 );
282 if( setC == 0 )
283 intc_clear_interrupt( INT_IRQ9 );
284 else
285 intc_raise_interrupt( INT_IRQ9 );
286 }
288 void g2_dma_transfer( int channel )
289 {
290 uint32_t offset = channel << 5;
292 if( MMIO_READ( EXTDMA, G2DMA0CTL1 + offset ) == 1 ) {
293 if( MMIO_READ( EXTDMA, G2DMA0CTL2 + offset ) == 1 ) {
294 uint32_t extaddr = MMIO_READ( EXTDMA, G2DMA0EXT + offset );
295 uint32_t sh4addr = MMIO_READ( EXTDMA, G2DMA0SH4 + offset );
296 uint32_t length = MMIO_READ( EXTDMA, G2DMA0SIZ + offset ) & 0x1FFFFFFF;
297 uint32_t dir = MMIO_READ( EXTDMA, G2DMA0DIR + offset );
298 // uint32_t mode = MMIO_READ( EXTDMA, G2DMA0MOD + offset );
299 unsigned char buf[length];
300 if( dir == 0 ) { /* SH4 to device */
301 mem_copy_from_sh4( buf, sh4addr, length );
302 mem_copy_to_sh4( extaddr, buf, length );
303 } else { /* Device to SH4 */
304 mem_copy_from_sh4( buf, extaddr, length );
305 mem_copy_to_sh4( sh4addr, buf, length );
306 }
307 MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
308 asic_event( EVENT_G2_DMA0 + channel );
309 } else {
310 MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
311 }
312 }
313 }
315 void asic_ide_dma_transfer( )
316 {
317 if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
318 if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 ) {
319 MMIO_WRITE( EXTDMA, IDEDMATXSIZ, 0 );
321 uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );
322 uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
323 // int dir = MMIO_READ( EXTDMA, IDEDMADIR );
325 uint32_t xfer = ide_read_data_dma( addr, length );
326 MMIO_WRITE( EXTDMA, IDEDMATXSIZ, xfer );
327 MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
328 asic_event( EVENT_IDE_DMA );
329 } else { /* 0 */
330 MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
331 }
332 }
333 }
335 void pvr_dma_transfer( )
336 {
337 sh4addr_t destaddr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
338 uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
339 unsigned char *data = alloca( count );
340 uint32_t rcount = DMAC_get_buffer( 2, data, count );
341 if( rcount != count )
342 WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
344 pvr2_dma_write( destaddr, data, rcount );
346 MMIO_WRITE( ASIC, PVRDMACTL, 0 );
347 MMIO_WRITE( ASIC, PVRDMACNT, 0 );
348 if( destaddr & 0x01000000 ) { /* Write to texture RAM */
349 MMIO_WRITE( ASIC, PVRDMADEST, destaddr + rcount );
350 }
351 asic_event( EVENT_PVR_DMA );
352 }
354 void sort_dma_transfer( )
355 {
356 sh4addr_t table_addr = MMIO_READ( ASIC, SORTDMATBL );
357 sh4addr_t data_addr = MMIO_READ( ASIC, SORTDMADATA );
358 int table_size = MMIO_READ( ASIC, SORTDMATSIZ );
359 int addr_shift = MMIO_READ( ASIC, SORTDMAASIZ ) ? 5 : 0;
360 int count = 1;
362 uint32_t *table32 = (uint32_t *)mem_get_region( table_addr );
363 uint16_t *table16 = (uint16_t *)table32;
364 uint32_t next = table_size ? (*table32++) : (uint32_t)(*table16++);
365 while(1) {
366 next &= 0x07FFFFFF;
367 if( next == 1 ) {
368 next = table_size ? (*table32++) : (uint32_t)(*table16++);
369 count++;
370 continue;
371 } else if( next == 2 ) {
372 asic_event( EVENT_SORT_DMA );
373 break;
374 }
375 uint32_t *data = (uint32_t *)mem_get_region(data_addr + (next<<addr_shift));
376 if( data == NULL ) {
377 break;
378 }
380 uint32_t *poly = pvr2_ta_find_polygon_context(data, 128);
381 if( poly == NULL ) {
382 asic_event( EVENT_SORT_DMA_ERR );
383 break;
384 }
385 uint32_t size = poly[6] & 0xFF;
386 if( size == 0 ) {
387 size = 0x100;
388 }
389 next = poly[7];
390 pvr2_ta_write( (unsigned char *)data, size<<5 );
391 }
393 MMIO_WRITE( ASIC, SORTDMACNT, count );
394 MMIO_WRITE( ASIC, SORTDMACTL, 0 );
395 }
397 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
398 {
399 switch( reg ) {
400 case PIRQ1:
401 break; /* Treat this as read-only for the moment */
402 case PIRQ0:
403 val = val & 0x3FFFFFFF; /* Top two bits aren't clearable */
404 MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
405 asic_check_cleared_events();
406 break;
407 case PIRQ2:
408 /* Clear any events */
409 val = MMIO_READ(ASIC, reg)&(~val);
410 MMIO_WRITE( ASIC, reg, val );
411 if( val == 0 ) { /* all clear - clear the cascade bit */
412 MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
413 }
414 asic_check_cleared_events();
415 break;
416 case IRQA0:
417 case IRQA1:
418 case IRQA2:
419 case IRQB0:
420 case IRQB1:
421 case IRQB2:
422 case IRQC0:
423 case IRQC1:
424 case IRQC2:
425 MMIO_WRITE( ASIC, reg, val );
426 asic_event_mask_changed();
427 break;
428 case SYSRESET:
429 if( val == 0x7611 ) {
430 dreamcast_reset();
431 } else {
432 WARN( "Unknown value %08X written to SYSRESET port", val );
433 }
434 break;
435 case MAPLE_STATE:
436 MMIO_WRITE( ASIC, reg, val );
437 if( val & 1 ) {
438 uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
439 maple_handle_buffer( maple_addr );
440 MMIO_WRITE( ASIC, reg, 0 );
441 }
442 break;
443 case PVRDMADEST:
444 MMIO_WRITE( ASIC, reg, (val & 0x03FFFFE0) | 0x10000000 );
445 break;
446 case PVRDMACNT:
447 MMIO_WRITE( ASIC, reg, val & 0x00FFFFE0 );
448 break;
449 case PVRDMACTL: /* Initiate PVR DMA transfer */
450 val = val & 0x01;
451 MMIO_WRITE( ASIC, reg, val );
452 if( val == 1 ) {
453 pvr_dma_transfer();
454 }
455 break;
456 case SORTDMATBL: case SORTDMADATA:
457 MMIO_WRITE( ASIC, reg, (val & 0x0FFFFFE0) | 0x08000000 );
458 break;
459 case SORTDMATSIZ: case SORTDMAASIZ:
460 MMIO_WRITE( ASIC, reg, (val & 1) );
461 break;
462 case SORTDMACTL:
463 val = val & 1;
464 MMIO_WRITE( ASIC, reg, val );
465 if( val == 1 ) {
466 sort_dma_transfer();
467 }
468 break;
469 case MAPLE_DMA:
470 MMIO_WRITE( ASIC, reg, val );
471 break;
472 default:
473 MMIO_WRITE( ASIC, reg, val );
474 }
475 }
477 int32_t mmio_region_ASIC_read( uint32_t reg )
478 {
479 int32_t val;
480 switch( reg ) {
481 case PIRQ0:
482 case PIRQ1:
483 case PIRQ2:
484 case IRQA0:
485 case IRQA1:
486 case IRQA2:
487 case IRQB0:
488 case IRQB1:
489 case IRQB2:
490 case IRQC0:
491 case IRQC1:
492 case IRQC2:
493 case MAPLE_STATE:
494 val = MMIO_READ(ASIC, reg);
495 return val;
496 case G2STATUS:
497 return g2_read_status();
498 default:
499 val = MMIO_READ(ASIC, reg);
500 return val;
501 }
503 }
505 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
506 {
507 if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
508 return; /* disabled */
509 }
511 switch( reg ) {
512 case IDEALTSTATUS: /* Device control */
513 ide_write_control( val );
514 break;
515 case IDEDATA:
516 ide_write_data_pio( val );
517 break;
518 case IDEFEAT:
519 if( ide_can_write_regs() )
520 idereg.feature = (uint8_t)val;
521 break;
522 case IDECOUNT:
523 if( ide_can_write_regs() )
524 idereg.count = (uint8_t)val;
525 break;
526 case IDELBA0:
527 if( ide_can_write_regs() )
528 idereg.lba0 = (uint8_t)val;
529 break;
530 case IDELBA1:
531 if( ide_can_write_regs() )
532 idereg.lba1 = (uint8_t)val;
533 break;
534 case IDELBA2:
535 if( ide_can_write_regs() )
536 idereg.lba2 = (uint8_t)val;
537 break;
538 case IDEDEV:
539 if( ide_can_write_regs() )
540 idereg.device = (uint8_t)val;
541 break;
542 case IDECMD:
543 if( ide_can_write_regs() || val == IDE_CMD_NOP ) {
544 ide_write_command( (uint8_t)val );
545 }
546 break;
547 case IDEDMASH4:
548 MMIO_WRITE( EXTDMA, reg, val & 0x1FFFFFE0 );
549 break;
550 case IDEDMASIZ:
551 MMIO_WRITE( EXTDMA, reg, val & 0x01FFFFFE );
552 break;
553 case IDEDMADIR:
554 MMIO_WRITE( EXTDMA, reg, val & 1 );
555 break;
556 case IDEDMACTL1:
557 case IDEDMACTL2:
558 MMIO_WRITE( EXTDMA, reg, val & 0x01 );
559 asic_ide_dma_transfer( );
560 break;
561 case IDEACTIVATE:
562 if( val == 0x001FFFFF ) {
563 idereg.interface_enabled = TRUE;
564 /* Conventional wisdom says that this is necessary but not
565 * sufficient to enable the IDE interface.
566 */
567 } else if( val == 0x000042FE ) {
568 idereg.interface_enabled = FALSE;
569 }
570 break;
571 case G2DMA0EXT: case G2DMA0SH4: case G2DMA0SIZ:
572 case G2DMA1EXT: case G2DMA1SH4: case G2DMA1SIZ:
573 case G2DMA2EXT: case G2DMA2SH4: case G2DMA2SIZ:
574 case G2DMA3EXT: case G2DMA3SH4: case G2DMA3SIZ:
575 MMIO_WRITE( EXTDMA, reg, val & 0x9FFFFFE0 );
576 break;
577 case G2DMA0MOD: case G2DMA1MOD: case G2DMA2MOD: case G2DMA3MOD:
578 MMIO_WRITE( EXTDMA, reg, val & 0x07 );
579 break;
580 case G2DMA0DIR: case G2DMA1DIR: case G2DMA2DIR: case G2DMA3DIR:
581 MMIO_WRITE( EXTDMA, reg, val & 0x01 );
582 break;
583 case G2DMA0CTL1:
584 case G2DMA0CTL2:
585 MMIO_WRITE( EXTDMA, reg, val & 1);
586 g2_dma_transfer( 0 );
587 break;
588 case G2DMA0STOP:
589 MMIO_WRITE( EXTDMA, reg, val & 0x37 );
590 break;
591 case G2DMA1CTL1:
592 case G2DMA1CTL2:
593 MMIO_WRITE( EXTDMA, reg, val & 1);
594 g2_dma_transfer( 1 );
595 break;
597 case G2DMA1STOP:
598 MMIO_WRITE( EXTDMA, reg, val & 0x37 );
599 break;
600 case G2DMA2CTL1:
601 case G2DMA2CTL2:
602 MMIO_WRITE( EXTDMA, reg, val &1 );
603 g2_dma_transfer( 2 );
604 break;
605 case G2DMA2STOP:
606 MMIO_WRITE( EXTDMA, reg, val & 0x37 );
607 break;
608 case G2DMA3CTL1:
609 case G2DMA3CTL2:
610 MMIO_WRITE( EXTDMA, reg, val &1 );
611 g2_dma_transfer( 3 );
612 break;
613 case G2DMA3STOP:
614 MMIO_WRITE( EXTDMA, reg, val & 0x37 );
615 break;
616 case PVRDMA2CTL1:
617 case PVRDMA2CTL2:
618 if( val != 0 ) {
619 ERROR( "Write to unimplemented DMA control register %08X", reg );
620 }
621 break;
622 default:
623 MMIO_WRITE( EXTDMA, reg, val );
624 }
625 }
627 MMIO_REGION_READ_FN( EXTDMA, reg )
628 {
629 uint32_t val;
630 if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
631 return 0xFFFFFFFF; /* disabled */
632 }
634 switch( reg ) {
635 case IDEALTSTATUS:
636 val = idereg.status;
637 return val;
638 case IDEDATA: return ide_read_data_pio( );
639 case IDEFEAT: return idereg.error;
640 case IDECOUNT:return idereg.count;
641 case IDELBA0: return ide_get_drive_status();
642 case IDELBA1: return idereg.lba1;
643 case IDELBA2: return idereg.lba2;
644 case IDEDEV: return idereg.device;
645 case IDECMD:
646 val = ide_read_status();
647 return val;
648 default:
649 val = MMIO_READ( EXTDMA, reg );
650 return val;
651 }
652 }
.