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lxdream.org :: lxdream/src/sh4/sh4core.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.c
changeset 23:1ec3acd0594d
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author nkeynes
date Fri Dec 23 11:44:55 2005 +0000 (14 years ago)
permissions -rw-r--r--
last change Start of "real" time slices, general structure in place now
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     1 /**
     2  * $Id: sh4core.c,v 1.9 2005-12-23 11:44:55 nkeynes Exp $
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #include <math.h>
    21 #include "dream.h"
    22 #include "modules.h"
    23 #include "sh4core.h"
    24 #include "sh4mmio.h"
    25 #include "mem.h"
    26 #include "clock.h"
    27 #include "intc.h"
    29 uint32_t sh4_freq = SH4_BASE_RATE;
    30 uint32_t sh4_bus_freq = SH4_BASE_RATE;
    31 uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 2;
    33 /********************** SH4 Module Definition ****************************/
    35 void sh4_init( void );
    36 void sh4_reset( void );
    37 void sh4_run_slice( int );
    38 void sh4_start( void );
    39 void sh4_stop( void );
    40 void sh4_save_state( FILE *f );
    41 int sh4_load_state( FILE *f );
    43 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    44 				       NULL, sh4_run_slice, sh4_stop,
    45 				       sh4_save_state, sh4_load_state };
    47 struct sh4_registers sh4r;
    48 static int running = 0;
    50 void sh4_init(void)
    51 {
    52     register_io_regions( mmio_list_sh4mmio );
    53     mmu_init();
    54 }
    56 void sh4_reset(void)
    57 {
    58     /* zero everything out, for the sake of having a consistent state. */
    59     memset( &sh4r, 0, sizeof(sh4r) );
    60     sh4r.pc    = 0xA0000000;
    61     sh4r.new_pc= 0xA0000002;
    62     sh4r.vbr   = 0x00000000;
    63     sh4r.fpscr = 0x00040001;
    64     sh4r.sr    = 0x700000F0;
    65     intc_reset();
    66 }
    68 void sh4_run_slice( int microsecs ) 
    69 {
    70     int count = sh4_freq * microsecs;
    71     int i;
    73     for( i=0; i<count; i++ ) {
    74 	sh4_execute_instruction();
    75     }
    76     TMU_run_slice( microsecs );
    77     SCIF_run_slice( microsecs );
    78 }
    80 void sh4_stop(void)
    81 {
    82     running = 0;
    83 }
    85 void sh4_save_state( FILE *f )
    86 {
    87     fwrite( &sh4r, sizeof(sh4r), 1, f );
    88     SCIF_save_state( f );
    89 }
    91 int sh4_load_state( FILE * f )
    92 {
    93     fread( &sh4r, sizeof(sh4r), 1, f );
    94     return SCIF_load_state( f );
    95 }
    97 void sh4_run(void)
    98 {
    99     running = 1;
   100     while( running ) {
   101         sh4_execute_instruction();
   102     }
   103 }
   105 /********************** SH4 emulation core  ****************************/
   107 void sh4_set_pc( int pc )
   108 {
   109     sh4r.pc = pc;
   110     sh4r.new_pc = pc+2;
   111 }
   113 void sh4_set_breakpoint( uint32_t pc, int type )
   114 {
   116 }
   118 void sh4_runfor(uint32_t count)
   119 {
   120     running = 1;
   121     while( running && count--) {
   122         int pc = sh4r.pc;
   123         sh4_execute_instruction();
   124         /*
   125         if( sh4r.pc == 0x8C0C1636 ||
   126             sh4r.pc == 0x8C0C1634 ) {
   127             WARN( "Branching to %08X from %08X", sh4r.pc, pc );
   128             sh4_stop();
   129             }*/
   130     }
   131 }
   133 int sh4_isrunning(void)
   134 {
   135     return running;
   136 }
   138 void sh4_runto( uint32_t target_pc, uint32_t count )
   139 {
   140     running = 1;
   141     while( running && count--) {
   142         sh4_execute_instruction();
   143         if( sh4r.pc == target_pc ) {
   144             running = 0;
   145             break;
   146         }
   147     }
   148 }
   150 #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_stop(); RAISE( EXC_ILLEGAL, EXV_ILLEGAL ); }while(0)
   151 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_stop(); return; }while(0)
   153 #define RAISE( x, v ) do{ \
   154     if( sh4r.vbr == 0 ) { \
   155         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   156         sh4_stop(); \
   157     } else { \
   158         sh4r.spc = sh4r.pc + 2; \
   159         sh4r.ssr = sh4_read_sr(); \
   160         sh4r.sgr = sh4r.r[15]; \
   161         MMIO_WRITE(MMU,EXPEVT,x); \
   162         sh4r.pc = sh4r.vbr + v; \
   163         sh4r.new_pc = sh4r.pc + 2; \
   164         sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   165     } \
   166     return; } while(0)
   168 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
   169 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
   170 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
   171 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
   172 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
   173 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
   175 #define MEM_FP_READ( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
   176     ((uint32_t *)FR)[(reg)&0xE0] = sh4_read_long(addr); \
   177     ((uint32_t *)FR)[(reg)|1] = sh4_read_long(addr+4); \
   178 } else ((uint32_t *)FR)[reg] = sh4_read_long(addr)
   180 #define MEM_FP_WRITE( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
   181     sh4_write_long( addr, ((uint32_t *)FR)[(reg)&0xE0] ); \
   182     sh4_write_long( addr+4, ((uint32_t *)FR)[(reg)|1] ); \
   183 } else sh4_write_long( addr, ((uint32_t *)FR)[reg] )
   185 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   187 #define EXC_POWER_RESET  0x000 /* vector special */
   188 #define EXC_MANUAL_RESET 0x020
   189 #define EXC_SLOT_ILLEGAL 0x1A0
   190 #define EXC_ILLEGAL      0x180
   191 #define EXV_ILLEGAL      0x100
   192 #define EXC_TRAP         0x160
   193 #define EXV_TRAP         0x100
   194 #define EXC_FPDISABLE    0x800
   195 #define EXV_FPDISABLE    0x100
   197 #define CHECK( x, c, v ) if( !x ) RAISE( c, v )
   198 #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
   199 #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
   200 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_stop(); return; }
   201 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }
   203 static void sh4_switch_banks( )
   204 {
   205     uint32_t tmp[8];
   207     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   208     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   209     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   210 }
   212 static void sh4_load_sr( uint32_t newval )
   213 {
   214     if( (newval ^ sh4r.sr) & SR_RB )
   215         sh4_switch_banks();
   216     sh4r.sr = newval;
   217     sh4r.t = (newval&SR_T) ? 1 : 0;
   218     sh4r.s = (newval&SR_S) ? 1 : 0;
   219     sh4r.m = (newval&SR_M) ? 1 : 0;
   220     sh4r.q = (newval&SR_Q) ? 1 : 0;
   221     intc_mask_changed();
   222 }
   224 static uint32_t sh4_read_sr( void )
   225 {
   226     /* synchronize sh4r.sr with the various bitflags */
   227     sh4r.sr &= SR_MQSTMASK;
   228     if( sh4r.t ) sh4r.sr |= SR_T;
   229     if( sh4r.s ) sh4r.sr |= SR_S;
   230     if( sh4r.m ) sh4r.sr |= SR_M;
   231     if( sh4r.q ) sh4r.sr |= SR_Q;
   232     return sh4r.sr;
   233 }
   234 /* function for external use */
   235 void sh4_raise_exception( int code, int vector )
   236 {
   237     RAISE(code, vector);
   238 }
   240 static void sh4_accept_interrupt( void )
   241 {
   242     uint32_t code = intc_accept_interrupt();
   243     sh4r.ssr = sh4_read_sr();
   244     sh4r.spc = sh4r.pc;
   245     sh4r.sgr = sh4r.r[15];
   246     sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   247     MMIO_WRITE( MMU, INTEVT, code );
   248     sh4r.pc = sh4r.vbr + 0x600;
   249     sh4r.new_pc = sh4r.pc + 2;
   250     WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   251 }
   253 void sh4_execute_instruction( void )
   254 {
   255     int pc;
   256     unsigned short ir;
   257     uint32_t tmp;
   258     uint64_t tmpl;
   260 #define R0 sh4r.r[0]
   261 #define FR0 (FR[0])
   262 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
   263 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
   264 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
   265 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
   266 #define DISP8(ir) (ir&0x00FF)
   267 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
   268 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
   269 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
   270 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
   271 #define FVN(ir) ((ir&0x0C00)>>8)
   272 #define FVM(ir) ((ir&0x0300)>>6)
   273 #define FRN(ir) (FR[(ir&0x0F00)>>8])
   274 #define FRM(ir) (FR[(ir&0x00F0)>>4])
   275 #define FRNi(ir) (((uint32_t *)FR)[(ir&0x0F00)>>8])
   276 #define FRMi(ir) (((uint32_t *)FR)[(ir&0x00F0)>>4])
   277 #define DRN(ir) (((double *)FR)[(ir&0x0E00)>>9])
   278 #define DRM(ir) (((double *)FR)[(ir&0x00E0)>>5])
   279 #define DRNi(ir) (((uint64_t *)FR)[(ir&0x0E00)>>9])
   280 #define DRMi(ir) (((uint64_t *)FR)[(ir&0x00E0)>>5])
   281 #define FRNn(ir) ((ir&0x0F00)>>8)
   282 #define FRMn(ir) ((ir&0x00F0)>>4)
   283 #define FPULf   *((float *)&sh4r.fpul)
   284 #define FPULi    (sh4r.fpul)
   286     if( SH4_INT_PENDING() ) 
   287         sh4_accept_interrupt();
   289     pc = sh4r.pc;
   290     ir = MEM_READ_WORD(pc);
   291     sh4r.icount++;
   293     switch( (ir&0xF000)>>12 ) {
   294         case 0: /* 0000nnnnmmmmxxxx */
   295             switch( ir&0x000F ) {
   296                 case 2:
   297                     switch( (ir&0x00F0)>>4 ) {
   298                         case 0: /* STC     SR, Rn */
   299                             CHECKPRIV();
   300                             RN(ir) = sh4_read_sr();
   301                             break;
   302                         case 1: /* STC     GBR, Rn */
   303                             RN(ir) = sh4r.gbr;
   304                             break;
   305                         case 2: /* STC     VBR, Rn */
   306                             CHECKPRIV();
   307                             RN(ir) = sh4r.vbr;
   308                             break;
   309                         case 3: /* STC     SSR, Rn */
   310                             CHECKPRIV();
   311                             RN(ir) = sh4r.ssr;
   312                             break;
   313                         case 4: /* STC     SPC, Rn */
   314                             CHECKPRIV();
   315                             RN(ir) = sh4r.spc;
   316                             break;
   317                         case 8: case 9: case 10: case 11: case 12: case 13:
   318                         case 14: case 15:/* STC     Rm_bank, Rn */
   319                             CHECKPRIV();
   320                             RN(ir) = RN_BANK(ir);
   321                             break;
   322                         default: UNDEF(ir);
   323                     }
   324                     break;
   325                 case 3:
   326                     switch( (ir&0x00F0)>>4 ) {
   327                         case 0: /* BSRF    Rn */
   328                             CHECKDEST( pc + 4 + RN(ir) );
   329                             CHECKSLOTILLEGAL();
   330                             sh4r.in_delay_slot = 1;
   331                             sh4r.pr = sh4r.pc + 4;
   332                             sh4r.pc = sh4r.new_pc;
   333                             sh4r.new_pc = pc + 4 + RN(ir);
   334                             return;
   335                         case 2: /* BRAF    Rn */
   336                             CHECKDEST( pc + 4 + RN(ir) );
   337                             CHECKSLOTILLEGAL();
   338                             sh4r.in_delay_slot = 1;
   339                             sh4r.pc = sh4r.new_pc;
   340                             sh4r.new_pc = pc + 4 + RN(ir);
   341                             return;
   342                         case 8: /* PREF    [Rn] */
   343                             tmp = RN(ir);
   344                             if( (tmp & 0xFC000000) == 0xE0000000 ) {
   345                                 /* Store queue operation */
   346                                 int queue = (tmp&0x20)>>2;
   347                                 int32_t *src = &sh4r.store_queue[queue];
   348                                 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
   349                                 uint32_t target = tmp&0x03FFFFE0 | hi;
   350                                 mem_copy_to_sh4( target, src, 32 );
   351                                 WARN( "Executed SQ%c => %08X",
   352                                       (queue == 0 ? '0' : '1'), target );
   353                             }
   354                             break;
   355                         case 9: /* OCBI    [Rn] */
   356                         case 10:/* OCBP    [Rn] */
   357                         case 11:/* OCBWB   [Rn] */
   358                             /* anything? */
   359                             break;
   360                         case 12:/* MOVCA.L R0, [Rn] */
   361                             UNIMP(ir);
   362                         default: UNDEF(ir);
   363                     }
   364                     break;
   365                 case 4: /* MOV.B   Rm, [R0 + Rn] */
   366                     MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
   367                     break;
   368                 case 5: /* MOV.W   Rm, [R0 + Rn] */
   369                     MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
   370                     break;
   371                 case 6: /* MOV.L   Rm, [R0 + Rn] */
   372                     MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
   373                     break;
   374                 case 7: /* MUL.L   Rm, Rn */
   375                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   376                         (RM(ir) * RN(ir));
   377                     break;
   378                 case 8: 
   379                     switch( (ir&0x0FF0)>>4 ) {
   380                         case 0: /* CLRT    */
   381                             sh4r.t = 0;
   382                             break;
   383                         case 1: /* SETT    */
   384                             sh4r.t = 1;
   385                             break;
   386                         case 2: /* CLRMAC  */
   387                             sh4r.mac = 0;
   388                             break;
   389                         case 3: /* LDTLB   */
   390                             break;
   391                         case 4: /* CLRS    */
   392                             sh4r.s = 0;
   393                             break;
   394                         case 5: /* SETS    */
   395                             sh4r.s = 1;
   396                             break;
   397                         default: UNDEF(ir);
   398                     }
   399                     break;
   400                 case 9: 
   401                     if( (ir&0x00F0) == 0x20 ) /* MOVT    Rn */
   402                         RN(ir) = sh4r.t;
   403                     else if( ir == 0x0019 ) /* DIV0U   */
   404                         sh4r.m = sh4r.q = sh4r.t = 0;
   405                     else if( ir == 0x0009 )
   406                         /* NOP     */;
   407                     else UNDEF(ir);
   408                     break;
   409                 case 10:
   410                     switch( (ir&0x00F0) >> 4 ) {
   411                         case 0: /* STS     MACH, Rn */
   412                             RN(ir) = sh4r.mac >> 32;
   413                             break;
   414                         case 1: /* STS     MACL, Rn */
   415                             RN(ir) = (uint32_t)sh4r.mac;
   416                             break;
   417                         case 2: /* STS     PR, Rn */
   418                             RN(ir) = sh4r.pr;
   419                             break;
   420                         case 3: /* STC     SGR, Rn */
   421                             CHECKPRIV();
   422                             RN(ir) = sh4r.sgr;
   423                             break;
   424                         case 5:/* STS      FPUL, Rn */
   425                             RN(ir) = sh4r.fpul;
   426                             break;
   427                         case 6: /* STS     FPSCR, Rn */
   428                             RN(ir) = sh4r.fpscr;
   429                             break;
   430                         case 15:/* STC     DBR, Rn */
   431                             CHECKPRIV();
   432                             RN(ir) = sh4r.dbr;
   433                             break;
   434                         default: UNDEF(ir);
   435                     }
   436                     break;
   437                 case 11:
   438                     switch( (ir&0x0FF0)>>4 ) {
   439                         case 0: /* RTS     */
   440                             CHECKDEST( sh4r.pr );
   441                             CHECKSLOTILLEGAL();
   442                             sh4r.in_delay_slot = 1;
   443                             sh4r.pc = sh4r.new_pc;
   444                             sh4r.new_pc = sh4r.pr;
   445                             return;
   446                         case 1: /* SLEEP   */
   447                             running = 0;
   448                             break;
   449                         case 2: /* RTE     */
   450                             CHECKPRIV();
   451                             CHECKDEST( sh4r.spc );
   452                             CHECKSLOTILLEGAL();
   453                             sh4r.in_delay_slot = 1;
   454                             sh4r.pc = sh4r.new_pc;
   455                             sh4r.new_pc = sh4r.spc;
   456                             sh4_load_sr( sh4r.ssr );
   457                             WARN( "RTE => %08X", sh4r.new_pc );
   458                             return;
   459                         default:UNDEF(ir);
   460                     }
   461                     break;
   462                 case 12:/* MOV.B   [R0+R%d], R%d */
   463                     RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
   464                     break;
   465                 case 13:/* MOV.W   [R0+R%d], R%d */
   466                     RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
   467                     break;
   468                 case 14:/* MOV.L   [R0+R%d], R%d */
   469                     RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
   470                     break;
   471                 case 15:/* MAC.L   [Rm++], [Rn++] */
   472                     tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
   473                                   SIGNEXT32(MEM_READ_LONG(RN(ir))) );
   474                     if( sh4r.s ) {
   475                         /* 48-bit Saturation. Yuch */
   476                         tmpl += SIGNEXT48(sh4r.mac);
   477                         if( tmpl < 0xFFFF800000000000LL )
   478                             tmpl = 0xFFFF800000000000LL;
   479                         else if( tmpl > 0x00007FFFFFFFFFFFLL )
   480                             tmpl = 0x00007FFFFFFFFFFFLL;
   481                         sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
   482                             (tmpl&0x0000FFFFFFFFFFFFLL);
   483                     } else sh4r.mac = tmpl;
   485                     RM(ir) += 4;
   486                     RN(ir) += 4;
   488                     break;
   489                 default: UNDEF(ir);
   490             }
   491             break;
   492         case 1: /* 0001nnnnmmmmdddd */
   493             /* MOV.L   Rm, [Rn + disp4*4] */
   494             MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) );
   495             break;
   496         case 2: /* 0010nnnnmmmmxxxx */
   497             switch( ir&0x000F ) {
   498                 case 0: /* MOV.B   Rm, [Rn] */
   499                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   500                     break;
   501                 case 1: /* MOV.W   Rm, [Rn] */
   502                     MEM_WRITE_WORD( RN(ir), RM(ir) );
   503                     break;
   504                 case 2: /* MOV.L   Rm, [Rn] */
   505                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   506                     break;
   507                 case 3: UNDEF(ir);
   508                     break;
   509                 case 4: /* MOV.B   Rm, [--Rn] */
   510                     RN(ir) --;
   511                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   512                     break;
   513                 case 5: /* MOV.W   Rm, [--Rn] */
   514                     RN(ir) -= 2;
   515                     MEM_WRITE_WORD( RN(ir), RM(ir) );
   516                     break;
   517                 case 6: /* MOV.L   Rm, [--Rn] */
   518                     RN(ir) -= 4;
   519                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   520                     break;
   521                 case 7: /* DIV0S   Rm, Rn */
   522                     sh4r.q = RN(ir)>>31;
   523                     sh4r.m = RM(ir)>>31;
   524                     sh4r.t = sh4r.q ^ sh4r.m;
   525                     break;
   526                 case 8: /* TST     Rm, Rn */
   527                     sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
   528                     break;
   529                 case 9: /* AND     Rm, Rn */
   530                     RN(ir) &= RM(ir);
   531                     break;
   532                 case 10:/* XOR     Rm, Rn */
   533                     RN(ir) ^= RM(ir);
   534                     break;
   535                 case 11:/* OR      Rm, Rn */
   536                     RN(ir) |= RM(ir);
   537                     break;
   538                 case 12:/* CMP/STR Rm, Rn */
   539                     /* set T = 1 if any byte in RM & RN is the same */
   540                     tmp = RM(ir) ^ RN(ir);
   541                     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   542                               (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   543                     break;
   544                 case 13:/* XTRCT   Rm, Rn */
   545                     RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
   546                     break;
   547                 case 14:/* MULU.W  Rm, Rn */
   548                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   549                         (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
   550                     break;
   551                 case 15:/* MULS.W  Rm, Rn */
   552                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   553                         (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
   554                     break;
   555             }
   556             break;
   557         case 3: /* 0011nnnnmmmmxxxx */
   558             switch( ir&0x000F ) {
   559                 case 0: /* CMP/EQ  Rm, Rn */
   560                     sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
   561                     break;
   562                 case 2: /* CMP/HS  Rm, Rn */
   563                     sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
   564                     break;
   565                 case 3: /* CMP/GE  Rm, Rn */
   566                     sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
   567                     break;
   568                 case 4: { /* DIV1    Rm, Rn */
   569                     /* This is just from the sh4p manual with some
   570                      * simplifications (someone want to check it's correct? :)
   571                      * Why they couldn't just provide a real DIV instruction...
   572                      * Please oh please let the translator batch these things
   573                      * up into a single DIV... */
   574                     uint32_t tmp0, tmp1, tmp2, dir;
   576                     dir = sh4r.q ^ sh4r.m;
   577                     sh4r.q = (RN(ir) >> 31);
   578                     tmp2 = RM(ir);
   579                     RN(ir) = (RN(ir) << 1) | sh4r.t;
   580                     tmp0 = RN(ir);
   581                     if( dir ) {
   582                         RN(ir) += tmp2;
   583                         tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
   584                     } else {
   585                         RN(ir) -= tmp2;
   586                         tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
   587                     }
   588                     sh4r.q ^= sh4r.m ^ tmp1;
   589                     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   590                     break; }
   591                 case 5: /* DMULU.L Rm, Rn */
   592                     sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
   593                     break;
   594                 case 6: /* CMP/HI  Rm, Rn */
   595                     sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
   596                     break;
   597                 case 7: /* CMP/GT  Rm, Rn */
   598                     sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
   599                     break;
   600                 case 8: /* SUB     Rm, Rn */
   601                     RN(ir) -= RM(ir);
   602                     break;
   603                 case 10:/* SUBC    Rm, Rn */
   604                     tmp = RN(ir);
   605                     RN(ir) = RN(ir) - RM(ir) - sh4r.t;
   606                     sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
   607                     break;
   608                 case 11:/* SUBV    Rm, Rn */
   609                     UNIMP(ir);
   610                     break;
   611                 case 12:/* ADD     Rm, Rn */
   612                     RN(ir) += RM(ir);
   613                     break;
   614                 case 13:/* DMULS.L Rm, Rn */
   615                     sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
   616                     break;
   617                 case 14:/* ADDC    Rm, Rn */
   618                     tmp = RN(ir);
   619                     RN(ir) += RM(ir) + sh4r.t;
   620                     sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
   621                     break;
   622                 case 15:/* ADDV    Rm, Rn */
   623                     UNIMP(ir);
   624                     break;
   625                 default: UNDEF(ir);
   626             }
   627             break;
   628         case 4: /* 0100nnnnxxxxxxxx */
   629             switch( ir&0x00FF ) {
   630                 case 0x00: /* SHLL    Rn */
   631                     sh4r.t = RN(ir) >> 31;
   632                     RN(ir) <<= 1;
   633                     break;
   634                 case 0x01: /* SHLR    Rn */
   635                     sh4r.t = RN(ir) & 0x00000001;
   636                     RN(ir) >>= 1;
   637                     break;
   638                 case 0x02: /* STS.L   MACH, [--Rn] */
   639                     RN(ir) -= 4;
   640                     MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
   641                     break;
   642                 case 0x03: /* STC.L   SR, [--Rn] */
   643                     CHECKPRIV();
   644                     RN(ir) -= 4;
   645                     MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
   646                     break;
   647                 case 0x04: /* ROTL    Rn */
   648                     sh4r.t = RN(ir) >> 31;
   649                     RN(ir) <<= 1;
   650                     RN(ir) |= sh4r.t;
   651                     break;
   652                 case 0x05: /* ROTR    Rn */
   653                     sh4r.t = RN(ir) & 0x00000001;
   654                     RN(ir) >>= 1;
   655                     RN(ir) |= (sh4r.t << 31);
   656                     break;
   657                 case 0x06: /* LDS.L   [Rn++], MACH */
   658                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   659                         (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
   660                     RN(ir) += 4;
   661                     break;
   662                 case 0x07: /* LDC.L   [Rn++], SR */
   663                     CHECKPRIV();
   664                     sh4_load_sr( MEM_READ_LONG(RN(ir)) );
   665                     RN(ir) +=4;
   666                     break;
   667                 case 0x08: /* SHLL2   Rn */
   668                     RN(ir) <<= 2;
   669                     break;
   670                 case 0x09: /* SHLR2   Rn */
   671                     RN(ir) >>= 2;
   672                     break;
   673                 case 0x0A: /* LDS     Rn, MACH */
   674                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   675                         (((uint64_t)RN(ir))<<32);
   676                     break;
   677                 case 0x0B: /* JSR     [Rn] */
   678                     CHECKDEST( RN(ir) );
   679                     CHECKSLOTILLEGAL();
   680                     sh4r.in_delay_slot = 1;
   681                     sh4r.pc = sh4r.new_pc;
   682                     sh4r.new_pc = RN(ir);
   683                     sh4r.pr = pc + 4;
   684                     return;
   685                 case 0x0E: /* LDC     Rn, SR */
   686                     CHECKPRIV();
   687                     sh4_load_sr( RN(ir) );
   688                     break;
   689                 case 0x10: /* DT      Rn */
   690                     RN(ir) --;
   691                     sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
   692                     break;
   693                 case 0x11: /* CMP/PZ  Rn */
   694                     sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
   695                     break;
   696                 case 0x12: /* STS.L   MACL, [--Rn] */
   697                     RN(ir) -= 4;
   698                     MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
   699                     break;
   700                 case 0x13: /* STC.L   GBR, [--Rn] */
   701                     RN(ir) -= 4;
   702                     MEM_WRITE_LONG( RN(ir), sh4r.gbr );
   703                     break;
   704                 case 0x15: /* CMP/PL  Rn */
   705                     sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
   706                     break;
   707                 case 0x16: /* LDS.L   [Rn++], MACL */
   708                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   709                         (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
   710                     RN(ir) += 4;
   711                     break;
   712                 case 0x17: /* LDC.L   [Rn++], GBR */
   713                     sh4r.gbr = MEM_READ_LONG(RN(ir));
   714                     RN(ir) +=4;
   715                     break;
   716                 case 0x18: /* SHLL8   Rn */
   717                     RN(ir) <<= 8;
   718                     break;
   719                 case 0x19: /* SHLR8   Rn */
   720                     RN(ir) >>= 8;
   721                     break;
   722                 case 0x1A: /* LDS     Rn, MACL */
   723                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   724                         (uint64_t)((uint32_t)(RN(ir)));
   725                     break;
   726                 case 0x1B: /* TAS.B   [Rn] */
   727                     tmp = MEM_READ_BYTE( RN(ir) );
   728                     sh4r.t = ( tmp == 0 ? 1 : 0 );
   729                     MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
   730                     break;
   731                 case 0x1E: /* LDC     Rn, GBR */
   732                     sh4r.gbr = RN(ir);
   733                     break;
   734                 case 0x20: /* SHAL    Rn */
   735                     sh4r.t = RN(ir) >> 31;
   736                     RN(ir) <<= 1;
   737                     break;
   738                 case 0x21: /* SHAR    Rn */
   739                     sh4r.t = RN(ir) & 0x00000001;
   740                     RN(ir) = ((int32_t)RN(ir)) >> 1;
   741                     break;
   742                 case 0x22: /* STS.L   PR, [--Rn] */
   743                     RN(ir) -= 4;
   744                     MEM_WRITE_LONG( RN(ir), sh4r.pr );
   745                     break;
   746                 case 0x23: /* STC.L   VBR, [--Rn] */
   747                     CHECKPRIV();
   748                     RN(ir) -= 4;
   749                     MEM_WRITE_LONG( RN(ir), sh4r.vbr );
   750                     break;
   751                 case 0x24: /* ROTCL   Rn */
   752                     tmp = RN(ir) >> 31;
   753                     RN(ir) <<= 1;
   754                     RN(ir) |= sh4r.t;
   755                     sh4r.t = tmp;
   756                     break;
   757                 case 0x25: /* ROTCR   Rn */
   758                     tmp = RN(ir) & 0x00000001;
   759                     RN(ir) >>= 1;
   760                     RN(ir) |= (sh4r.t << 31 );
   761                     sh4r.t = tmp;
   762                     break;
   763                 case 0x26: /* LDS.L   [Rn++], PR */
   764                     sh4r.pr = MEM_READ_LONG( RN(ir) );
   765                     RN(ir) += 4;
   766                     break;
   767                 case 0x27: /* LDC.L   [Rn++], VBR */
   768                     CHECKPRIV();
   769                     sh4r.vbr = MEM_READ_LONG(RN(ir));
   770                     RN(ir) +=4;
   771                     break;
   772                 case 0x28: /* SHLL16  Rn */
   773                     RN(ir) <<= 16;
   774                     break;
   775                 case 0x29: /* SHLR16  Rn */
   776                     RN(ir) >>= 16;
   777                     break;
   778                 case 0x2A: /* LDS     Rn, PR */
   779                     sh4r.pr = RN(ir);
   780                     break;
   781                 case 0x2B: /* JMP     [Rn] */
   782                     CHECKDEST( RN(ir) );
   783                     CHECKSLOTILLEGAL();
   784                     sh4r.in_delay_slot = 1;
   785                     sh4r.pc = sh4r.new_pc;
   786                     sh4r.new_pc = RN(ir);
   787                     return;
   788                 case 0x2E: /* LDC     Rn, VBR */
   789                     CHECKPRIV();
   790                     sh4r.vbr = RN(ir);
   791                     break;
   792                 case 0x32: /* STC.L   SGR, [--Rn] */
   793                     CHECKPRIV();
   794                     RN(ir) -= 4;
   795                     MEM_WRITE_LONG( RN(ir), sh4r.sgr );
   796                     break;
   797                 case 0x33: /* STC.L   SSR, [--Rn] */
   798                     CHECKPRIV();
   799                     RN(ir) -= 4;
   800                     MEM_WRITE_LONG( RN(ir), sh4r.ssr );
   801                     break;
   802                 case 0x37: /* LDC.L   [Rn++], SSR */
   803                     CHECKPRIV();
   804                     sh4r.ssr = MEM_READ_LONG(RN(ir));
   805                     RN(ir) +=4;
   806                     break;
   807                 case 0x3E: /* LDC     Rn, SSR */
   808                     CHECKPRIV();
   809                     sh4r.ssr = RN(ir);
   810                     break;
   811                 case 0x43: /* STC.L   SPC, [--Rn] */
   812                     CHECKPRIV();
   813                     RN(ir) -= 4;
   814                     MEM_WRITE_LONG( RN(ir), sh4r.spc );
   815                     break;
   816                 case 0x47: /* LDC.L   [Rn++], SPC */
   817                     CHECKPRIV();
   818                     sh4r.spc = MEM_READ_LONG(RN(ir));
   819                     RN(ir) +=4;
   820                     break;
   821                 case 0x4E: /* LDC     Rn, SPC */
   822                     CHECKPRIV();
   823                     sh4r.spc = RN(ir);
   824                     break;
   825                 case 0x52: /* STS.L   FPUL, [--Rn] */
   826                     RN(ir) -= 4;
   827                     MEM_WRITE_LONG( RN(ir), sh4r.fpul );
   828                     break;
   829                 case 0x56: /* LDS.L   [Rn++], FPUL */
   830                     sh4r.fpul = MEM_READ_LONG(RN(ir));
   831                     RN(ir) +=4;
   832                     break;
   833                 case 0x5A: /* LDS     Rn, FPUL */
   834                     sh4r.fpul = RN(ir);
   835                     break;
   836                 case 0x62: /* STS.L   FPSCR, [--Rn] */
   837                     RN(ir) -= 4;
   838                     MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
   839                     break;
   840                 case 0x66: /* LDS.L   [Rn++], FPSCR */
   841                     sh4r.fpscr = MEM_READ_LONG(RN(ir));
   842                     RN(ir) +=4;
   843                     break;
   844                 case 0x6A: /* LDS     Rn, FPSCR */
   845                     sh4r.fpscr = RN(ir);
   846                     break;
   847                 case 0xF2: /* STC.L   DBR, [--Rn] */
   848                     CHECKPRIV();
   849                     RN(ir) -= 4;
   850                     MEM_WRITE_LONG( RN(ir), sh4r.dbr );
   851                     break;
   852                 case 0xF6: /* LDC.L   [Rn++], DBR */
   853                     CHECKPRIV();
   854                     sh4r.dbr = MEM_READ_LONG(RN(ir));
   855                     RN(ir) +=4;
   856                     break;
   857                 case 0xFA: /* LDC     Rn, DBR */
   858                     CHECKPRIV();
   859                     sh4r.dbr = RN(ir);
   860                     break;
   861                 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
   862                 case 0xD3: case 0xE3: case 0xF3: /* STC.L   Rn_BANK, [--Rn] */
   863                     CHECKPRIV();
   864                     RN(ir) -= 4;
   865                     MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
   866                     break;
   867                 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
   868                 case 0xD7: case 0xE7: case 0xF7: /* LDC.L   [Rn++], Rn_BANK */
   869                     CHECKPRIV();
   870                     RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
   871                     RN(ir) += 4;
   872                     break;
   873                 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
   874                 case 0xDE: case 0xEE: case 0xFE: /* LDC     Rm, Rn_BANK */
   875                     CHECKPRIV();
   876                     RN_BANK(ir) = RM(ir);
   877                     break;
   878                 default:
   879                     if( (ir&0x000F) == 0x0F ) {
   880                         /* MAC.W   [Rm++], [Rn++] */
   881                         tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
   882                             SIGNEXT16(MEM_READ_WORD(RN(ir)));
   883                         if( sh4r.s ) {
   884                             /* FIXME */
   885                             UNIMP(ir);
   886                         } else sh4r.mac += SIGNEXT32(tmp);
   887                         RM(ir) += 2;
   888                         RN(ir) += 2;
   889                     } else if( (ir&0x000F) == 0x0C ) {
   890                         /* SHAD    Rm, Rn */
   891                         tmp = RM(ir);
   892                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
   893                         else if( (tmp & 0x1F) == 0 )  
   894 			  RN(ir) = ((int32_t)RN(ir)) >> 31;
   895                         else 
   896 			  RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
   897                     } else if( (ir&0x000F) == 0x0D ) {
   898                         /* SHLD    Rm, Rn */
   899                         tmp = RM(ir);
   900                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
   901                         else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
   902                         else RN(ir) >>= (((~tmp) & 0x1F)+1);
   903                     } else UNDEF(ir);
   904             }
   905             break;
   906         case 5: /* 0101nnnnmmmmdddd */
   907             /* MOV.L   [Rm + disp4*4], Rn */
   908             RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) );
   909             break;
   910         case 6: /* 0110xxxxxxxxxxxx */
   911             switch( ir&0x000f ) {
   912                 case 0: /* MOV.B   [Rm], Rn */
   913                     RN(ir) = MEM_READ_BYTE( RM(ir) );
   914                     break;
   915                 case 1: /* MOV.W   [Rm], Rn */
   916                     RN(ir) = MEM_READ_WORD( RM(ir) );
   917                     break;
   918                 case 2: /* MOV.L   [Rm], Rn */
   919                     RN(ir) = MEM_READ_LONG( RM(ir) );
   920                     break;
   921                 case 3: /* MOV     Rm, Rn */
   922                     RN(ir) = RM(ir);
   923                     break;
   924                 case 4: /* MOV.B   [Rm++], Rn */
   925                     RN(ir) = MEM_READ_BYTE( RM(ir) );
   926                     RM(ir) ++;
   927                     break;
   928                 case 5: /* MOV.W   [Rm++], Rn */
   929                     RN(ir) = MEM_READ_WORD( RM(ir) );
   930                     RM(ir) += 2;
   931                     break;
   932                 case 6: /* MOV.L   [Rm++], Rn */
   933                     RN(ir) = MEM_READ_LONG( RM(ir) );
   934                     RM(ir) += 4;
   935                     break;
   936                 case 7: /* NOT     Rm, Rn */
   937                     RN(ir) = ~RM(ir);
   938                     break;
   939                 case 8: /* SWAP.B  Rm, Rn */
   940                     RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
   941                         ((RM(ir)&0x000000FF)<<8);
   942                     break;
   943                 case 9: /* SWAP.W  Rm, Rn */
   944                     RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
   945                     break;
   946                 case 10:/* NEGC    Rm, Rn */
   947                     tmp = 0 - RM(ir);
   948                     RN(ir) = tmp - sh4r.t;
   949                     sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
   950                     break;
   951                 case 11:/* NEG     Rm, Rn */
   952                     RN(ir) = 0 - RM(ir);
   953                     break;
   954                 case 12:/* EXTU.B  Rm, Rn */
   955                     RN(ir) = RM(ir)&0x000000FF;
   956                     break;
   957                 case 13:/* EXTU.W  Rm, Rn */
   958                     RN(ir) = RM(ir)&0x0000FFFF;
   959                     break;
   960                 case 14:/* EXTS.B  Rm, Rn */
   961                     RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
   962                     break;
   963                 case 15:/* EXTS.W  Rm, Rn */
   964                     RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
   965                     break;
   966             }
   967             break;
   968         case 7: /* 0111nnnniiiiiiii */
   969             /* ADD    imm8, Rn */
   970             RN(ir) += IMM8(ir);
   971             break;
   972         case 8: /* 1000xxxxxxxxxxxx */
   973             switch( (ir&0x0F00) >> 8 ) {
   974                 case 0: /* MOV.B   R0, [Rm + disp4] */
   975                     MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
   976                     break;
   977                 case 1: /* MOV.W   R0, [Rm + disp4*2] */
   978                     MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 );
   979                     break;
   980                 case 4: /* MOV.B   [Rm + disp4], R0 */
   981                     R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
   982                     break;
   983                 case 5: /* MOV.W   [Rm + disp4*2], R0 */
   984                     R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) );
   985                     break;
   986                 case 8: /* CMP/EQ  imm, R0 */
   987                     sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
   988                     break;
   989                 case 9: /* BT      disp8 */
   990                     CHECKSLOTILLEGAL()
   991                     if( sh4r.t ) {
   992                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
   993                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
   994                         sh4r.new_pc = sh4r.pc + 2;
   995                         return;
   996                     }
   997                     break;
   998                 case 11:/* BF      disp8 */
   999                     CHECKSLOTILLEGAL()
  1000                     if( !sh4r.t ) {
  1001                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1002                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
  1003                         sh4r.new_pc = sh4r.pc + 2;
  1004                         return;
  1006                     break;
  1007                 case 13:/* BT/S    disp8 */
  1008                     CHECKSLOTILLEGAL()
  1009                     if( sh4r.t ) {
  1010                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1011                         sh4r.in_delay_slot = 1;
  1012                         sh4r.pc = sh4r.new_pc;
  1013                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
  1014                         sh4r.in_delay_slot = 1;
  1015                         return;
  1017                     break;
  1018                 case 15:/* BF/S    disp8 */
  1019                     CHECKSLOTILLEGAL()
  1020                     if( !sh4r.t ) {
  1021                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1022                         sh4r.in_delay_slot = 1;
  1023                         sh4r.pc = sh4r.new_pc;
  1024                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
  1025                         return;
  1027                     break;
  1028                 default: UNDEF(ir);
  1030             break;
  1031         case 9: /* 1001xxxxxxxxxxxx */
  1032             /* MOV.W   [disp8*2 + pc + 4], Rn */
  1033             RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) );
  1034             break;
  1035         case 10:/* 1010dddddddddddd */
  1036             /* BRA     disp12 */
  1037             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
  1038             CHECKSLOTILLEGAL()
  1039             sh4r.in_delay_slot = 1;
  1040             sh4r.pc = sh4r.new_pc;
  1041             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
  1042             return;
  1043         case 11:/* 1011dddddddddddd */
  1044             /* BSR     disp12 */
  1045             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
  1046             CHECKSLOTILLEGAL()
  1047             sh4r.in_delay_slot = 1;
  1048             sh4r.pr = pc + 4;
  1049             sh4r.pc = sh4r.new_pc;
  1050             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
  1051             return;
  1052         case 12:/* 1100xxxxdddddddd */
  1053         switch( (ir&0x0F00)>>8 ) {
  1054                 case 0: /* MOV.B  R0, [GBR + disp8] */
  1055                     MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
  1056                     break;
  1057                 case 1: /* MOV.W  R0, [GBR + disp8*2] */
  1058                     MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 );
  1059                     break;
  1060                 case  2: /*MOV.L   R0, [GBR + disp8*4] */
  1061                     MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 );
  1062                     break;
  1063                 case 3: /* TRAPA   imm8 */
  1064                     CHECKSLOTILLEGAL()
  1065                     sh4r.in_delay_slot = 1;
  1066                     MMIO_WRITE( MMU, TRA, UIMM8(ir) );
  1067                     sh4r.pc = sh4r.new_pc;  /* RAISE ends the instruction */
  1068                     sh4r.new_pc += 2;
  1069                     RAISE( EXC_TRAP, EXV_TRAP );
  1070                     break;
  1071                 case 4: /* MOV.B   [GBR + disp8], R0 */
  1072                     R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
  1073                     break;
  1074                 case 5: /* MOV.W   [GBR + disp8*2], R0 */
  1075                     R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) );
  1076                     break;
  1077                 case 6: /* MOV.L   [GBR + disp8*4], R0 */
  1078                     R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) );
  1079                     break;
  1080                 case 7: /* MOVA    disp8 + pc&~3 + 4, R0 */
  1081                     R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
  1082                     break;
  1083                 case 8: /* TST     imm8, R0 */
  1084                     sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
  1085                     break;
  1086                 case 9: /* AND     imm8, R0 */
  1087                     R0 &= UIMM8(ir);
  1088                     break;
  1089                 case 10:/* XOR     imm8, R0 */
  1090                     R0 ^= UIMM8(ir);
  1091                     break;
  1092                 case 11:/* OR      imm8, R0 */
  1093                     R0 |= UIMM8(ir);
  1094                     break;
  1095                 case 12:/* TST.B   imm8, [R0+GBR] */
  1096                     sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
  1097                     break;
  1098                 case 13:/* AND.B   imm8, [R0+GBR] */
  1099                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1100                                     UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
  1101                     break;
  1102                 case 14:/* XOR.B   imm8, [R0+GBR] */
  1103                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1104                                     UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
  1105                     break;
  1106                 case 15:/* OR.B    imm8, [R0+GBR] */
  1107                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1108                                     UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
  1109                     break;
  1111             break;
  1112         case 13:/* 1101nnnndddddddd */
  1113             /* MOV.L   [disp8*4 + pc&~3 + 4], Rn */
  1114             RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 );
  1115             break;
  1116         case 14:/* 1110nnnniiiiiiii */
  1117             /* MOV     imm8, Rn */
  1118             RN(ir) = IMM8(ir);
  1119             break;
  1120         case 15:/* 1111xxxxxxxxxxxx */
  1121             CHECKFPUEN();
  1122             switch( ir&0x000F ) {
  1123                 case 0: /* FADD    FRm, FRn */
  1124                     FRN(ir) += FRM(ir);
  1125                     break;
  1126                 case 1: /* FSUB    FRm, FRn */
  1127                     FRN(ir) -= FRM(ir);
  1128                     break;
  1129                 case 2: /* FMUL    FRm, FRn */
  1130                     FRN(ir) = FRN(ir) * FRM(ir);
  1131                     break;
  1132                 case 3: /* FDIV    FRm, FRn */
  1133                     FRN(ir) = FRN(ir) / FRM(ir);
  1134                     break;
  1135                 case 4: /* FCMP/EQ FRm, FRn */
  1136                     sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
  1137                     break;
  1138                 case 5: /* FCMP/GT FRm, FRn */
  1139                     sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
  1140                     break;
  1141                 case 6: /* FMOV.S  [Rm+R0], FRn */
  1142                     MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
  1143                     break;
  1144                 case 7: /* FMOV.S  FRm, [Rn+R0] */
  1145                     MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
  1146                     break;
  1147                 case 8: /* FMOV.S  [Rm], FRn */
  1148                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1149                     break;
  1150                 case 9: /* FMOV.S  [Rm++], FRn */
  1151                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1152                     RM(ir) += FP_WIDTH;
  1153                     break;
  1154                 case 10:/* FMOV.S  FRm, [Rn] */
  1155                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1156                     break;
  1157                 case 11:/* FMOV.S  FRm, [--Rn] */
  1158                     RN(ir) -= FP_WIDTH;
  1159                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1160                     break;
  1161                 case 12:/* FMOV    FRm, FRn */
  1162                     if( IS_FPU_DOUBLESIZE() ) {
  1163                         DRN(ir) = DRM(ir);
  1164                     } else {
  1165                         FRN(ir) = FRM(ir);
  1167                     break;
  1168                 case 13:
  1169                     switch( (ir&0x00F0) >> 4 ) {
  1170                         case 0: /* FSTS    FPUL, FRn */
  1171                             FRN(ir) = FPULf;
  1172                             break;
  1173                         case 1: /* FLDS    FRn, FPUL */
  1174                             FPULf = FRN(ir);
  1175                             break;
  1176                         case 2: /* FLOAT   FPUL, FRn */
  1177                             FRN(ir) = (float)FPULi;
  1178                             break;
  1179                         case 3: /* FTRC    FRn, FPUL */
  1180                             FPULi = (uint32_t)FRN(ir);
  1181                             /* FIXME: is this sufficient? */
  1182                             break;
  1183                         case 4: /* FNEG    FRn */
  1184                             FRN(ir) = -FRN(ir);
  1185                             break;
  1186                         case 5: /* FABS    FRn */
  1187                             FRN(ir) = fabsf(FRN(ir));
  1188                             break;
  1189                         case 6: /* FSQRT   FRn */
  1190                             FRN(ir) = sqrtf(FRN(ir));
  1191                             break;
  1192                         case 7: /* FSRRA FRn */
  1193                             FRN(ir) = 1.0/sqrtf(FRN(ir));
  1194                             break;
  1195                         case 8: /* FLDI0   FRn */
  1196                             FRN(ir) = 0.0;
  1197                             break;
  1198                         case 9: /* FLDI1   FRn */
  1199                             FRN(ir) = 1.0;
  1200                             break;
  1201                         case 10: /* FCNVSD FPUL, DRn */
  1202                             if( IS_FPU_DOUBLEPREC() )
  1203                                 DRN(ir) = (double)FPULf;
  1204                             else UNDEF(ir);
  1205                             break;
  1206                         case 11: /* FCNVDS DRn, FPUL */
  1207                             if( IS_FPU_DOUBLEPREC() ) 
  1208                                 FPULf = (float)DRN(ir);
  1209                             else UNDEF(ir);
  1210                             break;
  1211                         case 14:/* FIPR    FVm, FVn */
  1212                             /* FIXME: This is not going to be entirely accurate
  1213                              * as the SH4 instruction is less precise. Also
  1214                              * need to check for 0s and infinities.
  1215                              */
  1217                             float *fr_bank = FR;
  1218                             int tmp2 = FVN(ir);
  1219                             tmp = FVM(ir);
  1220                             fr_bank[tmp2+3] = fr_bank[tmp]*fr_bank[tmp2] +
  1221                                 fr_bank[tmp+1]*fr_bank[tmp2+1] +
  1222                                 fr_bank[tmp+2]*fr_bank[tmp2+2] +
  1223                                 fr_bank[tmp+3]*fr_bank[tmp2+3];
  1224                             break;
  1226                         case 15:
  1227                             if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
  1228                                 float *fvout = FR+FVN(ir);
  1229                                 float *xm = XF;
  1230                                 float fv[4] = { fvout[0], fvout[1], fvout[2], fvout[3] };
  1231                                 fvout[0] = xm[0] * fv[0] + xm[4]*fv[1] +
  1232                                     xm[8]*fv[2] + xm[12]*fv[3];
  1233                                 fvout[1] = xm[1] * fv[0] + xm[5]*fv[1] +
  1234                                     xm[9]*fv[2] + xm[13]*fv[3];
  1235                                 fvout[2] = xm[2] * fv[0] + xm[6]*fv[1] +
  1236                                     xm[10]*fv[2] + xm[14]*fv[3];
  1237                                 fvout[3] = xm[3] * fv[0] + xm[7]*fv[1] +
  1238                                     xm[11]*fv[2] + xm[15]*fv[3];
  1239                                 break;
  1241                             else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */
  1242                                 float angle = (((float)(short)(FPULi>>16)) +
  1243                                                ((float)(FPULi&16)/65536.0)) *
  1244                                     2 * M_PI;
  1245                                 int reg = FRNn(ir);
  1246                                 FR[reg] = sinf(angle);
  1247                                 FR[reg+1] = cosf(angle);
  1248                                 break;
  1250                             else if( ir == 0xFBFD ) {
  1251                                 /* FRCHG   */
  1252                                 sh4r.fpscr ^= FPSCR_FR;
  1253                                 break;
  1255                             else if( ir == 0xF3FD ) {
  1256                                 /* FSCHG   */
  1257                                 sh4r.fpscr ^= FPSCR_SZ;
  1258                                 break;
  1260                         default: UNDEF(ir);
  1262                     break;
  1263                 case 14:/* FMAC    FR0, FRm, FRn */
  1264                     FRN(ir) += FRM(ir)*FR0;
  1265                     break;
  1266                 default: UNDEF(ir);
  1268             break;
  1270     sh4r.pc = sh4r.new_pc;
  1271     sh4r.new_pc += 2;
  1272     sh4r.in_delay_slot = 0;
.