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lxdream.org :: lxdream/src/sh4/sh4core.h
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.h
changeset 23:1ec3acd0594d
prev10:c898b37506e0
next27:1ef09a52cd1e
author nkeynes
date Fri Dec 23 11:44:55 2005 +0000 (15 years ago)
permissions -rw-r--r--
last change Start of "real" time slices, general structure in place now
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     1 /**
     2  * $Id: sh4core.h,v 1.4 2005-12-23 11:44:55 nkeynes Exp $
     3  * 
     4  * This file defines the public functions exported by the SH4 core, except
     5  * for disassembly functions defined in sh4dasm.h
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    19 #ifndef sh4core_H
    20 #define sh4core_H 1
    22 #include <stdint.h>
    23 #include <stdio.h>
    25 #ifdef __cplusplus
    26 extern "C" {
    27 #if 0
    28 }
    29 #endif
    30 #endif
    32 struct sh4_registers {
    33     uint32_t r[16];
    34     uint32_t r_bank[8]; /* hidden banked registers */
    35     uint32_t sr, gbr, ssr, spc, sgr, dbr, vbr;
    36     uint32_t pr, pc, fpul, fpscr;
    37     uint64_t mac;
    38     uint32_t m, q, s, t; /* really boolean - 0 or 1 */
    39     float fr[2][16];
    41     int32_t store_queue[16]; /* technically 2 banks of 32 bytes */
    43     uint32_t new_pc; /* Not a real register, but used to handle delay slots */
    44     uint32_t icount; /* Also not a real register, instruction counter */
    45     uint32_t int_pending; /* flag set by the INTC = pending priority level */
    46     int in_delay_slot; /* flag to indicate the current instruction is in
    47                              * a delay slot (certain rules apply) */
    48 };
    50 extern struct sh4_registers sh4r;
    52 /* Public functions */
    54 void sh4_init( void );
    55 void sh4_reset( void );
    56 void sh4_run( void );
    57 void sh4_runto( uint32_t pc, uint32_t count );
    58 void sh4_runfor( uint32_t count );
    59 int sh4_isrunning( void );
    60 void sh4_stop( void );
    61 void sh4_set_pc( int );
    62 void sh4_execute_instruction( void );
    63 void sh4_raise_exception( int, int );
    64 void sh4_set_breakpoint( uint32_t pc, int type );
    66 #define BREAK_ONESHOT 1
    67 #define BREAK_PERM 2
    69 /* SH4 Memory */
    70 int32_t sh4_read_long( uint32_t addr );
    71 int32_t sh4_read_word( uint32_t addr );
    72 int32_t sh4_read_byte( uint32_t addr );
    73 void sh4_write_long( uint32_t addr, uint32_t val );
    74 void sh4_write_word( uint32_t addr, uint32_t val );
    75 void sh4_write_byte( uint32_t addr, uint32_t val );
    76 int32_t sh4_read_phys_word( uint32_t addr );
    78 /* Peripheral functions */
    79 void DMAC_run_slice( int );
    80 void TMU_run_slice( int );
    81 void SCIF_run_slice( int );
    82 void SCIF_save_state( FILE *f );
    83 int SCIF_load_state( FILE *f );
    85 #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
    86 #define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
    87 #define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20)
    88 #define SIGNEXT16(n) ((int32_t)((int16_t)(n)))
    89 #define SIGNEXT32(n) ((int64_t)((int32_t)(n)))
    90 #define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16)
    92 /* Status Register (SR) bits */
    93 #define SR_MD    0x40000000 /* Processor mode ( User=0, Privileged=1 ) */ 
    94 #define SR_RB    0x20000000 /* Register bank (priviledged mode only) */
    95 #define SR_BL    0x10000000 /* Exception/interupt block (1 = masked) */
    96 #define SR_FD    0x00008000 /* FPU disable */
    97 #define SR_M     0x00000200
    98 #define SR_Q     0x00000100
    99 #define SR_IMASK 0x000000F0 /* Interrupt mask level */
   100 #define SR_S     0x00000002 /* Saturation operation for MAC instructions */
   101 #define SR_T     0x00000001 /* True/false or carry/borrow */
   102 #define SR_MASK  0x700083F3
   103 #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */
   105 #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)
   106 #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)
   107 #define SH4_INT_PENDING() (sh4r.int_pending && !sh4r.in_delay_slot)
   109 #define FPSCR_FR     0x00200000 /* FPU register bank */
   110 #define FPSCR_SZ     0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
   111 #define FPSCR_PR     0x00080000 /* Precision (0=32 bites, 1=64 bits) */
   112 #define FPSCR_DN     0x00040000 /* Denormalization mode (1 = treat as 0) */
   113 #define FPSCR_CAUSE  0x0003F000
   114 #define FPSCR_ENABLE 0x00000F80
   115 #define FPSCR_FLAG   0x0000007C
   116 #define FPSCR_RM     0x00000003 /* Rounding mode (0=nearest, 1=to zero) */
   118 #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR)
   119 #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
   120 #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
   122 #define FR sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21]
   123 #define XF sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21]
   125 /* Exceptions (for use with sh4_raise_exception) */
   127 #define EX_ILLEGAL_INSTRUCTION 0x180, 0x100
   128 #define EX_SLOT_ILLEGAL        0x1A0, 0x100
   129 #define EX_TLB_MISS_READ       0x040, 0x400
   130 #define EX_TLB_MISS_WRITE      0x060, 0x400
   131 #define EX_INIT_PAGE_WRITE     0x080, 0x100
   132 #define EX_TLB_PROT_READ       0x0A0, 0x100
   133 #define EX_TLB_PROT_WRITE      0x0C0, 0x100
   134 #define EX_DATA_ADDR_READ      0x0E0, 0x100
   135 #define EX_DATA_ADDR_WRITE     0x100, 0x100
   136 #define EX_FPU_EXCEPTION       0x120, 0x100
   137 #define EX_TRAPA               0x160, 0x100
   138 #define EX_BREAKPOINT          0x1E0, 0x100
   139 #define EX_FPU_DISABLED        0x800, 0x100
   140 #define EX_SLOT_FPU_DISABLED   0x820, 0x100
   142 #define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val;
   144 #ifdef __cplusplus
   145 }
   146 #endif
   147 #endif
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