Search
lxdream.org :: lxdream/src/sh4/sh4mmio.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/sh4mmio.c
changeset 23:1ec3acd0594d
prev19:9da7a8e38f9d
next30:89b30313d757
author nkeynes
date Fri Dec 23 11:44:55 2005 +0000 (15 years ago)
permissions -rw-r--r--
last change Start of "real" time slices, general structure in place now
view annotate diff log raw
     1 #include "dream.h"
     2 #include "mem.h"
     3 #include "clock.h"
     4 #include "sh4core.h"
     5 #include "sh4mmio.h"
     6 #define MMIO_IMPL
     7 #include "sh4mmio.h"
     9 /********************************* MMU *************************************/
    11 MMIO_REGION_READ_STUBFN( MMU )
    13 #define OCRAM_START (0x1C000000>>PAGE_BITS)
    14 #define OCRAM_END   (0x20000000>>PAGE_BITS)
    16 static char *cache = NULL;
    18 void mmio_region_MMU_write( uint32_t reg, uint32_t val )
    19 {
    20     switch(reg) {
    21         case CCR:
    22             mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
    23             INFO( "Cache mode set to %08X", val );
    24             break;
    25         default:
    26             break;
    27     }
    28     MMIO_WRITE( MMU, reg, val );
    29 }
    32 void mmu_init() 
    33 {
    34     cache = mem_alloc_pages(2);
    35 }
    37 void mmu_set_cache_mode( int mode )
    38 {
    39     uint32_t i;
    40     switch( mode ) {
    41         case MEM_OC_INDEX0: /* OIX=0 */
    42             for( i=OCRAM_START; i<OCRAM_END; i++ )
    43                 page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));
    44             break;
    45         case MEM_OC_INDEX1: /* OIX=1 */
    46             for( i=OCRAM_START; i<OCRAM_END; i++ )
    47                 page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));
    48             break;
    49         default: /* disabled */
    50             for( i=OCRAM_START; i<OCRAM_END; i++ )
    51                 page_map[i] = NULL;
    52             break;
    53     }
    54 }
    57 /********************************* BSC *************************************/
    59 uint16_t bsc_output_mask_lo = 0, bsc_output_mask_hi = 0;
    60 uint16_t bsc_input_mask_lo = 0, bsc_input_mask_hi = 0;
    61 uint32_t bsc_output = 0, bsc_input = 0x0300;
    63 void bsc_out( int output, int mask )
    64 {
    65     /* Go figure... The BIOS won't start without this mess though */
    66     if( ((output | (~mask)) & 0x03) == 3 ) {
    67         bsc_output |= 0x03;
    68     } else {
    69         bsc_output &= ~0x03;
    70     }
    71 }
    73 void mmio_region_BSC_write( uint32_t reg, uint32_t val )
    74 {
    75     int i;
    76     switch( reg ) {
    77         case PCTRA:
    78             bsc_input_mask_lo = bsc_output_mask_lo = 0;
    79             for( i=0; i<16; i++ ) {
    80                 int bits = (val >> (i<<1)) & 0x03;
    81                 if( bits == 2 ) bsc_input_mask_lo |= (1<<i);
    82                 else if( bits != 0 ) bsc_output_mask_lo |= (1<<i);
    83             }
    84             bsc_output = (bsc_output&0x000F0000) |
    85                 (MMIO_READ( BSC, PDTRA ) & bsc_output_mask_lo);
    86             bsc_out( MMIO_READ( BSC, PDTRA ) | ((MMIO_READ(BSC,PDTRB)<<16)),
    87                      bsc_output_mask_lo | (bsc_output_mask_hi<<16) );
    88             break;
    89         case PCTRB:
    90             bsc_input_mask_hi = bsc_output_mask_hi = 0;
    91             for( i=0; i<4; i++ ) {
    92                 int bits = (val >> (i>>1)) & 0x03;
    93                 if( bits == 2 ) bsc_input_mask_hi |= (1<<i);
    94                 else if( bits != 0 ) bsc_output_mask_hi |= (1<<i);
    95             }
    96             bsc_output = (bsc_output&0xFFFF) |
    97                 ((MMIO_READ( BSC, PDTRA ) & bsc_output_mask_hi)<<16);
    98             break;
    99         case PDTRA:
   100             bsc_output = (bsc_output&0x000F0000) |
   101                 (val & bsc_output_mask_lo );
   102             bsc_out( val | ((MMIO_READ(BSC,PDTRB)<<16)),
   103                      bsc_output_mask_lo | (bsc_output_mask_hi<<16) );
   104             break;
   105         case PDTRB:
   106             bsc_output = (bsc_output&0xFFFF) |
   107                 ( (val & bsc_output_mask_hi)<<16 );
   108             break;
   109     }
   110     WARN( "Write to (mostly) unimplemented BSC (%03X <= %08X) [%s: %s]",
   111           reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );
   112     MMIO_WRITE( BSC, reg, val );
   113 }
   115 int32_t mmio_region_BSC_read( uint32_t reg )
   116 {
   117     int32_t val;
   118     switch( reg ) {
   119         case PDTRA:
   120             val = (bsc_input & bsc_input_mask_lo) | (bsc_output&0xFFFF);
   121             break;
   122         case PDTRB:
   123             val = ((bsc_input>>16) & bsc_input_mask_hi) | (bsc_output>>16);
   124             break;
   125         default:
   126             val = MMIO_READ( BSC, reg );
   127     }
   128     WARN( "Read from (mostly) unimplemented BSC (%03X => %08X) [%s: %s]",
   129           reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );
   130     return val;
   131 }
   133 /********************************* UBC *************************************/
   135 MMIO_REGION_STUBFNS( UBC )
   138 /********************************* DMAC *************************************/
   140 MMIO_REGION_STUBFNS( DMAC )
   144 /********************************** SCI *************************************/
   146 MMIO_REGION_STUBFNS( SCI )
.