3 #if (defined(MMIO_IMPL) && !defined(SH4MMIO_IMPL)) || \
4 (!defined(MMIO_IMPL) && !defined(SH4MMIO_IFACE))
11 /* SH7750 onchip mmio devices */
13 MMIO_REGION_BEGIN( 0xFF000000, MMU, "MMU Registers" )
14 LONG_PORT( 0x000, PTEH, PORT_MRW, UNDEFINED, "Page table entry high" )
15 LONG_PORT( 0x004, PTEL, PORT_MRW, UNDEFINED, "Page table entry low" )
16 LONG_PORT( 0x008, TTB, PORT_MRW, UNDEFINED, "Translation table base" )
17 LONG_PORT( 0x00C, TEA, PORT_MRW, UNDEFINED, "TLB exception address" )
18 LONG_PORT( 0x010, MMUCR,PORT_MRW, 0, "MMU control register" )
19 BYTE_PORT( 0x14, BASRA, PORT_MRW, UNDEFINED, "Break ASID A" ) /* UBC */
20 BYTE_PORT( 0x18, BASRB, PORT_MRW, UNDEFINED, "Break ASID B" ) /* UBC */
21 LONG_PORT( 0x01C, CCR, PORT_MRW, 0, "Cache control register" )
22 LONG_PORT( 0x020, TRA, PORT_MRW, UNDEFINED, "TRAPA exception register" )
23 LONG_PORT( 0x024, EXPEVT,PORT_MRW, 0, "Exception event register" )
24 LONG_PORT( 0x028, INTEVT,PORT_MRW, UNDEFINED, "Interrupt event register" )
25 LONG_PORT( 0x034, PTEA, PORT_MRW, UNDEFINED, "Page table entry assistance" )
26 LONG_PORT( 0x038, QACR0,PORT_MRW, UNDEFINED, "Queue address control 0" )
27 LONG_PORT( 0x03C, QACR1,PORT_MRW, UNDEFINED, "Queue address control 1" )
30 /* User Break Controller (Page 717 [757] of sh7750h manual) */
31 MMIO_REGION_BEGIN( 0xFF200000, UBC, "User Break Controller" )
32 LONG_PORT( 0x000, BARA, PORT_MRW, UNDEFINED, "Break address A" )
33 BYTE_PORT( 0x004, BAMRA, PORT_MRW, UNDEFINED, "Break address mask A" )
34 WORD_PORT( 0x008, BBRA, PORT_MRW, 0, "Break bus cycle A" )
35 LONG_PORT( 0x00C, BARB, PORT_MRW, UNDEFINED, "Break address B" )
36 BYTE_PORT( 0x010, BAMRB, PORT_MRW, UNDEFINED, "Break address mask B" )
37 WORD_PORT( 0x014, BBRB, PORT_MRW, 0, "Break bus cycle B" )
38 LONG_PORT( 0x018, BDRB, PORT_MRW, UNDEFINED, "Break data B" )
39 LONG_PORT( 0x01C, BDMRB, PORT_MRW, UNDEFINED, "Break data mask B" )
40 WORD_PORT( 0x020, BRCR, PORT_MRW, 0, "Break control" )
42 /* Bus State Controller (Page 293 [333] of sh7750h manual)
44 MMIO_REGION_BEGIN( 0xFF800000, BSC, "Bus State Controller" )
45 LONG_PORT( 0x000, BCR1, PORT_MRW, 0, "Bus control 1" )
46 WORD_PORT( 0x004, BCR2, PORT_MRW, 0x3FFC, "Bus control 2" )
47 LONG_PORT( 0x008, WCR1, PORT_MRW, 0x77777777, "Wait state control 1" )
48 LONG_PORT( 0x00C, WCR2, PORT_MRW, 0xFFFEEFFF, "Wait state control 2" )
49 LONG_PORT( 0x010, WCR3, PORT_MRW, 0x07777777, "Wait state control 3" )
50 LONG_PORT( 0x014, MCR, PORT_MRW, 0, "Memory control register" )
51 WORD_PORT( 0x018, PCR, PORT_MRW, 0, "PCMCIA control register" )
52 WORD_PORT( 0x01C, RTCSR, PORT_MRW, 0, "Refresh timer control/status" )
53 WORD_PORT( 0x020, RTCNT, PORT_MRW, 0, "Refresh timer counter" )
54 WORD_PORT( 0x024, RTCOR, PORT_MRW, 0, "Refresh timer constant" )
55 WORD_PORT( 0x028, RFCR, PORT_MRW, 0, "Refresh count" )
56 LONG_PORT( 0x02C, PCTRA, PORT_MRW, 0, "Port control register A" )
57 WORD_PORT( 0x030, PDTRA, PORT_RW, UNDEFINED, "Port data register A" )
58 LONG_PORT( 0x040, PCTRB, PORT_MRW, 0, "Port control register B" )
59 WORD_PORT( 0x044, PDTRB, PORT_RW, UNDEFINED, "Port data register B" )
60 WORD_PORT( 0x048, GPIOIC, PORT_MRW, 0, "GPIO interrupt control register" )
63 /* DMA Controller (Page 457 [497] of sh7750h manual) */
64 MMIO_REGION_BEGIN( 0xFFA00000, DMAC, "DMA Controller" )
65 LONG_PORT( 0x000, SAR0, PORT_MRW, UNDEFINED, "DMA source address 0" )
66 LONG_PORT( 0x004, DAR0, PORT_MRW, UNDEFINED, "DMA destination address 0" )
67 LONG_PORT( 0x008, DMATCR0, PORT_MRW, UNDEFINED, "DMA transfer count 0" )
68 LONG_PORT( 0x00C, CHCR0, PORT_MRW, 0, "DMA channel control 0" )
69 LONG_PORT( 0x010, SAR1, PORT_MRW, UNDEFINED, "DMA source address 1" )
70 LONG_PORT( 0x014, DAR1, PORT_MRW, UNDEFINED, "DMA destination address 1" )
71 LONG_PORT( 0x018, DMATCR1, PORT_MRW, UNDEFINED, "DMA transfer count 1" )
72 LONG_PORT( 0x01C, CHCR1, PORT_MRW, 0, "DMA channel control 1" )
73 LONG_PORT( 0x020, SAR2, PORT_MRW, UNDEFINED, "DMA source address 2" )
74 LONG_PORT( 0x024, DAR2, PORT_MRW, UNDEFINED, "DMA destination address 2" )
75 LONG_PORT( 0x028, DMATCR2, PORT_MRW, UNDEFINED, "DMA transfer count 2" )
76 LONG_PORT( 0x02C, CHCR2, PORT_MRW, 0, "DMA channel control 2" )
77 LONG_PORT( 0x030, SAR3, PORT_MRW, UNDEFINED, "DMA source address 3" )
78 LONG_PORT( 0x034, DAR3, PORT_MRW, UNDEFINED, "DMA destination address 3" )
79 LONG_PORT( 0x038, DMATCR3, PORT_MRW, UNDEFINED, "DMA transfer count 3" )
80 LONG_PORT( 0x03C, CHCR3, PORT_MRW, 0, "DMA channel control 3" )
81 LONG_PORT( 0x040, DMAOR, PORT_MRW, 0, "DMA operation register" )
84 /* Clock Pulse Generator (page 233 [273] of sh7750h manual) */
85 MMIO_REGION_BEGIN( 0xFFC00000, CPG, "Clock Pulse Generator" )
86 WORD_PORT( 0x000, FRQCR, PORT_MRW, UNDEFINED, "Frequency control" )
87 BYTE_PORT( 0x004, STBCR, PORT_MRW, 0, "Standby control" )
88 BYTE_PORT( 0x008, WTCNT, PORT_MRW, 0, "Watchdog timer counter" )
89 BYTE_PORT( 0x00C, WTCSR, PORT_MRW, 0, "Watchdog timer control/status" )
90 BYTE_PORT( 0x010, STBCR2, PORT_MRW, 0, "Standby control 2" )
93 /* Real time clock (Page 253 [293] of sh7750h manual) */
94 MMIO_REGION_BEGIN( 0xFFC80000, RTC, "Realtime Clock" )
95 BYTE_PORT( 0x000, R64CNT, PORT_R, UNDEFINED, "64 Hz counter" )
96 BYTE_PORT( 0x004, RSECCNT, PORT_MRW, UNDEFINED, "Second counter" )
100 /* Interrupt controller (Page 699 [739] of sh7750h manual) */
101 MMIO_REGION_BEGIN( 0xFFD00000, INTC, "Interrupt Controller" )
102 WORD_PORT( 0x000, ICR, PORT_MRW, 0x0000, "Interrupt control register" )
103 WORD_PORT( 0x004, IPRA, PORT_MRW, 0x0000, "Interrupt priority register A" )
104 WORD_PORT( 0x008, IPRB, PORT_MRW, 0x0000, "Interrupt priority register B" )
105 WORD_PORT( 0x00C, IPRC, PORT_MRW, 0x0000, "Interrupt priority register C" )
106 WORD_PORT( 0x010, IPRD, PORT_MRW, 0xDA74, "Interrupt priority register D" )
109 /* Timer unit (Page 277 [317] of sh7750h manual) */
110 MMIO_REGION_BEGIN( 0xFFD80000, TMU, "Timer Unit" )
111 BYTE_PORT( 0x000, TOCR, PORT_MRW, 0x00, "Timer output control register" )
112 BYTE_PORT( 0x004, TSTR, PORT_MRW, 0x00, "Timer start register" )
113 LONG_PORT( 0x008, TCOR0, PORT_MRW, 0xFFFFFFFF, "Timer constant 0" )
114 LONG_PORT( 0x00C, TCNT0, PORT_MRW, 0xFFFFFFFF, "Timer counter 0" )
115 WORD_PORT( 0x010, TCR0, PORT_MRW, 0x0000, "Timer control 0" )
116 LONG_PORT( 0x014, TCOR1, PORT_MRW, 0xFFFFFFFF, "Timer constant 1" )
117 LONG_PORT( 0x018, TCNT1, PORT_MRW, 0xFFFFFFFF, "Timer counter 1" )
118 WORD_PORT( 0x01C, TCR1, PORT_MRW, 0x0000, "Timer control 1" )
119 LONG_PORT( 0x020, TCOR2, PORT_MRW, 0xFFFFFFFF, "Timer constant 2" )
120 LONG_PORT( 0x024, TCNT2, PORT_MRW, 0xFFFFFFFF, "Timer counter 2" )
121 WORD_PORT( 0x028, TCR2, PORT_MRW, 0x0000, "Timer control 2" )
122 LONG_PORT( 0x02C, TCPR2, PORT_R, UNDEFINED, "Input capture register" )
125 /* Serial channel (page 541 [581] of sh7750h manual) */
126 MMIO_REGION_BEGIN( 0xFFE00000, SCI, "Serial Communication Interface" )
127 BYTE_PORT( 0x000, SCSMR1, PORT_MRW, 0x00, "Serial mode register" )
128 BYTE_PORT( 0x004, SCBRR1, PORT_MRW, 0xFF, "Bit rate register" )
129 BYTE_PORT( 0x008, SCSCR1, PORT_MRW, 0x00, "Serial control register" )
130 BYTE_PORT( 0x00C, SCTDR1, PORT_MRW, 0xFF, "Transmit data register" )
131 BYTE_PORT( 0x010, SCSSR1, PORT_MRW, 0x84, "Serial status register" )
132 BYTE_PORT( 0x014, SCRDR1, PORT_R, 0x00, "Receive data register" )
133 BYTE_PORT( 0x01C, SCSPTR1, PORT_MRW, 0x00, "Serial port register" )
136 MMIO_REGION_BEGIN( 0xFFE80000, SCIF, "Serial Controller (FIFO) Registers" )
137 WORD_PORT( 0x000, SCSMR2, PORT_MRW, 0x0000, "Serial mode register (FIFO)" )
138 BYTE_PORT( 0x004, SCBRR2, PORT_MRW, 0xFF, "Bit rate register (FIFO)" )
139 WORD_PORT( 0x008, SCSCR2, PORT_MRW, 0x0000, "Serial control register" )
140 BYTE_PORT( 0x00C, SCFTDR2, PORT_W, UNDEFINED, "Transmit FIFO data register" )
141 WORD_PORT( 0x010, SCFSR2, PORT_MRW, 0x0060, "Serial status register (FIFO)")
142 BYTE_PORT( 0x014, SCFRDR2, PORT_R, UNDEFINED, "Receive FIFO data register" )
143 WORD_PORT( 0x018, SCFCR2, PORT_MRW, 0x0000, "FIFO control register" )
144 WORD_PORT( 0x01C, SCFDR2, PORT_MR, 0x0000, "FIFO data count register" )
145 WORD_PORT( 0x020, SCSPTR2, PORT_MRW, 0x0000, "Serial port register (FIFO)" )
146 WORD_PORT( 0x024, SCLSR2, PORT_MRW, 0x0000, "Line status register (FIFO)" )
149 MMIO_REGION_LIST_BEGIN( sh4mmio )
162 /* mmucr register bits */
163 #define MMUCR_AT 0x00000001 /* Address Translation enabled */
164 #define MMUCR_TI 0x00000004 /* TLB invalidate (always read as 0) */
165 #define MMUCR_SV 0x00000100 /* Single Virtual mode=1 / multiple virtual=0 */
166 #define MMUCR_SQMD 0x00000200 /* Store queue mode bit (0=user, 1=priv only) */
167 #define MMUCR_URC 0x0000FC00 /* UTLB access counter */
168 #define MMUCR_URB 0x00FC0000 /* UTLB entry boundary */
169 #define MMUCR_LRUI 0xFC000000 /* Least recently used ITLB */
170 #define MMUCR_MASK 0xFCFCFF05
171 #define MMUCR_RMASK 0xFCFCFF01 /* Read mask */
173 #define IS_MMU_ENABLED() (MMIO_READ(MMU, MMUCR)&MMUCR_AT)
175 /* ccr register bits */
176 #define CCR_IIX 0x00008000 /* IC index enable */
177 #define CCR_ICI 0x00000800 /* IC invalidation (always read as 0) */
178 #define CCR_ICE 0x00000100 /* IC enable */
179 #define CCR_OIX 0x00000080 /* OC index enable */
180 #define CCR_ORA 0x00000020 /* OC RAM enable */
181 #define CCR_OCI 0x00000008 /* OC invalidation (always read as 0) */
182 #define CCR_CB 0x00000004 /* Copy-back (P1 area cache write mode) */
183 #define CCR_WT 0x00000002 /* Write-through (P0,U0,P3 write mode) */
184 #define CCR_OCE 0x00000001 /* OC enable */
185 #define CCR_MASK 0x000089AF
186 #define CCR_RMASK 0x000081A7 /* Read mask */
188 #define MEM_OC_DISABLED 0
189 #define MEM_OC_INDEX0 CCR_ORA
190 #define MEM_OC_INDEX1 CCR_ORA|CCR_OIX
193 void mmu_set_cache_mode( int );
.
lxdream 0.9.1