lxdream 0.9.1| filename | src/sh4/sh4core.c |
| changeset | 27:1ef09a52cd1e |
| prev | 23:1ec3acd0594d |
| next | 30:89b30313d757 |
| author | nkeynes |
| date | Sun Dec 25 01:28:39 2005 +0000 (15 years ago) |
| permissions | -rw-r--r-- |
| last change | Refactor all the GUI bits out of the main directory (except for a couple lingering temporarily in loader.c Fix a few timeslice issues |
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1 /**
2 * $Id: sh4core.c,v 1.10 2005-12-25 01:28:39 nkeynes Exp $
3 *
4 * SH4 emulation core, and parent module for all the SH4 peripheral
5 * modules.
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #include <math.h>
21 #include "dream.h"
22 #include "modules.h"
23 #include "sh4core.h"
24 #include "sh4mmio.h"
25 #include "mem.h"
26 #include "clock.h"
27 #include "intc.h"
29 /* CPU-generated exception code/vector pairs */
30 #define EXC_POWER_RESET 0x000 /* vector special */
31 #define EXC_MANUAL_RESET 0x020
32 #define EXC_SLOT_ILLEGAL 0x1A0
33 #define EXC_ILLEGAL 0x180
34 #define EXV_ILLEGAL 0x100
35 #define EXC_TRAP 0x160
36 #define EXV_TRAP 0x100
37 #define EXC_FPDISABLE 0x800
38 #define EXV_FPDISABLE 0x100
40 uint32_t sh4_freq = SH4_BASE_RATE;
41 uint32_t sh4_bus_freq = SH4_BASE_RATE;
42 uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 2;
44 /********************** SH4 Module Definition ****************************/
46 void sh4_init( void );
47 void sh4_reset( void );
48 int sh4_run_slice( int );
49 void sh4_start( void );
50 void sh4_stop( void );
51 void sh4_save_state( FILE *f );
52 int sh4_load_state( FILE *f );
54 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
55 NULL, sh4_run_slice, sh4_stop,
56 sh4_save_state, sh4_load_state };
58 struct sh4_registers sh4r;
60 void sh4_init(void)
61 {
62 register_io_regions( mmio_list_sh4mmio );
63 mmu_init();
64 sh4_reset();
65 }
67 void sh4_reset(void)
68 {
69 /* zero everything out, for the sake of having a consistent state. */
70 memset( &sh4r, 0, sizeof(sh4r) );
72 /* Resume running if we were halted */
73 sh4r.sh4_state = SH4_STATE_RUNNING;
75 sh4r.pc = 0xA0000000;
76 sh4r.new_pc= 0xA0000002;
77 sh4r.vbr = 0x00000000;
78 sh4r.fpscr = 0x00040001;
79 sh4r.sr = 0x700000F0;
81 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
82 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
84 /* Peripheral modules */
85 intc_reset();
86 }
88 int sh4_run_slice( int microsecs )
89 {
90 int target = sh4r.icount + sh4_freq * microsecs;
91 int start = sh4r.icount;
92 int i;
94 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
95 if( sh4r.int_pending != 0 )
96 sh4r.sh4_state = SH4_STATE_RUNNING;;
97 }
99 while( sh4r.icount < target && sh4r.sh4_state == SH4_STATE_RUNNING ) {
100 sh4r.icount++;
101 if( !sh4_execute_instruction() )
102 break;
103 }
104 if( target != sh4r.icount ) {
105 /* Halted - compute time actually executed */
106 microsecs = (sh4r.icount - start) / sh4_freq;
107 }
108 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
109 TMU_run_slice( microsecs );
110 SCIF_run_slice( microsecs );
111 }
112 return microsecs;
113 }
115 void sh4_stop(void)
116 {
118 }
120 void sh4_save_state( FILE *f )
121 {
122 fwrite( &sh4r, sizeof(sh4r), 1, f );
123 SCIF_save_state( f );
124 }
126 int sh4_load_state( FILE * f )
127 {
128 fread( &sh4r, sizeof(sh4r), 1, f );
129 return SCIF_load_state( f );
130 }
132 /********************** SH4 emulation core ****************************/
134 void sh4_set_pc( int pc )
135 {
136 sh4r.pc = pc;
137 sh4r.new_pc = pc+2;
138 }
140 void sh4_set_breakpoint( uint32_t pc, int type )
141 {
143 }
145 #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); RAISE( EXC_ILLEGAL, EXV_ILLEGAL ); }while(0)
146 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
148 #define RAISE( x, v ) do{ \
149 if( sh4r.vbr == 0 ) { \
150 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
151 sh4_stop(); \
152 } else { \
153 sh4r.spc = sh4r.pc + 2; \
154 sh4r.ssr = sh4_read_sr(); \
155 sh4r.sgr = sh4r.r[15]; \
156 MMIO_WRITE(MMU,EXPEVT,x); \
157 sh4r.pc = sh4r.vbr + v; \
158 sh4r.new_pc = sh4r.pc + 2; \
159 sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
160 } \
161 return TRUE; } while(0)
163 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
164 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
165 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
166 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
167 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
168 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
170 #define MEM_FP_READ( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
171 ((uint32_t *)FR)[(reg)&0xE0] = sh4_read_long(addr); \
172 ((uint32_t *)FR)[(reg)|1] = sh4_read_long(addr+4); \
173 } else ((uint32_t *)FR)[reg] = sh4_read_long(addr)
175 #define MEM_FP_WRITE( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
176 sh4_write_long( addr, ((uint32_t *)FR)[(reg)&0xE0] ); \
177 sh4_write_long( addr+4, ((uint32_t *)FR)[(reg)|1] ); \
178 } else sh4_write_long( addr, ((uint32_t *)FR)[reg] )
180 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
182 #define CHECK( x, c, v ) if( !x ) RAISE( c, v )
183 #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
184 #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
185 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_stop(); return; }
186 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }
188 static void sh4_switch_banks( )
189 {
190 uint32_t tmp[8];
192 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
193 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
194 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
195 }
197 static void sh4_load_sr( uint32_t newval )
198 {
199 if( (newval ^ sh4r.sr) & SR_RB )
200 sh4_switch_banks();
201 sh4r.sr = newval;
202 sh4r.t = (newval&SR_T) ? 1 : 0;
203 sh4r.s = (newval&SR_S) ? 1 : 0;
204 sh4r.m = (newval&SR_M) ? 1 : 0;
205 sh4r.q = (newval&SR_Q) ? 1 : 0;
206 intc_mask_changed();
207 }
209 static uint32_t sh4_read_sr( void )
210 {
211 /* synchronize sh4r.sr with the various bitflags */
212 sh4r.sr &= SR_MQSTMASK;
213 if( sh4r.t ) sh4r.sr |= SR_T;
214 if( sh4r.s ) sh4r.sr |= SR_S;
215 if( sh4r.m ) sh4r.sr |= SR_M;
216 if( sh4r.q ) sh4r.sr |= SR_Q;
217 return sh4r.sr;
218 }
219 /* function for external use */
220 void sh4_raise_exception( int code, int vector )
221 {
222 RAISE(code, vector);
223 }
225 static void sh4_accept_interrupt( void )
226 {
227 uint32_t code = intc_accept_interrupt();
228 sh4r.ssr = sh4_read_sr();
229 sh4r.spc = sh4r.pc;
230 sh4r.sgr = sh4r.r[15];
231 sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
232 MMIO_WRITE( MMU, INTEVT, code );
233 sh4r.pc = sh4r.vbr + 0x600;
234 sh4r.new_pc = sh4r.pc + 2;
235 WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
236 }
238 gboolean sh4_execute_instruction( void )
239 {
240 int pc;
241 unsigned short ir;
242 uint32_t tmp;
243 uint64_t tmpl;
245 #define R0 sh4r.r[0]
246 #define FR0 (FR[0])
247 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
248 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
249 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
250 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
251 #define DISP8(ir) (ir&0x00FF)
252 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
253 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
254 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
255 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
256 #define FVN(ir) ((ir&0x0C00)>>8)
257 #define FVM(ir) ((ir&0x0300)>>6)
258 #define FRN(ir) (FR[(ir&0x0F00)>>8])
259 #define FRM(ir) (FR[(ir&0x00F0)>>4])
260 #define FRNi(ir) (((uint32_t *)FR)[(ir&0x0F00)>>8])
261 #define FRMi(ir) (((uint32_t *)FR)[(ir&0x00F0)>>4])
262 #define DRN(ir) (((double *)FR)[(ir&0x0E00)>>9])
263 #define DRM(ir) (((double *)FR)[(ir&0x00E0)>>5])
264 #define DRNi(ir) (((uint64_t *)FR)[(ir&0x0E00)>>9])
265 #define DRMi(ir) (((uint64_t *)FR)[(ir&0x00E0)>>5])
266 #define FRNn(ir) ((ir&0x0F00)>>8)
267 #define FRMn(ir) ((ir&0x00F0)>>4)
268 #define FPULf *((float *)&sh4r.fpul)
269 #define FPULi (sh4r.fpul)
271 if( SH4_INT_PENDING() )
272 sh4_accept_interrupt();
274 pc = sh4r.pc;
275 ir = MEM_READ_WORD(pc);
276 sh4r.icount++;
278 switch( (ir&0xF000)>>12 ) {
279 case 0: /* 0000nnnnmmmmxxxx */
280 switch( ir&0x000F ) {
281 case 2:
282 switch( (ir&0x00F0)>>4 ) {
283 case 0: /* STC SR, Rn */
284 CHECKPRIV();
285 RN(ir) = sh4_read_sr();
286 break;
287 case 1: /* STC GBR, Rn */
288 RN(ir) = sh4r.gbr;
289 break;
290 case 2: /* STC VBR, Rn */
291 CHECKPRIV();
292 RN(ir) = sh4r.vbr;
293 break;
294 case 3: /* STC SSR, Rn */
295 CHECKPRIV();
296 RN(ir) = sh4r.ssr;
297 break;
298 case 4: /* STC SPC, Rn */
299 CHECKPRIV();
300 RN(ir) = sh4r.spc;
301 break;
302 case 8: case 9: case 10: case 11: case 12: case 13:
303 case 14: case 15:/* STC Rm_bank, Rn */
304 CHECKPRIV();
305 RN(ir) = RN_BANK(ir);
306 break;
307 default: UNDEF(ir);
308 }
309 break;
310 case 3:
311 switch( (ir&0x00F0)>>4 ) {
312 case 0: /* BSRF Rn */
313 CHECKDEST( pc + 4 + RN(ir) );
314 CHECKSLOTILLEGAL();
315 sh4r.in_delay_slot = 1;
316 sh4r.pr = sh4r.pc + 4;
317 sh4r.pc = sh4r.new_pc;
318 sh4r.new_pc = pc + 4 + RN(ir);
319 return TRUE;
320 case 2: /* BRAF Rn */
321 CHECKDEST( pc + 4 + RN(ir) );
322 CHECKSLOTILLEGAL();
323 sh4r.in_delay_slot = 1;
324 sh4r.pc = sh4r.new_pc;
325 sh4r.new_pc = pc + 4 + RN(ir);
326 return TRUE;
327 case 8: /* PREF [Rn] */
328 tmp = RN(ir);
329 if( (tmp & 0xFC000000) == 0xE0000000 ) {
330 /* Store queue operation */
331 int queue = (tmp&0x20)>>2;
332 int32_t *src = &sh4r.store_queue[queue];
333 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
334 uint32_t target = tmp&0x03FFFFE0 | hi;
335 mem_copy_to_sh4( target, src, 32 );
336 WARN( "Executed SQ%c => %08X",
337 (queue == 0 ? '0' : '1'), target );
338 }
339 break;
340 case 9: /* OCBI [Rn] */
341 case 10:/* OCBP [Rn] */
342 case 11:/* OCBWB [Rn] */
343 /* anything? */
344 break;
345 case 12:/* MOVCA.L R0, [Rn] */
346 UNIMP(ir);
347 default: UNDEF(ir);
348 }
349 break;
350 case 4: /* MOV.B Rm, [R0 + Rn] */
351 MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
352 break;
353 case 5: /* MOV.W Rm, [R0 + Rn] */
354 MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
355 break;
356 case 6: /* MOV.L Rm, [R0 + Rn] */
357 MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
358 break;
359 case 7: /* MUL.L Rm, Rn */
360 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
361 (RM(ir) * RN(ir));
362 break;
363 case 8:
364 switch( (ir&0x0FF0)>>4 ) {
365 case 0: /* CLRT */
366 sh4r.t = 0;
367 break;
368 case 1: /* SETT */
369 sh4r.t = 1;
370 break;
371 case 2: /* CLRMAC */
372 sh4r.mac = 0;
373 break;
374 case 3: /* LDTLB */
375 break;
376 case 4: /* CLRS */
377 sh4r.s = 0;
378 break;
379 case 5: /* SETS */
380 sh4r.s = 1;
381 break;
382 default: UNDEF(ir);
383 }
384 break;
385 case 9:
386 if( (ir&0x00F0) == 0x20 ) /* MOVT Rn */
387 RN(ir) = sh4r.t;
388 else if( ir == 0x0019 ) /* DIV0U */
389 sh4r.m = sh4r.q = sh4r.t = 0;
390 else if( ir == 0x0009 )
391 /* NOP */;
392 else UNDEF(ir);
393 break;
394 case 10:
395 switch( (ir&0x00F0) >> 4 ) {
396 case 0: /* STS MACH, Rn */
397 RN(ir) = sh4r.mac >> 32;
398 break;
399 case 1: /* STS MACL, Rn */
400 RN(ir) = (uint32_t)sh4r.mac;
401 break;
402 case 2: /* STS PR, Rn */
403 RN(ir) = sh4r.pr;
404 break;
405 case 3: /* STC SGR, Rn */
406 CHECKPRIV();
407 RN(ir) = sh4r.sgr;
408 break;
409 case 5:/* STS FPUL, Rn */
410 RN(ir) = sh4r.fpul;
411 break;
412 case 6: /* STS FPSCR, Rn */
413 RN(ir) = sh4r.fpscr;
414 break;
415 case 15:/* STC DBR, Rn */
416 CHECKPRIV();
417 RN(ir) = sh4r.dbr;
418 break;
419 default: UNDEF(ir);
420 }
421 break;
422 case 11:
423 switch( (ir&0x0FF0)>>4 ) {
424 case 0: /* RTS */
425 CHECKDEST( sh4r.pr );
426 CHECKSLOTILLEGAL();
427 sh4r.in_delay_slot = 1;
428 sh4r.pc = sh4r.new_pc;
429 sh4r.new_pc = sh4r.pr;
430 return TRUE;
431 case 1: /* SLEEP */
432 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
433 sh4r.sh4_state = SH4_STATE_STANDBY;
434 } else {
435 sh4r.sh4_state = SH4_STATE_SLEEP;
436 }
437 return FALSE; /* Halt CPU */
438 case 2: /* RTE */
439 CHECKPRIV();
440 CHECKDEST( sh4r.spc );
441 CHECKSLOTILLEGAL();
442 sh4r.in_delay_slot = 1;
443 sh4r.pc = sh4r.new_pc;
444 sh4r.new_pc = sh4r.spc;
445 sh4_load_sr( sh4r.ssr );
446 WARN( "RTE => %08X", sh4r.new_pc );
447 return TRUE;
448 default:UNDEF(ir);
449 }
450 break;
451 case 12:/* MOV.B [R0+R%d], R%d */
452 RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
453 break;
454 case 13:/* MOV.W [R0+R%d], R%d */
455 RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
456 break;
457 case 14:/* MOV.L [R0+R%d], R%d */
458 RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
459 break;
460 case 15:/* MAC.L [Rm++], [Rn++] */
461 tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
462 SIGNEXT32(MEM_READ_LONG(RN(ir))) );
463 if( sh4r.s ) {
464 /* 48-bit Saturation. Yuch */
465 tmpl += SIGNEXT48(sh4r.mac);
466 if( tmpl < 0xFFFF800000000000LL )
467 tmpl = 0xFFFF800000000000LL;
468 else if( tmpl > 0x00007FFFFFFFFFFFLL )
469 tmpl = 0x00007FFFFFFFFFFFLL;
470 sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
471 (tmpl&0x0000FFFFFFFFFFFFLL);
472 } else sh4r.mac = tmpl;
474 RM(ir) += 4;
475 RN(ir) += 4;
477 break;
478 default: UNDEF(ir);
479 }
480 break;
481 case 1: /* 0001nnnnmmmmdddd */
482 /* MOV.L Rm, [Rn + disp4*4] */
483 MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) );
484 break;
485 case 2: /* 0010nnnnmmmmxxxx */
486 switch( ir&0x000F ) {
487 case 0: /* MOV.B Rm, [Rn] */
488 MEM_WRITE_BYTE( RN(ir), RM(ir) );
489 break;
490 case 1: /* MOV.W Rm, [Rn] */
491 MEM_WRITE_WORD( RN(ir), RM(ir) );
492 break;
493 case 2: /* MOV.L Rm, [Rn] */
494 MEM_WRITE_LONG( RN(ir), RM(ir) );
495 break;
496 case 3: UNDEF(ir);
497 break;
498 case 4: /* MOV.B Rm, [--Rn] */
499 RN(ir) --;
500 MEM_WRITE_BYTE( RN(ir), RM(ir) );
501 break;
502 case 5: /* MOV.W Rm, [--Rn] */
503 RN(ir) -= 2;
504 MEM_WRITE_WORD( RN(ir), RM(ir) );
505 break;
506 case 6: /* MOV.L Rm, [--Rn] */
507 RN(ir) -= 4;
508 MEM_WRITE_LONG( RN(ir), RM(ir) );
509 break;
510 case 7: /* DIV0S Rm, Rn */
511 sh4r.q = RN(ir)>>31;
512 sh4r.m = RM(ir)>>31;
513 sh4r.t = sh4r.q ^ sh4r.m;
514 break;
515 case 8: /* TST Rm, Rn */
516 sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
517 break;
518 case 9: /* AND Rm, Rn */
519 RN(ir) &= RM(ir);
520 break;
521 case 10:/* XOR Rm, Rn */
522 RN(ir) ^= RM(ir);
523 break;
524 case 11:/* OR Rm, Rn */
525 RN(ir) |= RM(ir);
526 break;
527 case 12:/* CMP/STR Rm, Rn */
528 /* set T = 1 if any byte in RM & RN is the same */
529 tmp = RM(ir) ^ RN(ir);
530 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
531 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
532 break;
533 case 13:/* XTRCT Rm, Rn */
534 RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
535 break;
536 case 14:/* MULU.W Rm, Rn */
537 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
538 (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
539 break;
540 case 15:/* MULS.W Rm, Rn */
541 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
542 (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
543 break;
544 }
545 break;
546 case 3: /* 0011nnnnmmmmxxxx */
547 switch( ir&0x000F ) {
548 case 0: /* CMP/EQ Rm, Rn */
549 sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
550 break;
551 case 2: /* CMP/HS Rm, Rn */
552 sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
553 break;
554 case 3: /* CMP/GE Rm, Rn */
555 sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
556 break;
557 case 4: { /* DIV1 Rm, Rn */
558 /* This is just from the sh4p manual with some
559 * simplifications (someone want to check it's correct? :)
560 * Why they couldn't just provide a real DIV instruction...
561 * Please oh please let the translator batch these things
562 * up into a single DIV... */
563 uint32_t tmp0, tmp1, tmp2, dir;
565 dir = sh4r.q ^ sh4r.m;
566 sh4r.q = (RN(ir) >> 31);
567 tmp2 = RM(ir);
568 RN(ir) = (RN(ir) << 1) | sh4r.t;
569 tmp0 = RN(ir);
570 if( dir ) {
571 RN(ir) += tmp2;
572 tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
573 } else {
574 RN(ir) -= tmp2;
575 tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
576 }
577 sh4r.q ^= sh4r.m ^ tmp1;
578 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
579 break; }
580 case 5: /* DMULU.L Rm, Rn */
581 sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
582 break;
583 case 6: /* CMP/HI Rm, Rn */
584 sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
585 break;
586 case 7: /* CMP/GT Rm, Rn */
587 sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
588 break;
589 case 8: /* SUB Rm, Rn */
590 RN(ir) -= RM(ir);
591 break;
592 case 10:/* SUBC Rm, Rn */
593 tmp = RN(ir);
594 RN(ir) = RN(ir) - RM(ir) - sh4r.t;
595 sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
596 break;
597 case 11:/* SUBV Rm, Rn */
598 UNIMP(ir);
599 break;
600 case 12:/* ADD Rm, Rn */
601 RN(ir) += RM(ir);
602 break;
603 case 13:/* DMULS.L Rm, Rn */
604 sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
605 break;
606 case 14:/* ADDC Rm, Rn */
607 tmp = RN(ir);
608 RN(ir) += RM(ir) + sh4r.t;
609 sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
610 break;
611 case 15:/* ADDV Rm, Rn */
612 UNIMP(ir);
613 break;
614 default: UNDEF(ir);
615 }
616 break;
617 case 4: /* 0100nnnnxxxxxxxx */
618 switch( ir&0x00FF ) {
619 case 0x00: /* SHLL Rn */
620 sh4r.t = RN(ir) >> 31;
621 RN(ir) <<= 1;
622 break;
623 case 0x01: /* SHLR Rn */
624 sh4r.t = RN(ir) & 0x00000001;
625 RN(ir) >>= 1;
626 break;
627 case 0x02: /* STS.L MACH, [--Rn] */
628 RN(ir) -= 4;
629 MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
630 break;
631 case 0x03: /* STC.L SR, [--Rn] */
632 CHECKPRIV();
633 RN(ir) -= 4;
634 MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
635 break;
636 case 0x04: /* ROTL Rn */
637 sh4r.t = RN(ir) >> 31;
638 RN(ir) <<= 1;
639 RN(ir) |= sh4r.t;
640 break;
641 case 0x05: /* ROTR Rn */
642 sh4r.t = RN(ir) & 0x00000001;
643 RN(ir) >>= 1;
644 RN(ir) |= (sh4r.t << 31);
645 break;
646 case 0x06: /* LDS.L [Rn++], MACH */
647 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
648 (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
649 RN(ir) += 4;
650 break;
651 case 0x07: /* LDC.L [Rn++], SR */
652 CHECKPRIV();
653 sh4_load_sr( MEM_READ_LONG(RN(ir)) );
654 RN(ir) +=4;
655 break;
656 case 0x08: /* SHLL2 Rn */
657 RN(ir) <<= 2;
658 break;
659 case 0x09: /* SHLR2 Rn */
660 RN(ir) >>= 2;
661 break;
662 case 0x0A: /* LDS Rn, MACH */
663 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
664 (((uint64_t)RN(ir))<<32);
665 break;
666 case 0x0B: /* JSR [Rn] */
667 CHECKDEST( RN(ir) );
668 CHECKSLOTILLEGAL();
669 sh4r.in_delay_slot = 1;
670 sh4r.pc = sh4r.new_pc;
671 sh4r.new_pc = RN(ir);
672 sh4r.pr = pc + 4;
673 return TRUE;
674 case 0x0E: /* LDC Rn, SR */
675 CHECKPRIV();
676 sh4_load_sr( RN(ir) );
677 break;
678 case 0x10: /* DT Rn */
679 RN(ir) --;
680 sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
681 break;
682 case 0x11: /* CMP/PZ Rn */
683 sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
684 break;
685 case 0x12: /* STS.L MACL, [--Rn] */
686 RN(ir) -= 4;
687 MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
688 break;
689 case 0x13: /* STC.L GBR, [--Rn] */
690 RN(ir) -= 4;
691 MEM_WRITE_LONG( RN(ir), sh4r.gbr );
692 break;
693 case 0x15: /* CMP/PL Rn */
694 sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
695 break;
696 case 0x16: /* LDS.L [Rn++], MACL */
697 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
698 (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
699 RN(ir) += 4;
700 break;
701 case 0x17: /* LDC.L [Rn++], GBR */
702 sh4r.gbr = MEM_READ_LONG(RN(ir));
703 RN(ir) +=4;
704 break;
705 case 0x18: /* SHLL8 Rn */
706 RN(ir) <<= 8;
707 break;
708 case 0x19: /* SHLR8 Rn */
709 RN(ir) >>= 8;
710 break;
711 case 0x1A: /* LDS Rn, MACL */
712 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
713 (uint64_t)((uint32_t)(RN(ir)));
714 break;
715 case 0x1B: /* TAS.B [Rn] */
716 tmp = MEM_READ_BYTE( RN(ir) );
717 sh4r.t = ( tmp == 0 ? 1 : 0 );
718 MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
719 break;
720 case 0x1E: /* LDC Rn, GBR */
721 sh4r.gbr = RN(ir);
722 break;
723 case 0x20: /* SHAL Rn */
724 sh4r.t = RN(ir) >> 31;
725 RN(ir) <<= 1;
726 break;
727 case 0x21: /* SHAR Rn */
728 sh4r.t = RN(ir) & 0x00000001;
729 RN(ir) = ((int32_t)RN(ir)) >> 1;
730 break;
731 case 0x22: /* STS.L PR, [--Rn] */
732 RN(ir) -= 4;
733 MEM_WRITE_LONG( RN(ir), sh4r.pr );
734 break;
735 case 0x23: /* STC.L VBR, [--Rn] */
736 CHECKPRIV();
737 RN(ir) -= 4;
738 MEM_WRITE_LONG( RN(ir), sh4r.vbr );
739 break;
740 case 0x24: /* ROTCL Rn */
741 tmp = RN(ir) >> 31;
742 RN(ir) <<= 1;
743 RN(ir) |= sh4r.t;
744 sh4r.t = tmp;
745 break;
746 case 0x25: /* ROTCR Rn */
747 tmp = RN(ir) & 0x00000001;
748 RN(ir) >>= 1;
749 RN(ir) |= (sh4r.t << 31 );
750 sh4r.t = tmp;
751 break;
752 case 0x26: /* LDS.L [Rn++], PR */
753 sh4r.pr = MEM_READ_LONG( RN(ir) );
754 RN(ir) += 4;
755 break;
756 case 0x27: /* LDC.L [Rn++], VBR */
757 CHECKPRIV();
758 sh4r.vbr = MEM_READ_LONG(RN(ir));
759 RN(ir) +=4;
760 break;
761 case 0x28: /* SHLL16 Rn */
762 RN(ir) <<= 16;
763 break;
764 case 0x29: /* SHLR16 Rn */
765 RN(ir) >>= 16;
766 break;
767 case 0x2A: /* LDS Rn, PR */
768 sh4r.pr = RN(ir);
769 break;
770 case 0x2B: /* JMP [Rn] */
771 CHECKDEST( RN(ir) );
772 CHECKSLOTILLEGAL();
773 sh4r.in_delay_slot = 1;
774 sh4r.pc = sh4r.new_pc;
775 sh4r.new_pc = RN(ir);
776 return TRUE;
777 case 0x2E: /* LDC Rn, VBR */
778 CHECKPRIV();
779 sh4r.vbr = RN(ir);
780 break;
781 case 0x32: /* STC.L SGR, [--Rn] */
782 CHECKPRIV();
783 RN(ir) -= 4;
784 MEM_WRITE_LONG( RN(ir), sh4r.sgr );
785 break;
786 case 0x33: /* STC.L SSR, [--Rn] */
787 CHECKPRIV();
788 RN(ir) -= 4;
789 MEM_WRITE_LONG( RN(ir), sh4r.ssr );
790 break;
791 case 0x37: /* LDC.L [Rn++], SSR */
792 CHECKPRIV();
793 sh4r.ssr = MEM_READ_LONG(RN(ir));
794 RN(ir) +=4;
795 break;
796 case 0x3E: /* LDC Rn, SSR */
797 CHECKPRIV();
798 sh4r.ssr = RN(ir);
799 break;
800 case 0x43: /* STC.L SPC, [--Rn] */
801 CHECKPRIV();
802 RN(ir) -= 4;
803 MEM_WRITE_LONG( RN(ir), sh4r.spc );
804 break;
805 case 0x47: /* LDC.L [Rn++], SPC */
806 CHECKPRIV();
807 sh4r.spc = MEM_READ_LONG(RN(ir));
808 RN(ir) +=4;
809 break;
810 case 0x4E: /* LDC Rn, SPC */
811 CHECKPRIV();
812 sh4r.spc = RN(ir);
813 break;
814 case 0x52: /* STS.L FPUL, [--Rn] */
815 RN(ir) -= 4;
816 MEM_WRITE_LONG( RN(ir), sh4r.fpul );
817 break;
818 case 0x56: /* LDS.L [Rn++], FPUL */
819 sh4r.fpul = MEM_READ_LONG(RN(ir));
820 RN(ir) +=4;
821 break;
822 case 0x5A: /* LDS Rn, FPUL */
823 sh4r.fpul = RN(ir);
824 break;
825 case 0x62: /* STS.L FPSCR, [--Rn] */
826 RN(ir) -= 4;
827 MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
828 break;
829 case 0x66: /* LDS.L [Rn++], FPSCR */
830 sh4r.fpscr = MEM_READ_LONG(RN(ir));
831 RN(ir) +=4;
832 break;
833 case 0x6A: /* LDS Rn, FPSCR */
834 sh4r.fpscr = RN(ir);
835 break;
836 case 0xF2: /* STC.L DBR, [--Rn] */
837 CHECKPRIV();
838 RN(ir) -= 4;
839 MEM_WRITE_LONG( RN(ir), sh4r.dbr );
840 break;
841 case 0xF6: /* LDC.L [Rn++], DBR */
842 CHECKPRIV();
843 sh4r.dbr = MEM_READ_LONG(RN(ir));
844 RN(ir) +=4;
845 break;
846 case 0xFA: /* LDC Rn, DBR */
847 CHECKPRIV();
848 sh4r.dbr = RN(ir);
849 break;
850 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
851 case 0xD3: case 0xE3: case 0xF3: /* STC.L Rn_BANK, [--Rn] */
852 CHECKPRIV();
853 RN(ir) -= 4;
854 MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
855 break;
856 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
857 case 0xD7: case 0xE7: case 0xF7: /* LDC.L [Rn++], Rn_BANK */
858 CHECKPRIV();
859 RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
860 RN(ir) += 4;
861 break;
862 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
863 case 0xDE: case 0xEE: case 0xFE: /* LDC Rm, Rn_BANK */
864 CHECKPRIV();
865 RN_BANK(ir) = RM(ir);
866 break;
867 default:
868 if( (ir&0x000F) == 0x0F ) {
869 /* MAC.W [Rm++], [Rn++] */
870 tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
871 SIGNEXT16(MEM_READ_WORD(RN(ir)));
872 if( sh4r.s ) {
873 /* FIXME */
874 UNIMP(ir);
875 } else sh4r.mac += SIGNEXT32(tmp);
876 RM(ir) += 2;
877 RN(ir) += 2;
878 } else if( (ir&0x000F) == 0x0C ) {
879 /* SHAD Rm, Rn */
880 tmp = RM(ir);
881 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
882 else if( (tmp & 0x1F) == 0 )
883 RN(ir) = ((int32_t)RN(ir)) >> 31;
884 else
885 RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
886 } else if( (ir&0x000F) == 0x0D ) {
887 /* SHLD Rm, Rn */
888 tmp = RM(ir);
889 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
890 else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
891 else RN(ir) >>= (((~tmp) & 0x1F)+1);
892 } else UNDEF(ir);
893 }
894 break;
895 case 5: /* 0101nnnnmmmmdddd */
896 /* MOV.L [Rm + disp4*4], Rn */
897 RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) );
898 break;
899 case 6: /* 0110xxxxxxxxxxxx */
900 switch( ir&0x000f ) {
901 case 0: /* MOV.B [Rm], Rn */
902 RN(ir) = MEM_READ_BYTE( RM(ir) );
903 break;
904 case 1: /* MOV.W [Rm], Rn */
905 RN(ir) = MEM_READ_WORD( RM(ir) );
906 break;
907 case 2: /* MOV.L [Rm], Rn */
908 RN(ir) = MEM_READ_LONG( RM(ir) );
909 break;
910 case 3: /* MOV Rm, Rn */
911 RN(ir) = RM(ir);
912 break;
913 case 4: /* MOV.B [Rm++], Rn */
914 RN(ir) = MEM_READ_BYTE( RM(ir) );
915 RM(ir) ++;
916 break;
917 case 5: /* MOV.W [Rm++], Rn */
918 RN(ir) = MEM_READ_WORD( RM(ir) );
919 RM(ir) += 2;
920 break;
921 case 6: /* MOV.L [Rm++], Rn */
922 RN(ir) = MEM_READ_LONG( RM(ir) );
923 RM(ir) += 4;
924 break;
925 case 7: /* NOT Rm, Rn */
926 RN(ir) = ~RM(ir);
927 break;
928 case 8: /* SWAP.B Rm, Rn */
929 RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
930 ((RM(ir)&0x000000FF)<<8);
931 break;
932 case 9: /* SWAP.W Rm, Rn */
933 RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
934 break;
935 case 10:/* NEGC Rm, Rn */
936 tmp = 0 - RM(ir);
937 RN(ir) = tmp - sh4r.t;
938 sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
939 break;
940 case 11:/* NEG Rm, Rn */
941 RN(ir) = 0 - RM(ir);
942 break;
943 case 12:/* EXTU.B Rm, Rn */
944 RN(ir) = RM(ir)&0x000000FF;
945 break;
946 case 13:/* EXTU.W Rm, Rn */
947 RN(ir) = RM(ir)&0x0000FFFF;
948 break;
949 case 14:/* EXTS.B Rm, Rn */
950 RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
951 break;
952 case 15:/* EXTS.W Rm, Rn */
953 RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
954 break;
955 }
956 break;
957 case 7: /* 0111nnnniiiiiiii */
958 /* ADD imm8, Rn */
959 RN(ir) += IMM8(ir);
960 break;
961 case 8: /* 1000xxxxxxxxxxxx */
962 switch( (ir&0x0F00) >> 8 ) {
963 case 0: /* MOV.B R0, [Rm + disp4] */
964 MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
965 break;
966 case 1: /* MOV.W R0, [Rm + disp4*2] */
967 MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 );
968 break;
969 case 4: /* MOV.B [Rm + disp4], R0 */
970 R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
971 break;
972 case 5: /* MOV.W [Rm + disp4*2], R0 */
973 R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) );
974 break;
975 case 8: /* CMP/EQ imm, R0 */
976 sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
977 break;
978 case 9: /* BT disp8 */
979 CHECKSLOTILLEGAL()
980 if( sh4r.t ) {
981 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
982 sh4r.pc += (PCDISP8(ir)<<1) + 4;
983 sh4r.new_pc = sh4r.pc + 2;
984 return TRUE;
985 }
986 break;
987 case 11:/* BF disp8 */
988 CHECKSLOTILLEGAL()
989 if( !sh4r.t ) {
990 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
991 sh4r.pc += (PCDISP8(ir)<<1) + 4;
992 sh4r.new_pc = sh4r.pc + 2;
993 return TRUE;
994 }
995 break;
996 case 13:/* BT/S disp8 */
997 CHECKSLOTILLEGAL()
998 if( sh4r.t ) {
999 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1000 sh4r.in_delay_slot = 1;
1001 sh4r.pc = sh4r.new_pc;
1002 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1003 sh4r.in_delay_slot = 1;
1004 return TRUE;
1005 }
1006 break;
1007 case 15:/* BF/S disp8 */
1008 CHECKSLOTILLEGAL()
1009 if( !sh4r.t ) {
1010 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1011 sh4r.in_delay_slot = 1;
1012 sh4r.pc = sh4r.new_pc;
1013 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1014 return TRUE;
1015 }
1016 break;
1017 default: UNDEF(ir);
1018 }
1019 break;
1020 case 9: /* 1001xxxxxxxxxxxx */
1021 /* MOV.W [disp8*2 + pc + 4], Rn */
1022 RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) );
1023 break;
1024 case 10:/* 1010dddddddddddd */
1025 /* BRA disp12 */
1026 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
1027 CHECKSLOTILLEGAL()
1028 sh4r.in_delay_slot = 1;
1029 sh4r.pc = sh4r.new_pc;
1030 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1031 return TRUE;
1032 case 11:/* 1011dddddddddddd */
1033 /* BSR disp12 */
1034 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
1035 CHECKSLOTILLEGAL()
1036 sh4r.in_delay_slot = 1;
1037 sh4r.pr = pc + 4;
1038 sh4r.pc = sh4r.new_pc;
1039 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1040 return TRUE;
1041 case 12:/* 1100xxxxdddddddd */
1042 switch( (ir&0x0F00)>>8 ) {
1043 case 0: /* MOV.B R0, [GBR + disp8] */
1044 MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
1045 break;
1046 case 1: /* MOV.W R0, [GBR + disp8*2] */
1047 MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 );
1048 break;
1049 case 2: /*MOV.L R0, [GBR + disp8*4] */
1050 MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 );
1051 break;
1052 case 3: /* TRAPA imm8 */
1053 CHECKSLOTILLEGAL()
1054 sh4r.in_delay_slot = 1;
1055 MMIO_WRITE( MMU, TRA, UIMM8(ir) );
1056 sh4r.pc = sh4r.new_pc; /* RAISE ends the instruction */
1057 sh4r.new_pc += 2;
1058 RAISE( EXC_TRAP, EXV_TRAP );
1059 break;
1060 case 4: /* MOV.B [GBR + disp8], R0 */
1061 R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
1062 break;
1063 case 5: /* MOV.W [GBR + disp8*2], R0 */
1064 R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) );
1065 break;
1066 case 6: /* MOV.L [GBR + disp8*4], R0 */
1067 R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) );
1068 break;
1069 case 7: /* MOVA disp8 + pc&~3 + 4, R0 */
1070 R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
1071 break;
1072 case 8: /* TST imm8, R0 */
1073 sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
1074 break;
1075 case 9: /* AND imm8, R0 */
1076 R0 &= UIMM8(ir);
1077 break;
1078 case 10:/* XOR imm8, R0 */
1079 R0 ^= UIMM8(ir);
1080 break;
1081 case 11:/* OR imm8, R0 */
1082 R0 |= UIMM8(ir);
1083 break;
1084 case 12:/* TST.B imm8, [R0+GBR] */
1085 sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
1086 break;
1087 case 13:/* AND.B imm8, [R0+GBR] */
1088 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1089 UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
1090 break;
1091 case 14:/* XOR.B imm8, [R0+GBR] */
1092 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1093 UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
1094 break;
1095 case 15:/* OR.B imm8, [R0+GBR] */
1096 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1097 UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
1098 break;
1099 }
1100 break;
1101 case 13:/* 1101nnnndddddddd */
1102 /* MOV.L [disp8*4 + pc&~3 + 4], Rn */
1103 RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 );
1104 break;
1105 case 14:/* 1110nnnniiiiiiii */
1106 /* MOV imm8, Rn */
1107 RN(ir) = IMM8(ir);
1108 break;
1109 case 15:/* 1111xxxxxxxxxxxx */
1110 CHECKFPUEN();
1111 switch( ir&0x000F ) {
1112 case 0: /* FADD FRm, FRn */
1113 FRN(ir) += FRM(ir);
1114 break;
1115 case 1: /* FSUB FRm, FRn */
1116 FRN(ir) -= FRM(ir);
1117 break;
1118 case 2: /* FMUL FRm, FRn */
1119 FRN(ir) = FRN(ir) * FRM(ir);
1120 break;
1121 case 3: /* FDIV FRm, FRn */
1122 FRN(ir) = FRN(ir) / FRM(ir);
1123 break;
1124 case 4: /* FCMP/EQ FRm, FRn */
1125 sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
1126 break;
1127 case 5: /* FCMP/GT FRm, FRn */
1128 sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
1129 break;
1130 case 6: /* FMOV.S [Rm+R0], FRn */
1131 MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
1132 break;
1133 case 7: /* FMOV.S FRm, [Rn+R0] */
1134 MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
1135 break;
1136 case 8: /* FMOV.S [Rm], FRn */
1137 MEM_FP_READ( RM(ir), FRNn(ir) );
1138 break;
1139 case 9: /* FMOV.S [Rm++], FRn */
1140 MEM_FP_READ( RM(ir), FRNn(ir) );
1141 RM(ir) += FP_WIDTH;
1142 break;
1143 case 10:/* FMOV.S FRm, [Rn] */
1144 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1145 break;
1146 case 11:/* FMOV.S FRm, [--Rn] */
1147 RN(ir) -= FP_WIDTH;
1148 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1149 break;
1150 case 12:/* FMOV FRm, FRn */
1151 if( IS_FPU_DOUBLESIZE() ) {
1152 DRN(ir) = DRM(ir);
1153 } else {
1154 FRN(ir) = FRM(ir);
1155 }
1156 break;
1157 case 13:
1158 switch( (ir&0x00F0) >> 4 ) {
1159 case 0: /* FSTS FPUL, FRn */
1160 FRN(ir) = FPULf;
1161 break;
1162 case 1: /* FLDS FRn, FPUL */
1163 FPULf = FRN(ir);
1164 break;
1165 case 2: /* FLOAT FPUL, FRn */
1166 FRN(ir) = (float)FPULi;
1167 break;
1168 case 3: /* FTRC FRn, FPUL */
1169 FPULi = (uint32_t)FRN(ir);
1170 /* FIXME: is this sufficient? */
1171 break;
1172 case 4: /* FNEG FRn */
1173 FRN(ir) = -FRN(ir);
1174 break;
1175 case 5: /* FABS FRn */
1176 FRN(ir) = fabsf(FRN(ir));
1177 break;
1178 case 6: /* FSQRT FRn */
1179 FRN(ir) = sqrtf(FRN(ir));
1180 break;
1181 case 7: /* FSRRA FRn */
1182 FRN(ir) = 1.0/sqrtf(FRN(ir));
1183 break;
1184 case 8: /* FLDI0 FRn */
1185 FRN(ir) = 0.0;
1186 break;
1187 case 9: /* FLDI1 FRn */
1188 FRN(ir) = 1.0;
1189 break;
1190 case 10: /* FCNVSD FPUL, DRn */
1191 if( IS_FPU_DOUBLEPREC() )
1192 DRN(ir) = (double)FPULf;
1193 else UNDEF(ir);
1194 break;
1195 case 11: /* FCNVDS DRn, FPUL */
1196 if( IS_FPU_DOUBLEPREC() )
1197 FPULf = (float)DRN(ir);
1198 else UNDEF(ir);
1199 break;
1200 case 14:/* FIPR FVm, FVn */
1201 /* FIXME: This is not going to be entirely accurate
1202 * as the SH4 instruction is less precise. Also
1203 * need to check for 0s and infinities.
1204 */
1205 {
1206 float *fr_bank = FR;
1207 int tmp2 = FVN(ir);
1208 tmp = FVM(ir);
1209 fr_bank[tmp2+3] = fr_bank[tmp]*fr_bank[tmp2] +
1210 fr_bank[tmp+1]*fr_bank[tmp2+1] +
1211 fr_bank[tmp+2]*fr_bank[tmp2+2] +
1212 fr_bank[tmp+3]*fr_bank[tmp2+3];
1213 break;
1214 }
1215 case 15:
1216 if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
1217 float *fvout = FR+FVN(ir);
1218 float *xm = XF;
1219 float fv[4] = { fvout[0], fvout[1], fvout[2], fvout[3] };
1220 fvout[0] = xm[0] * fv[0] + xm[4]*fv[1] +
1221 xm[8]*fv[2] + xm[12]*fv[3];
1222 fvout[1] = xm[1] * fv[0] + xm[5]*fv[1] +
1223 xm[9]*fv[2] + xm[13]*fv[3];
1224 fvout[2] = xm[2] * fv[0] + xm[6]*fv[1] +
1225 xm[10]*fv[2] + xm[14]*fv[3];
1226 fvout[3] = xm[3] * fv[0] + xm[7]*fv[1] +
1227 xm[11]*fv[2] + xm[15]*fv[3];
1228 break;
1229 }
1230 else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
1231 float angle = (((float)(short)(FPULi>>16)) +
1232 ((float)(FPULi&16)/65536.0)) *
1233 2 * M_PI;
1234 int reg = FRNn(ir);
1235 FR[reg] = sinf(angle);
1236 FR[reg+1] = cosf(angle);
1237 break;
1238 }
1239 else if( ir == 0xFBFD ) {
1240 /* FRCHG */
1241 sh4r.fpscr ^= FPSCR_FR;
1242 break;
1243 }
1244 else if( ir == 0xF3FD ) {
1245 /* FSCHG */
1246 sh4r.fpscr ^= FPSCR_SZ;
1247 break;
1248 }
1249 default: UNDEF(ir);
1250 }
1251 break;
1252 case 14:/* FMAC FR0, FRm, FRn */
1253 FRN(ir) += FRM(ir)*FR0;
1254 break;
1255 default: UNDEF(ir);
1256 }
1257 break;
1258 }
1259 sh4r.pc = sh4r.new_pc;
1260 sh4r.new_pc += 2;
1261 sh4r.in_delay_slot = 0;
1262 }
.