filename | src/asic.c |
changeset | 430:467519b050f4 |
prev | 422:61a0598e07ff |
next | 549:828d103ad115 |
author | nkeynes |
date | Wed Oct 17 11:26:45 2007 +0000 (16 years ago) |
permissions | -rw-r--r-- |
last change | Split config management out to config.[ch] Manage config filename Check home dir + sysconfdir for conf file Initial work on a path settings dialog |
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1 /**
2 * $Id: asic.c,v 1.30 2007-10-08 12:06:01 nkeynes Exp $
3 *
4 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
5 * and DMA).
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #define MODULE asic_module
22 #include <assert.h>
23 #include <stdlib.h>
24 #include "dream.h"
25 #include "mem.h"
26 #include "sh4/intc.h"
27 #include "sh4/dmac.h"
28 #include "sh4/sh4core.h"
29 #include "dreamcast.h"
30 #include "maple/maple.h"
31 #include "gdrom/ide.h"
32 #include "pvr2/pvr2.h"
33 #include "asic.h"
34 #define MMIO_IMPL
35 #include "asic.h"
36 /*
37 * Open questions:
38 * 1) Does changing the mask after event occurance result in the
39 * interrupt being delivered immediately?
40 * TODO: Logic diagram of ASIC event/interrupt logic.
41 *
42 * ... don't even get me started on the "EXTDMA" page, about which, apparently,
43 * practically nothing is publicly known...
44 */
46 static void asic_check_cleared_events( void );
47 static void asic_init( void );
48 static void asic_reset( void );
49 static uint32_t asic_run_slice( uint32_t nanosecs );
50 static void asic_save_state( FILE *f );
51 static int asic_load_state( FILE *f );
52 static uint32_t g2_update_fifo_status( uint32_t slice_cycle );
54 struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, asic_run_slice,
55 NULL, asic_save_state, asic_load_state };
57 #define G2_BIT5_TICKS 60
58 #define G2_BIT4_TICKS 160
59 #define G2_BIT0_ON_TICKS 120
60 #define G2_BIT0_OFF_TICKS 420
62 struct asic_g2_state {
63 int bit5_off_timer;
64 int bit4_on_timer;
65 int bit4_off_timer;
66 int bit0_on_timer;
67 int bit0_off_timer;
68 };
70 static struct asic_g2_state g2_state;
72 static uint32_t asic_run_slice( uint32_t nanosecs )
73 {
74 g2_update_fifo_status(nanosecs);
75 if( g2_state.bit5_off_timer <= (int32_t)nanosecs ) {
76 g2_state.bit5_off_timer = -1;
77 } else {
78 g2_state.bit5_off_timer -= nanosecs;
79 }
81 if( g2_state.bit4_off_timer <= (int32_t)nanosecs ) {
82 g2_state.bit4_off_timer = -1;
83 } else {
84 g2_state.bit4_off_timer -= nanosecs;
85 }
86 if( g2_state.bit4_on_timer <= (int32_t)nanosecs ) {
87 g2_state.bit4_on_timer = -1;
88 } else {
89 g2_state.bit4_on_timer -= nanosecs;
90 }
92 if( g2_state.bit0_off_timer <= (int32_t)nanosecs ) {
93 g2_state.bit0_off_timer = -1;
94 } else {
95 g2_state.bit0_off_timer -= nanosecs;
96 }
97 if( g2_state.bit0_on_timer <= (int32_t)nanosecs ) {
98 g2_state.bit0_on_timer = -1;
99 } else {
100 g2_state.bit0_on_timer -= nanosecs;
101 }
103 return nanosecs;
104 }
106 static void asic_init( void )
107 {
108 register_io_region( &mmio_region_ASIC );
109 register_io_region( &mmio_region_EXTDMA );
110 asic_reset();
111 }
113 static void asic_reset( void )
114 {
115 memset( &g2_state, 0xFF, sizeof(g2_state) );
116 }
118 static void asic_save_state( FILE *f )
119 {
120 fwrite( &g2_state, sizeof(g2_state), 1, f );
121 }
123 static int asic_load_state( FILE *f )
124 {
125 if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 )
126 return 1;
127 else
128 return 0;
129 }
132 /**
133 * Setup the timers for the 3 FIFO status bits following a write through the G2
134 * bus from the SH4 side. The timing is roughly as follows: (times are
135 * approximate based on software readings - I wouldn't take this as gospel but
136 * it seems to be enough to fool most programs).
137 * 0ns: Bit 5 (Input fifo?) goes high immediately on the write
138 * 40ns: Bit 5 goes low and bit 4 goes high
139 * 120ns: Bit 4 goes low, bit 0 goes high
140 * 240ns: Bit 0 goes low.
141 *
142 * Additional writes while the FIFO is in operation extend the time that the
143 * bits remain high as one might expect, without altering the time at which
144 * they initially go high.
145 */
146 void asic_g2_write_word()
147 {
148 if( g2_state.bit5_off_timer < (int32_t)sh4r.slice_cycle ) {
149 g2_state.bit5_off_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
150 } else {
151 g2_state.bit5_off_timer += G2_BIT5_TICKS;
152 }
154 if( g2_state.bit4_on_timer < (int32_t)sh4r.slice_cycle ) {
155 g2_state.bit4_on_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
156 }
158 if( g2_state.bit4_off_timer < (int32_t)sh4r.slice_cycle ) {
159 g2_state.bit4_off_timer = g2_state.bit4_on_timer + G2_BIT4_TICKS;
160 } else {
161 g2_state.bit4_off_timer += G2_BIT4_TICKS;
162 }
164 if( g2_state.bit0_on_timer < (int32_t)sh4r.slice_cycle ) {
165 g2_state.bit0_on_timer = sh4r.slice_cycle + G2_BIT0_ON_TICKS;
166 }
168 if( g2_state.bit0_off_timer < (int32_t)sh4r.slice_cycle ) {
169 g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
170 } else {
171 g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
172 }
174 MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
175 }
177 static uint32_t g2_update_fifo_status( uint32_t nanos )
178 {
179 uint32_t val = MMIO_READ( ASIC, G2STATUS );
180 if( ((uint32_t)g2_state.bit5_off_timer) <= nanos ) {
181 val = val & (~0x20);
182 g2_state.bit5_off_timer = -1;
183 }
184 if( ((uint32_t)g2_state.bit4_on_timer) <= nanos ) {
185 val = val | 0x10;
186 g2_state.bit4_on_timer = -1;
187 }
188 if( ((uint32_t)g2_state.bit4_off_timer) <= nanos ) {
189 val = val & (~0x10);
190 g2_state.bit4_off_timer = -1;
191 }
193 if( ((uint32_t)g2_state.bit0_on_timer) <= nanos ) {
194 val = val | 0x01;
195 g2_state.bit0_on_timer = -1;
196 }
197 if( ((uint32_t)g2_state.bit0_off_timer) <= nanos ) {
198 val = val & (~0x01);
199 g2_state.bit0_off_timer = -1;
200 }
202 MMIO_WRITE( ASIC, G2STATUS, val );
203 return val;
204 }
206 static int g2_read_status() {
207 return g2_update_fifo_status( sh4r.slice_cycle );
208 }
211 void asic_event( int event )
212 {
213 int offset = ((event&0x60)>>3);
214 int result = (MMIO_READ(ASIC, PIRQ0 + offset)) |= (1<<(event&0x1F));
216 if( result & MMIO_READ(ASIC, IRQA0 + offset) )
217 intc_raise_interrupt( INT_IRQ13 );
218 if( result & MMIO_READ(ASIC, IRQB0 + offset) )
219 intc_raise_interrupt( INT_IRQ11 );
220 if( result & MMIO_READ(ASIC, IRQC0 + offset) )
221 intc_raise_interrupt( INT_IRQ9 );
223 if( event >= 64 ) { /* Third word */
224 asic_event( EVENT_CASCADE2 );
225 } else if( event >= 32 ) { /* Second word */
226 asic_event( EVENT_CASCADE1 );
227 }
228 }
230 void asic_clear_event( int event ) {
231 int offset = ((event&0x60)>>3);
232 uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset) & (~(1<<(event&0x1F)));
233 MMIO_WRITE( ASIC, PIRQ0 + offset, result );
234 if( result == 0 ) {
235 /* clear cascades if necessary */
236 if( event >= 64 ) {
237 MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
238 } else if( event >= 32 ) {
239 MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0xBFFFFFFF );
240 }
241 }
243 asic_check_cleared_events();
244 }
246 void asic_check_cleared_events( )
247 {
248 int i, setA = 0, setB = 0, setC = 0;
249 uint32_t bits;
250 for( i=0; i<3; i++ ) {
251 bits = MMIO_READ( ASIC, PIRQ0 + i );
252 setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
253 setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
254 setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
255 }
256 if( setA == 0 )
257 intc_clear_interrupt( INT_IRQ13 );
258 if( setB == 0 )
259 intc_clear_interrupt( INT_IRQ11 );
260 if( setC == 0 )
261 intc_clear_interrupt( INT_IRQ9 );
262 }
264 void g2_dma_transfer( int channel )
265 {
266 uint32_t offset = channel << 5;
268 if( MMIO_READ( EXTDMA, G2DMA0CTL1 + offset ) == 1 ) {
269 if( MMIO_READ( EXTDMA, G2DMA0CTL2 + offset ) == 1 ) {
270 uint32_t extaddr = MMIO_READ( EXTDMA, G2DMA0EXT + offset );
271 uint32_t sh4addr = MMIO_READ( EXTDMA, G2DMA0SH4 + offset );
272 uint32_t length = MMIO_READ( EXTDMA, G2DMA0SIZ + offset ) & 0x1FFFFFFF;
273 uint32_t dir = MMIO_READ( EXTDMA, G2DMA0DIR + offset );
274 // uint32_t mode = MMIO_READ( EXTDMA, G2DMA0MOD + offset );
275 unsigned char buf[length];
276 if( dir == 0 ) { /* SH4 to device */
277 mem_copy_from_sh4( buf, sh4addr, length );
278 mem_copy_to_sh4( extaddr, buf, length );
279 } else { /* Device to SH4 */
280 mem_copy_from_sh4( buf, extaddr, length );
281 mem_copy_to_sh4( sh4addr, buf, length );
282 }
283 MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
284 asic_event( EVENT_G2_DMA0 + channel );
285 } else {
286 MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
287 }
288 }
289 }
291 void asic_ide_dma_transfer( )
292 {
293 if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
294 if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 ) {
295 MMIO_WRITE( EXTDMA, IDEDMATXSIZ, 0 );
297 uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );
298 uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
299 // int dir = MMIO_READ( EXTDMA, IDEDMADIR );
301 uint32_t xfer = ide_read_data_dma( addr, length );
302 MMIO_WRITE( EXTDMA, IDEDMATXSIZ, xfer );
303 MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
304 } else { /* 0 */
305 MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
306 }
307 }
308 }
310 void pvr_dma_transfer( )
311 {
312 sh4addr_t destaddr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
313 uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
314 unsigned char *data = alloca( count );
315 uint32_t rcount = DMAC_get_buffer( 2, data, count );
316 if( rcount != count )
317 WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
319 pvr2_dma_write( destaddr, data, rcount );
321 MMIO_WRITE( ASIC, PVRDMACTL, 0 );
322 MMIO_WRITE( ASIC, PVRDMACNT, 0 );
323 if( destaddr & 0x01000000 ) { /* Write to texture RAM */
324 MMIO_WRITE( ASIC, PVRDMADEST, destaddr + rcount );
325 }
326 asic_event( EVENT_PVR_DMA );
327 }
329 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
330 {
331 switch( reg ) {
332 case PIRQ1:
333 break; /* Treat this as read-only for the moment */
334 case PIRQ0:
335 val = val & 0x3FFFFFFF; /* Top two bits aren't clearable */
336 MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
337 asic_check_cleared_events();
338 break;
339 case PIRQ2:
340 /* Clear any events */
341 val = MMIO_READ(ASIC, reg)&(~val);
342 MMIO_WRITE( ASIC, reg, val );
343 if( val == 0 ) { /* all clear - clear the cascade bit */
344 MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
345 }
346 asic_check_cleared_events();
347 break;
348 case SYSRESET:
349 if( val == 0x7611 ) {
350 dreamcast_reset();
351 sh4r.new_pc = sh4r.pc;
352 } else {
353 WARN( "Unknown value %08X written to SYSRESET port", val );
354 }
355 break;
356 case MAPLE_STATE:
357 MMIO_WRITE( ASIC, reg, val );
358 if( val & 1 ) {
359 uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
360 maple_handle_buffer( maple_addr );
361 MMIO_WRITE( ASIC, reg, 0 );
362 }
363 break;
364 case PVRDMADEST:
365 MMIO_WRITE( ASIC, reg, (val & 0x03FFFFE0) | 0x10000000 );
366 break;
367 case PVRDMACNT:
368 MMIO_WRITE( ASIC, reg, val & 0x00FFFFE0 );
369 break;
370 case PVRDMACTL: /* Initiate PVR DMA transfer */
371 val = val & 0x01;
372 MMIO_WRITE( ASIC, reg, val );
373 if( val == 1 ) {
374 pvr_dma_transfer();
375 }
376 break;
377 case MAPLE_DMA:
378 MMIO_WRITE( ASIC, reg, val );
379 break;
380 default:
381 MMIO_WRITE( ASIC, reg, val );
382 }
383 }
385 int32_t mmio_region_ASIC_read( uint32_t reg )
386 {
387 int32_t val;
388 switch( reg ) {
389 /*
390 case 0x89C:
391 sh4_stop();
392 return 0x000000B;
393 */
394 case PIRQ0:
395 case PIRQ1:
396 case PIRQ2:
397 case IRQA0:
398 case IRQA1:
399 case IRQA2:
400 case IRQB0:
401 case IRQB1:
402 case IRQB2:
403 case IRQC0:
404 case IRQC1:
405 case IRQC2:
406 case MAPLE_STATE:
407 val = MMIO_READ(ASIC, reg);
408 return val;
409 case G2STATUS:
410 return g2_read_status();
411 default:
412 val = MMIO_READ(ASIC, reg);
413 return val;
414 }
416 }
418 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
419 {
420 if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
421 return; /* disabled */
422 }
424 switch( reg ) {
425 case IDEALTSTATUS: /* Device control */
426 ide_write_control( val );
427 break;
428 case IDEDATA:
429 ide_write_data_pio( val );
430 break;
431 case IDEFEAT:
432 if( ide_can_write_regs() )
433 idereg.feature = (uint8_t)val;
434 break;
435 case IDECOUNT:
436 if( ide_can_write_regs() )
437 idereg.count = (uint8_t)val;
438 break;
439 case IDELBA0:
440 if( ide_can_write_regs() )
441 idereg.lba0 = (uint8_t)val;
442 break;
443 case IDELBA1:
444 if( ide_can_write_regs() )
445 idereg.lba1 = (uint8_t)val;
446 break;
447 case IDELBA2:
448 if( ide_can_write_regs() )
449 idereg.lba2 = (uint8_t)val;
450 break;
451 case IDEDEV:
452 if( ide_can_write_regs() )
453 idereg.device = (uint8_t)val;
454 break;
455 case IDECMD:
456 if( ide_can_write_regs() || val == IDE_CMD_NOP ) {
457 ide_write_command( (uint8_t)val );
458 }
459 break;
460 case IDEDMASH4:
461 MMIO_WRITE( EXTDMA, reg, val & 0x1FFFFFE0 );
462 break;
463 case IDEDMASIZ:
464 MMIO_WRITE( EXTDMA, reg, val & 0x01FFFFFE );
465 break;
466 case IDEDMACTL1:
467 case IDEDMACTL2:
468 MMIO_WRITE( EXTDMA, reg, val & 0x01 );
469 asic_ide_dma_transfer( );
470 break;
471 case IDEACTIVATE:
472 if( val == 0x001FFFFF ) {
473 idereg.interface_enabled = TRUE;
474 /* Conventional wisdom says that this is necessary but not
475 * sufficient to enable the IDE interface.
476 */
477 } else if( val == 0x000042FE ) {
478 idereg.interface_enabled = FALSE;
479 }
480 break;
481 case G2DMA0CTL1:
482 case G2DMA0CTL2:
483 MMIO_WRITE( EXTDMA, reg, val );
484 g2_dma_transfer( 0 );
485 break;
486 case G2DMA0STOP:
487 break;
488 case G2DMA1CTL1:
489 case G2DMA1CTL2:
490 MMIO_WRITE( EXTDMA, reg, val );
491 g2_dma_transfer( 1 );
492 break;
494 case G2DMA1STOP:
495 break;
496 case G2DMA2CTL1:
497 case G2DMA2CTL2:
498 MMIO_WRITE( EXTDMA, reg, val );
499 g2_dma_transfer( 2 );
500 break;
501 case G2DMA2STOP:
502 break;
503 case G2DMA3CTL1:
504 case G2DMA3CTL2:
505 MMIO_WRITE( EXTDMA, reg, val );
506 g2_dma_transfer( 3 );
507 break;
508 case G2DMA3STOP:
509 break;
510 case PVRDMA2CTL1:
511 case PVRDMA2CTL2:
512 if( val != 0 ) {
513 ERROR( "Write to unimplemented DMA control register %08X", reg );
514 //dreamcast_stop();
515 //sh4_stop();
516 }
517 break;
518 default:
519 MMIO_WRITE( EXTDMA, reg, val );
520 }
521 }
523 MMIO_REGION_READ_FN( EXTDMA, reg )
524 {
525 uint32_t val;
526 if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
527 return 0xFFFFFFFF; /* disabled */
528 }
530 switch( reg ) {
531 case IDEALTSTATUS:
532 val = idereg.status;
533 return val;
534 case IDEDATA: return ide_read_data_pio( );
535 case IDEFEAT: return idereg.error;
536 case IDECOUNT:return idereg.count;
537 case IDELBA0: return ide_get_drive_status();
538 case IDELBA1: return idereg.lba1;
539 case IDELBA2: return idereg.lba2;
540 case IDEDEV: return idereg.device;
541 case IDECMD:
542 val = ide_read_status();
543 return val;
544 default:
545 val = MMIO_READ( EXTDMA, reg );
546 return val;
547 }
548 }
.