4 * ARM7TDMI CPU emulation core.
6 * Copyright (c) 2005 Nathan Keynes.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #define MODULE aica_module
21 #include "dreamcast.h"
24 #include "aica/armcore.h"
25 #include "aica/aica.h"
27 #define STM_R15_OFFSET 12
29 struct arm_registers armr;
31 void arm_set_mode( int mode );
33 uint32_t arm_exceptions[][2] = {{ MODE_SVC, 0x00000000 },
34 { MODE_UND, 0x00000004 },
35 { MODE_SVC, 0x00000008 },
36 { MODE_ABT, 0x0000000C },
37 { MODE_ABT, 0x00000010 },
38 { MODE_IRQ, 0x00000018 },
39 { MODE_FIQ, 0x0000001C } };
42 #define EXC_UNDEFINED 1
43 #define EXC_SOFTWARE 2
44 #define EXC_PREFETCH_ABORT 3
45 #define EXC_DATA_ABORT 4
47 #define EXC_FAST_IRQ 6
49 uint32_t arm_cpu_freq = ARM_BASE_RATE;
50 uint32_t arm_cpu_period = 1000 / ARM_BASE_RATE;
52 #define CYCLES_PER_SAMPLE ((ARM_BASE_RATE * 1000000) / AICA_SAMPLE_RATE)
54 static struct breakpoint_struct arm_breakpoints[MAX_BREAKPOINTS];
55 static int arm_breakpoint_count = 0;
57 void arm_set_breakpoint( uint32_t pc, breakpoint_type_t type )
59 arm_breakpoints[arm_breakpoint_count].address = pc;
60 arm_breakpoints[arm_breakpoint_count].type = type;
61 arm_breakpoint_count++;
64 gboolean arm_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
68 for( i=0; i<arm_breakpoint_count; i++ ) {
69 if( arm_breakpoints[i].address == pc &&
70 arm_breakpoints[i].type == type ) {
71 while( ++i < arm_breakpoint_count ) {
72 arm_breakpoints[i-1].address = arm_breakpoints[i].address;
73 arm_breakpoints[i-1].type = arm_breakpoints[i].type;
75 arm_breakpoint_count--;
82 int arm_get_breakpoint( uint32_t pc )
85 for( i=0; i<arm_breakpoint_count; i++ ) {
86 if( arm_breakpoints[i].address == pc )
87 return arm_breakpoints[i].type;
92 uint32_t arm_run_slice( uint32_t num_samples )
99 for( i=0; i<num_samples; i++ ) {
100 for( j=0; j < CYCLES_PER_SAMPLE; j++ ) {
102 if( !arm_execute_instruction() )
104 #ifdef ENABLE_DEBUG_MODE
105 for( k=0; k<arm_breakpoint_count; k++ ) {
106 if( arm_breakpoints[k].address == armr.r[15] ) {
108 if( arm_breakpoints[k].type == BREAK_ONESHOT )
109 arm_clear_breakpoint( armr.r[15], BREAK_ONESHOT );
116 k = MMIO_READ( AICA2, AICA_TCR );
117 uint8_t val = MMIO_READ( AICA2, AICA_TIMER );
120 aica_event( AICA_EVENT_TIMER );
121 // MMIO_WRITE( AICA2, AICA_TCR, k & ~0x40 );
123 MMIO_WRITE( AICA2, AICA_TIMER, val );
124 if( !dreamcast_is_running() )
131 void arm_save_state( FILE *f )
133 fwrite( &armr, sizeof(armr), 1, f );
136 int arm_load_state( FILE *f )
138 fread( &armr, sizeof(armr), 1, f );
143 void arm_reset( void )
145 /* Wipe all processor state */
146 memset( &armr, 0, sizeof(armr) );
148 armr.cpsr = MODE_SVC | CPSR_I | CPSR_F;
149 armr.r[15] = 0x00000000;
153 #define SET_CPSR_CONTROL 0x00010000
154 #define SET_CPSR_EXTENSION 0x00020000
155 #define SET_CPSR_STATUS 0x00040000
156 #define SET_CPSR_FLAGS 0x00080000
158 uint32_t arm_get_cpsr( void )
160 /* write back all flags to the cpsr */
161 armr.cpsr = armr.cpsr & CPSR_COMPACT_MASK;
162 if( armr.n ) armr.cpsr |= CPSR_N;
163 if( armr.z ) armr.cpsr |= CPSR_Z;
164 if( armr.c ) armr.cpsr |= CPSR_C;
165 if( armr.v ) armr.cpsr |= CPSR_V;
166 if( armr.t ) armr.cpsr |= CPSR_T;
171 * Return a pointer to the specified register in the user bank,
172 * regardless of the active bank
174 static uint32_t *arm_user_reg( int reg )
176 if( IS_EXCEPTION_MODE() ) {
177 if( reg == 13 || reg == 14 )
178 return &armr.user_r[reg-8];
179 if( IS_FIQ_MODE() ) {
180 if( reg >= 8 || reg <= 12 )
181 return &armr.user_r[reg-8];
187 #define USER_R(n) *arm_user_reg(n)
190 * Set the CPSR to the specified value.
192 * @param value values to set in CPSR
193 * @param fields set of mask values to define which sections of the
194 * CPSR to set (one of the SET_CPSR_* values above)
196 void arm_set_cpsr( uint32_t value, uint32_t fields )
198 if( IS_PRIVILEGED_MODE() ) {
199 if( fields & SET_CPSR_CONTROL ) {
200 int mode = value & CPSR_MODE;
201 arm_set_mode( mode );
202 armr.t = ( value & CPSR_T ); /* Technically illegal to change */
203 armr.cpsr = (armr.cpsr & 0xFFFFFF00) | (value & 0x000000FF);
206 /* Middle 16 bits not currently defined */
208 if( fields & SET_CPSR_FLAGS ) {
209 /* Break flags directly out of given value - don't bother writing
212 armr.n = ( value & CPSR_N );
213 armr.z = ( value & CPSR_Z );
214 armr.c = ( value & CPSR_C );
215 armr.v = ( value & CPSR_V );
219 void arm_set_spsr( uint32_t value, uint32_t fields )
221 /* Only defined if we actually have an SPSR register */
222 if( IS_EXCEPTION_MODE() ) {
223 if( fields & SET_CPSR_CONTROL ) {
224 armr.spsr = (armr.spsr & 0xFFFFFF00) | (value & 0x000000FF);
227 /* Middle 16 bits not currently defined */
229 if( fields & SET_CPSR_FLAGS ) {
230 armr.spsr = (armr.spsr & 0x00FFFFFF) | (value & 0xFF000000);
236 * Raise an ARM exception (other than reset, which uses arm_reset().
237 * @param exception one of the EXC_* exception codes defined above.
239 void arm_raise_exception( int exception )
241 int mode = arm_exceptions[exception][0];
242 uint32_t spsr = arm_get_cpsr();
243 arm_set_mode( mode );
245 armr.r[14] = armr.r[15] + 4;
246 armr.cpsr = (spsr & 0xFFFFFF00) | mode | CPSR_I;
247 if( mode == MODE_FIQ )
249 armr.r[15] = arm_exceptions[exception][1];
252 void arm_restore_cpsr( void )
254 int spsr = armr.spsr;
255 int mode = spsr & CPSR_MODE;
256 arm_set_mode( mode );
258 armr.n = ( spsr & CPSR_N );
259 armr.z = ( spsr & CPSR_Z );
260 armr.c = ( spsr & CPSR_C );
261 armr.v = ( spsr & CPSR_V );
262 armr.t = ( spsr & CPSR_T );
268 * Change the current executing ARM mode to the requested mode.
269 * Saves any required registers to banks and restores those for the
270 * correct mode. (Note does not actually update CPSR at the moment).
272 void arm_set_mode( int targetMode )
274 int currentMode = armr.cpsr & CPSR_MODE;
275 if( currentMode == targetMode )
278 switch( currentMode ) {
281 armr.user_r[5] = armr.r[13];
282 armr.user_r[6] = armr.r[14];
285 armr.svc_r[0] = armr.r[13];
286 armr.svc_r[1] = armr.r[14];
287 armr.svc_r[2] = armr.spsr;
290 armr.abt_r[0] = armr.r[13];
291 armr.abt_r[1] = armr.r[14];
292 armr.abt_r[2] = armr.spsr;
295 armr.und_r[0] = armr.r[13];
296 armr.und_r[1] = armr.r[14];
297 armr.und_r[2] = armr.spsr;
300 armr.irq_r[0] = armr.r[13];
301 armr.irq_r[1] = armr.r[14];
302 armr.irq_r[2] = armr.spsr;
305 armr.fiq_r[0] = armr.r[8];
306 armr.fiq_r[1] = armr.r[9];
307 armr.fiq_r[2] = armr.r[10];
308 armr.fiq_r[3] = armr.r[11];
309 armr.fiq_r[4] = armr.r[12];
310 armr.fiq_r[5] = armr.r[13];
311 armr.fiq_r[6] = armr.r[14];
312 armr.fiq_r[7] = armr.spsr;
313 armr.r[8] = armr.user_r[0];
314 armr.r[9] = armr.user_r[1];
315 armr.r[10] = armr.user_r[2];
316 armr.r[11] = armr.user_r[3];
317 armr.r[12] = armr.user_r[4];
321 switch( targetMode ) {
324 armr.r[13] = armr.user_r[5];
325 armr.r[14] = armr.user_r[6];
328 armr.r[13] = armr.svc_r[0];
329 armr.r[14] = armr.svc_r[1];
330 armr.spsr = armr.svc_r[2];
333 armr.r[13] = armr.abt_r[0];
334 armr.r[14] = armr.abt_r[1];
335 armr.spsr = armr.abt_r[2];
338 armr.r[13] = armr.und_r[0];
339 armr.r[14] = armr.und_r[1];
340 armr.spsr = armr.und_r[2];
343 armr.r[13] = armr.irq_r[0];
344 armr.r[14] = armr.irq_r[1];
345 armr.spsr = armr.irq_r[2];
348 armr.user_r[0] = armr.r[8];
349 armr.user_r[1] = armr.r[9];
350 armr.user_r[2] = armr.r[10];
351 armr.user_r[3] = armr.r[11];
352 armr.user_r[4] = armr.r[12];
353 armr.r[8] = armr.fiq_r[0];
354 armr.r[9] = armr.fiq_r[1];
355 armr.r[10] = armr.fiq_r[2];
356 armr.r[11] = armr.fiq_r[3];
357 armr.r[12] = armr.fiq_r[4];
358 armr.r[13] = armr.fiq_r[5];
359 armr.r[14] = armr.fiq_r[6];
360 armr.spsr = armr.fiq_r[7];
365 /* Page references are as per ARM DDI 0100E (June 2000) */
367 #define MEM_READ_BYTE( addr ) arm_read_byte(addr)
368 #define MEM_READ_WORD( addr ) arm_read_word(addr)
369 #define MEM_READ_LONG( addr ) arm_read_long(addr)
370 #define MEM_WRITE_BYTE( addr, val ) arm_write_byte(addr, val)
371 #define MEM_WRITE_WORD( addr, val ) arm_write_word(addr, val)
372 #define MEM_WRITE_LONG( addr, val ) arm_write_long(addr, val)
375 #define IS_NOTBORROW( result, op1, op2 ) (op2 > op1 ? 0 : 1)
376 #define IS_CARRY( result, op1, op2 ) (result < op1 ? 1 : 0)
377 #define IS_SUBOVERFLOW( result, op1, op2 ) (((op1^op2) & (result^op1)) >> 31)
378 #define IS_ADDOVERFLOW( result, op1, op2 ) (((op1&op2) & (result^op1)) >> 31)
380 #define PC armr.r[15]
382 /* Instruction fields */
383 #define COND(ir) (ir>>28)
384 #define GRP(ir) ((ir>>26)&0x03)
385 #define OPCODE(ir) ((ir>>20)&0x1F)
386 #define IFLAG(ir) (ir&0x02000000)
387 #define SFLAG(ir) (ir&0x00100000)
388 #define PFLAG(ir) (ir&0x01000000)
389 #define UFLAG(ir) (ir&0x00800000)
390 #define BFLAG(ir) (ir&0x00400000)
391 #define WFLAG(ir) (ir&0x00200000)
392 #define LFLAG(ir) SFLAG(ir)
393 #define RN(ir) (armr.r[((ir>>16)&0x0F)] + (((ir>>16)&0x0F) == 0x0F ? 4 : 0))
394 #define RD(ir) (armr.r[((ir>>12)&0x0F)] + (((ir>>12)&0x0F) == 0x0F ? 4 : 0))
395 #define RDn(ir) ((ir>>12)&0x0F)
396 #define RS(ir) (armr.r[((ir>>8)&0x0F)] + (((ir>>8)&0x0F) == 0x0F ? 4 : 0))
397 #define RM(ir) (armr.r[(ir&0x0F)] + (((ir&0x0F) == 0x0F ? 4 : 0)) )
398 #define LRN(ir) armr.r[((ir>>16)&0x0F)]
399 #define LRD(ir) armr.r[((ir>>12)&0x0F)]
400 #define LRS(ir) armr.r[((ir>>8)&0x0F)]
401 #define LRM(ir) armr.r[(ir&0x0F)]
403 #define IMM8(ir) (ir&0xFF)
404 #define IMM12(ir) (ir&0xFFF)
405 #define IMMSPLIT8(ir) (((ir&0xF00)>>4)|(ir&0x0F))
406 #define SHIFTIMM(ir) ((ir>>7)&0x1F)
407 #define IMMROT(ir) ((ir>>7)&0x1E)
408 #define ROTIMM12(ir) ROTATE_RIGHT_LONG(IMM8(ir),IMMROT(ir))
409 #define SIGNEXT24(n) (((n)&0x00800000) ? ((n)|0xFF000000) : ((n)&0x00FFFFFF))
410 #define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
411 #define SIGNEXT16(n) ((int32_t)((int16_t)(n)))
412 #define SHIFT(ir) ((ir>>4)&0x07)
413 #define DISP24(ir) ((ir&0x00FFFFFF))
414 #define UNDEF(ir) do{ arm_raise_exception( EXC_UNDEFINED ); return TRUE; } while(0)
415 #define UNIMP(ir) do{ PC-=4; ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", PC, ir ); dreamcast_stop(); return FALSE; }while(0)
418 * Determine the value of the shift-operand for a data processing instruction,
419 * without determing a value for shift_C (optimized form for instructions that
420 * don't require shift_C ).
421 * @see s5.1 Addressing Mode 1 - Data-processing operands (p A5-2, 218)
423 static uint32_t arm_get_shift_operand( uint32_t ir )
425 uint32_t operand, tmp;
426 if( IFLAG(ir) == 0 ) {
429 case 0: /* (Rm << imm) */
430 operand = operand << SHIFTIMM(ir);
432 case 1: /* (Rm << Rs) */
434 if( tmp > 31 ) operand = 0;
435 else operand = operand << tmp;
437 case 2: /* (Rm >> imm) */
438 operand = operand >> SHIFTIMM(ir);
440 case 3: /* (Rm >> Rs) */
442 if( tmp > 31 ) operand = 0;
443 else operand = operand >> ir;
445 case 4: /* (Rm >>> imm) */
447 if( tmp == 0 ) operand = ((int32_t)operand) >> 31;
448 else operand = ((int32_t)operand) >> tmp;
450 case 5: /* (Rm >>> Rs) */
452 if( tmp > 31 ) operand = ((int32_t)operand) >> 31;
453 else operand = ((int32_t)operand) >> tmp;
457 if( tmp == 0 ) /* RRX aka rotate with carry */
458 operand = (operand >> 1) | (armr.c<<31);
460 operand = ROTATE_RIGHT_LONG(operand,tmp);
464 operand = ROTATE_RIGHT_LONG(operand,tmp);
470 operand = ROTATE_RIGHT_LONG(operand, tmp);
476 * Determine the value of the shift-operand for a data processing instruction,
477 * and set armr.shift_c accordingly.
478 * @see s5.1 Addressing Mode 1 - Data-processing operands (p A5-2, 218)
480 static uint32_t arm_get_shift_operand_s( uint32_t ir )
482 uint32_t operand, tmp;
483 if( IFLAG(ir) == 0 ) {
486 case 0: /* (Rm << imm) */
488 if( tmp == 0 ) { /* Rm */
489 armr.shift_c = armr.c;
490 } else { /* Rm << imm */
491 armr.shift_c = (operand >> (32-tmp)) & 0x01;
492 operand = operand << tmp;
495 case 1: /* (Rm << Rs) */
498 armr.shift_c = armr.c;
501 armr.shift_c = (operand >> (32-tmp)) & 0x01;
502 else armr.shift_c = 0;
504 operand = operand << tmp;
508 case 2: /* (Rm >> imm) */
511 armr.shift_c = operand >> 31;
514 armr.shift_c = (operand >> (tmp-1)) & 0x01;
515 operand = RM(ir) >> tmp;
518 case 3: /* (Rm >> Rs) */
521 armr.shift_c = armr.c;
524 armr.shift_c = (operand >> (tmp-1))&0x01;
525 else armr.shift_c = 0;
527 operand = operand >> tmp;
531 case 4: /* (Rm >>> imm) */
534 armr.shift_c = operand >> 31;
535 operand = -armr.shift_c;
537 armr.shift_c = (operand >> (tmp-1)) & 0x01;
538 operand = ((int32_t)operand) >> tmp;
541 case 5: /* (Rm >>> Rs) */
544 armr.shift_c = armr.c;
547 armr.shift_c = (operand >> (tmp-1))&0x01;
548 operand = ((int32_t)operand) >> tmp;
550 armr.shift_c = operand >> 31;
551 operand = ((int32_t)operand) >> 31;
557 if( tmp == 0 ) { /* RRX aka rotate with carry */
558 armr.shift_c = operand&0x01;
559 operand = (operand >> 1) | (armr.c<<31);
561 armr.shift_c = operand>>(tmp-1);
562 operand = ROTATE_RIGHT_LONG(operand,tmp);
568 armr.shift_c = armr.c;
572 armr.shift_c = operand>>31;
574 armr.shift_c = (operand>>(tmp-1))&0x1;
575 operand = ROTATE_RIGHT_LONG(operand,tmp);
584 armr.shift_c = armr.c;
586 operand = ROTATE_RIGHT_LONG(operand, tmp);
587 armr.shift_c = operand>>31;
594 * Another variant of the shifter code for index-based memory addressing.
595 * Distinguished by the fact that it doesn't support register shifts, and
596 * ignores the I flag (WTF do the load/store instructions use the I flag to
597 * mean the _exact opposite_ of what it means for the data processing
600 static uint32_t arm_get_address_index( uint32_t ir )
602 uint32_t operand = RM(ir);
606 case 0: /* (Rm << imm) */
607 operand = operand << SHIFTIMM(ir);
609 case 2: /* (Rm >> imm) */
610 operand = operand >> SHIFTIMM(ir);
612 case 4: /* (Rm >>> imm) */
614 if( tmp == 0 ) operand = ((int32_t)operand) >> 31;
615 else operand = ((int32_t)operand) >> tmp;
619 if( tmp == 0 ) /* RRX aka rotate with carry */
620 operand = (operand >> 1) | (armr.c<<31);
622 operand = ROTATE_RIGHT_LONG(operand,tmp);
630 * Determine the address operand of a load/store instruction, including
631 * applying any pre/post adjustments to the address registers.
632 * @see s5.2 Addressing Mode 2 - Load and Store Word or Unsigned Byte
633 * @param The instruction word.
634 * @return The calculated address
636 static uint32_t arm_get_address_operand( uint32_t ir )
641 switch( (ir>>21)&0x1D ) {
642 case 0: /* Rn -= imm offset (post-indexed) [5.2.8 A5-28] */
645 LRN(ir) = addr - IMM12(ir);
647 case 4: /* Rn += imm offsett (post-indexed) [5.2.8 A5-28] */
650 LRN(ir) = addr + IMM12(ir);
652 case 8: /* Rn - imm offset [5.2.2 A5-20] */
653 addr = RN(ir) - IMM12(ir);
655 case 9: /* Rn -= imm offset (pre-indexed) [5.2.5 A5-24] */
656 addr = RN(ir) - IMM12(ir);
659 case 12: /* Rn + imm offset [5.2.2 A5-20] */
660 addr = RN(ir) + IMM12(ir);
662 case 13: /* Rn += imm offset [5.2.5 A5-24 ] */
663 addr = RN(ir) + IMM12(ir);
666 case 16: /* Rn -= Rm (post-indexed) [5.2.10 A5-32 ] */
669 LRN(ir) = addr - arm_get_address_index(ir);
671 case 20: /* Rn += Rm (post-indexed) [5.2.10 A5-32 ] */
674 LRN(ir) = addr - arm_get_address_index(ir);
676 case 24: /* Rn - Rm [5.2.4 A5-23] */
677 addr = RN(ir) - arm_get_address_index(ir);
679 case 25: /* RN -= Rm (pre-indexed) [5.2.7 A5-26] */
680 addr = RN(ir) - arm_get_address_index(ir);
683 case 28: /* Rn + Rm [5.2.4 A5-23] */
684 addr = RN(ir) + arm_get_address_index(ir);
686 case 29: /* RN += Rm (pre-indexed) [5.2.7 A5-26] */
687 addr = RN(ir) + arm_get_address_index(ir);
695 * Determine the address operand of a miscellaneous load/store instruction,
696 * including applying any pre/post adjustments to the address registers.
697 * @see s5.3 Addressing Mode 3 - Miscellaneous Loads and Stores
698 * @param The instruction word.
699 * @return The calculated address
701 static uint32_t arm_get_address3_operand( uint32_t ir )
706 switch( (ir>>21)&0x0F ) {
707 case 0: /* Rn -= Rm (post-indexed) [5.3.7 A5-48] */
708 case 1: /* UNPREDICTABLE */
712 case 2: /* Rn -= imm (post-indexed) [5.3.6 A5-46] */
713 case 3: /* UNPREDICTABLE */
715 LRN(ir) -= IMMSPLIT8(ir);
717 case 4: /* Rn += Rm (post-indexed) [5.3.7 A5-48] */
718 case 5: /* UNPREDICTABLE */
722 case 6: /* Rn += imm (post-indexed) [5.3.6 A5-44] */
723 case 7: /* UNPREDICTABLE */
725 LRN(ir) += IMMSPLIT8(ir);
727 case 8: /* Rn - Rm [5.3.3 A5-38] */
728 addr = RN(ir) - RM(ir);
730 case 9: /* Rn -= Rm (pre-indexed) [5.3.5 A5-42] */
731 addr = RN(ir) - RM(ir);
734 case 10: /* Rn - imm offset [5.3.2 A5-36] */
735 addr = RN(ir) - IMMSPLIT8(ir);
737 case 11: /* Rn -= imm offset (pre-indexed) [5.3.4 A5-40] */
738 addr = RN(ir) - IMMSPLIT8(ir);
741 case 12: /* Rn + Rm [5.3.3 A5-38] */
742 addr = RN(ir) + RM(ir);
744 case 13: /* Rn += Rm (pre-indexed) [5.3.5 A5-42] */
745 addr = RN(ir) + RM(ir);
748 case 14: /* Rn + imm offset [5.3.2 A5-36] */
749 addr = RN(ir) + IMMSPLIT8(ir);
751 case 15: /* Rn += imm offset (pre-indexed) [5.3.4 A5-40] */
752 addr = RN(ir) + IMMSPLIT8(ir);
760 gboolean arm_execute_instruction( void )
764 uint32_t operand, operand2, tmp, tmp2, cond;
767 tmp = armr.int_pending & (~armr.cpsr);
770 arm_raise_exception( EXC_FAST_IRQ );
772 arm_raise_exception( EXC_IRQ );
776 ir = MEM_READ_LONG(PC);
781 * Check the condition bits first - if the condition fails return
782 * immediately without actually looking at the rest of the instruction.
810 cond = armr.c && !armr.z;
813 cond = (!armr.c) || armr.z;
816 cond = (armr.n == armr.v);
819 cond = (armr.n != armr.v);
822 cond = (!armr.z) && (armr.n == armr.v);
825 cond = armr.z || (armr.n != armr.v);
838 * Condition passed, now for the actual instructions...
842 if( (ir & 0x0D900000) == 0x01000000 ) {
843 /* Instructions that aren't actual data processing even though
844 * they sit in the DP instruction block.
846 switch( ir & 0x0FF000F0 ) {
847 case 0x01200010: /* BX Rd */
849 armr.r[15] = RM(ir) & 0xFFFFFFFE;
851 case 0x01000000: /* MRS Rd, CPSR */
852 LRD(ir) = arm_get_cpsr();
854 case 0x01400000: /* MRS Rd, SPSR */
857 case 0x01200000: /* MSR CPSR, Rd */
858 arm_set_cpsr( RM(ir), ir );
860 case 0x01600000: /* MSR SPSR, Rd */
861 arm_set_spsr( RM(ir), ir );
863 case 0x03200000: /* MSR CPSR, imm */
864 arm_set_cpsr( ROTIMM12(ir), ir );
866 case 0x03600000: /* MSR SPSR, imm */
867 arm_set_spsr( ROTIMM12(ir), ir );
872 } else if( (ir & 0x0E000090) == 0x00000090 ) {
873 /* Neither are these */
874 switch( (ir>>5)&0x03 ) {
876 /* Arithmetic extension area */
879 LRN(ir) = RM(ir) * RS(ir);
882 tmp = RM(ir) * RS(ir);
888 LRN(ir) = RM(ir) * RS(ir) + RD(ir);
891 tmp = RM(ir) * RS(ir) + RD(ir);
899 case 11: /* UMLALS */
901 case 13: /* SMULLS */
903 case 15: /* SMLALS */
907 tmp = arm_read_long( RN(ir) );
908 switch( RN(ir) & 0x03 ) {
910 tmp = ROTATE_RIGHT_LONG(tmp, 8);
913 tmp = ROTATE_RIGHT_LONG(tmp, 16);
916 tmp = ROTATE_RIGHT_LONG(tmp, 24);
919 arm_write_long( RN(ir), RM(ir) );
923 tmp = arm_read_byte( RN(ir) );
924 arm_write_byte( RN(ir), RM(ir) );
932 operand = arm_get_address3_operand(ir);
933 if( LFLAG(ir) ) { /* LDRH */
934 LRD(ir) = MEM_READ_WORD( operand ) & 0x0000FFFF;
936 MEM_WRITE_WORD( operand, RD(ir) );
940 if( LFLAG(ir) ) { /* LDRSB */
941 operand = arm_get_address3_operand(ir);
942 LRD(ir) = SIGNEXT8( MEM_READ_BYTE( operand ) );
948 if( LFLAG(ir) ) { /* LDRSH */
949 operand = arm_get_address3_operand(ir);
950 LRD(ir) = SIGNEXT16( MEM_READ_WORD( operand ) );
957 /* Data processing */
960 case 0: /* AND Rd, Rn, operand */
961 LRD(ir) = RN(ir) & arm_get_shift_operand(ir);
963 case 1: /* ANDS Rd, Rn, operand */
964 operand = arm_get_shift_operand_s(ir) & RN(ir);
966 if( RDn(ir) == 15 ) {
969 armr.n = operand>>31;
970 armr.z = (operand == 0);
971 armr.c = armr.shift_c;
974 case 2: /* EOR Rd, Rn, operand */
975 LRD(ir) = RN(ir) ^ arm_get_shift_operand(ir);
977 case 3: /* EORS Rd, Rn, operand */
978 operand = arm_get_shift_operand_s(ir) ^ RN(ir);
980 if( RDn(ir) == 15 ) {
983 armr.n = operand>>31;
984 armr.z = (operand == 0);
985 armr.c = armr.shift_c;
988 case 4: /* SUB Rd, Rn, operand */
989 LRD(ir) = RN(ir) - arm_get_shift_operand(ir);
991 case 5: /* SUBS Rd, Rn, operand */
993 operand2 = arm_get_shift_operand(ir);
994 tmp = operand - operand2;
996 if( RDn(ir) == 15 ) {
1000 armr.z = (tmp == 0);
1001 armr.c = IS_NOTBORROW(tmp,operand,operand2);
1002 armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
1005 case 6: /* RSB Rd, operand, Rn */
1006 LRD(ir) = arm_get_shift_operand(ir) - RN(ir);
1008 case 7: /* RSBS Rd, operand, Rn */
1009 operand = arm_get_shift_operand(ir);
1011 tmp = operand - operand2;
1013 if( RDn(ir) == 15 ) {
1017 armr.z = (tmp == 0);
1018 armr.c = IS_NOTBORROW(tmp,operand,operand2);
1019 armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
1022 case 8: /* ADD Rd, Rn, operand */
1023 LRD(ir) = RN(ir) + arm_get_shift_operand(ir);
1025 case 9: /* ADDS Rd, Rn, operand */
1026 operand = arm_get_shift_operand(ir);
1028 tmp = operand + operand2;
1030 if( RDn(ir) == 15 ) {
1034 armr.z = (tmp == 0);
1035 armr.c = IS_CARRY(tmp,operand,operand2);
1036 armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);
1040 LRD(ir) = RN(ir) + arm_get_shift_operand(ir) +
1044 operand = arm_get_shift_operand(ir);
1046 tmp = operand + operand2;
1047 tmp2 = tmp + armr.c ? 1 : 0;
1049 if( RDn(ir) == 15 ) {
1053 armr.z = (tmp == 0 );
1054 armr.c = IS_CARRY(tmp,operand,operand2) ||
1056 armr.v = IS_ADDOVERFLOW(tmp,operand, operand2) ||
1057 ((tmp&0x80000000) != (tmp2&0x80000000));
1061 LRD(ir) = RN(ir) - arm_get_shift_operand(ir) -
1066 operand2 = arm_get_shift_operand(ir);
1067 tmp = operand - operand2;
1068 tmp2 = tmp - (armr.c ? 0 : 1);
1069 if( RDn(ir) == 15 ) {
1073 armr.z = (tmp == 0 );
1074 armr.c = IS_NOTBORROW(tmp,operand,operand2) &&
1076 armr.v = IS_SUBOVERFLOW(tmp,operand,operand2) ||
1077 ((tmp&0x80000000) != (tmp2&0x80000000));
1081 LRD(ir) = arm_get_shift_operand(ir) - RN(ir) -
1085 operand = arm_get_shift_operand(ir);
1087 tmp = operand - operand2;
1088 tmp2 = tmp - (armr.c ? 0 : 1);
1089 if( RDn(ir) == 15 ) {
1093 armr.z = (tmp == 0 );
1094 armr.c = IS_NOTBORROW(tmp,operand,operand2) &&
1096 armr.v = IS_SUBOVERFLOW(tmp,operand,operand2) ||
1097 ((tmp&0x80000000) != (tmp2&0x80000000));
1100 case 17: /* TST Rn, operand */
1101 operand = arm_get_shift_operand_s(ir) & RN(ir);
1102 armr.n = operand>>31;
1103 armr.z = (operand == 0);
1104 armr.c = armr.shift_c;
1106 case 19: /* TEQ Rn, operand */
1107 operand = arm_get_shift_operand_s(ir) ^ RN(ir);
1108 armr.n = operand>>31;
1109 armr.z = (operand == 0);
1110 armr.c = armr.shift_c;
1112 case 21: /* CMP Rn, operand */
1114 operand2 = arm_get_shift_operand(ir);
1115 tmp = operand - operand2;
1117 armr.z = (tmp == 0);
1118 armr.c = IS_NOTBORROW(tmp,operand,operand2);
1119 armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
1121 case 23: /* CMN Rn, operand */
1123 operand2 = arm_get_shift_operand(ir);
1124 tmp = operand + operand2;
1126 armr.z = (tmp == 0);
1127 armr.c = IS_CARRY(tmp,operand,operand2);
1128 armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);
1130 case 24: /* ORR Rd, Rn, operand */
1131 LRD(ir) = RN(ir) | arm_get_shift_operand(ir);
1133 case 25: /* ORRS Rd, Rn, operand */
1134 operand = arm_get_shift_operand_s(ir) | RN(ir);
1136 if( RDn(ir) == 15 ) {
1139 armr.n = operand>>31;
1140 armr.z = (operand == 0);
1141 armr.c = armr.shift_c;
1144 case 26: /* MOV Rd, operand */
1145 LRD(ir) = arm_get_shift_operand(ir);
1147 case 27: /* MOVS Rd, operand */
1148 operand = arm_get_shift_operand_s(ir);
1150 if( RDn(ir) == 15 ) {
1153 armr.n = operand>>31;
1154 armr.z = (operand == 0);
1155 armr.c = armr.shift_c;
1158 case 28: /* BIC Rd, Rn, operand */
1159 LRD(ir) = RN(ir) & (~arm_get_shift_operand(ir));
1161 case 29: /* BICS Rd, Rn, operand */
1162 operand = RN(ir) & (~arm_get_shift_operand_s(ir));
1164 if( RDn(ir) == 15 ) {
1167 armr.n = operand>>31;
1168 armr.z = (operand == 0);
1169 armr.c = armr.shift_c;
1172 case 30: /* MVN Rd, operand */
1173 LRD(ir) = ~arm_get_shift_operand(ir);
1175 case 31: /* MVNS Rd, operand */
1176 operand = ~arm_get_shift_operand_s(ir);
1178 if( RDn(ir) == 15 ) {
1181 armr.n = operand>>31;
1182 armr.z = (operand == 0);
1183 armr.c = armr.shift_c;
1191 case 1: /* Load/store */
1192 operand = arm_get_address_operand(ir);
1193 switch( (ir>>20)&0x17 ) {
1194 case 0: case 16: case 18: /* STR Rd, address */
1195 arm_write_long( operand, RD(ir) );
1197 case 1: case 17: case 19: /* LDR Rd, address */
1198 LRD(ir) = arm_read_long(operand);
1200 case 2: /* STRT Rd, address */
1201 arm_write_long_user( operand, RD(ir) );
1203 case 3: /* LDRT Rd, address */
1204 LRD(ir) = arm_read_long_user( operand );
1206 case 4: case 20: case 22: /* STRB Rd, address */
1207 arm_write_byte( operand, RD(ir) );
1209 case 5: case 21: case 23: /* LDRB Rd, address */
1210 LRD(ir) = arm_read_byte( operand );
1212 case 6: /* STRBT Rd, address */
1213 arm_write_byte_user( operand, RD(ir) );
1215 case 7: /* LDRBT Rd, address */
1216 LRD(ir) = arm_read_byte_user( operand );
1220 case 2: /* Load/store multiple, branch*/
1221 if( (ir & 0x02000000) == 0x02000000 ) { /* B[L] imm24 */
1222 operand = (SIGNEXT24(ir&0x00FFFFFF) << 2);
1223 if( (ir & 0x01000000) == 0x01000000 ) {
1224 armr.r[14] = pc; /* BL */
1226 armr.r[15] = pc + 4 + operand;
1227 } else { /* Load/store multiple */
1228 gboolean needRestore = FALSE;
1231 switch( (ir & 0x01D00000) >> 20 ) {
1234 arm_write_long( operand, armr.r[15]+8 );
1237 for( i=14; i>= 0; i-- ) {
1238 if( (ir & (1<<i)) ) {
1239 arm_write_long( operand, armr.r[i] );
1245 for( i=15; i>= 0; i-- ) {
1246 if( (ir & (1<<i)) ) {
1247 armr.r[i] = arm_read_long( operand );
1252 case 4: /* STMDA (S) */
1254 arm_write_long( operand, armr.r[15]+8 );
1257 for( i=14; i>= 0; i-- ) {
1258 if( (ir & (1<<i)) ) {
1259 arm_write_long( operand, USER_R(i) );
1264 case 5: /* LDMDA (S) */
1265 if( (ir&0x00008000) ) { /* Load PC */
1266 for( i=15; i>= 0; i-- ) {
1267 if( (ir & (1<<i)) ) {
1268 armr.r[i] = arm_read_long( operand );
1274 for( i=15; i>= 0; i-- ) {
1275 if( (ir & (1<<i)) ) {
1276 USER_R(i) = arm_read_long( operand );
1283 for( i=0; i< 15; i++ ) {
1284 if( (ir & (1<<i)) ) {
1285 arm_write_long( operand, armr.r[i] );
1290 arm_write_long( operand, armr.r[15]+8 );
1295 for( i=0; i< 16; i++ ) {
1296 if( (ir & (1<<i)) ) {
1297 armr.r[i] = arm_read_long( operand );
1302 case 12: /* STMIA (S) */
1303 for( i=0; i< 15; i++ ) {
1304 if( (ir & (1<<i)) ) {
1305 arm_write_long( operand, USER_R(i) );
1310 arm_write_long( operand, armr.r[15]+8 );
1314 case 13: /* LDMIA (S) */
1315 if( (ir&0x00008000) ) { /* Load PC */
1316 for( i=0; i < 16; i++ ) {
1317 if( (ir & (1<<i)) ) {
1318 armr.r[i] = arm_read_long( operand );
1324 for( i=0; i < 16; i++ ) {
1325 if( (ir & (1<<i)) ) {
1326 USER_R(i) = arm_read_long( operand );
1332 case 16: /* STMDB */
1335 arm_write_long( operand, armr.r[15]+8 );
1337 for( i=14; i>= 0; i-- ) {
1338 if( (ir & (1<<i)) ) {
1340 arm_write_long( operand, armr.r[i] );
1344 case 17: /* LDMDB */
1345 for( i=15; i>= 0; i-- ) {
1346 if( (ir & (1<<i)) ) {
1348 armr.r[i] = arm_read_long( operand );
1352 case 20: /* STMDB (S) */
1355 arm_write_long( operand, armr.r[15]+8 );
1357 for( i=14; i>= 0; i-- ) {
1358 if( (ir & (1<<i)) ) {
1360 arm_write_long( operand, USER_R(i) );
1364 case 21: /* LDMDB (S) */
1365 if( (ir&0x00008000) ) { /* Load PC */
1366 for( i=15; i>= 0; i-- ) {
1367 if( (ir & (1<<i)) ) {
1369 armr.r[i] = arm_read_long( operand );
1374 for( i=15; i>= 0; i-- ) {
1375 if( (ir & (1<<i)) ) {
1377 USER_R(i) = arm_read_long( operand );
1382 case 24: /* STMIB */
1383 for( i=0; i< 15; i++ ) {
1384 if( (ir & (1<<i)) ) {
1386 arm_write_long( operand, armr.r[i] );
1391 arm_write_long( operand, armr.r[15]+8 );
1394 case 25: /* LDMIB */
1395 for( i=0; i< 16; i++ ) {
1396 if( (ir & (1<<i)) ) {
1398 armr.r[i] = arm_read_long( operand );
1402 case 28: /* STMIB (S) */
1403 for( i=0; i< 15; i++ ) {
1404 if( (ir & (1<<i)) ) {
1406 arm_write_long( operand, USER_R(i) );
1411 arm_write_long( operand, armr.r[15]+8 );
1414 case 29: /* LDMIB (S) */
1415 if( (ir&0x00008000) ) { /* Load PC */
1416 for( i=0; i < 16; i++ ) {
1417 if( (ir & (1<<i)) ) {
1419 armr.r[i] = arm_read_long( operand );
1424 for( i=0; i < 16; i++ ) {
1425 if( (ir & (1<<i)) ) {
1427 USER_R(i) = arm_read_long( operand );
1441 if( (ir & 0x0F000000) == 0x0F000000 ) { /* SWI */
1442 arm_raise_exception( EXC_SOFTWARE );
1451 if( armr.r[15] >= 0x00200000 ) {
1452 armr.running = FALSE;
1453 WARN( "ARM Halted: BRANCH to invalid address %08X at %08X", armr.r[15], pc );
.