filename | src/aica/armcore.h |
changeset | 35:21a4be098304 |
prev | 30:89b30313d757 |
next | 37:1d84f4c18816 |
author | nkeynes |
date | Mon Dec 26 03:54:55 2005 +0000 (18 years ago) |
permissions | -rw-r--r-- |
last change | Remove modules.h - move definitions into dream.h Add source string to output list (taken from module name) ARM Work in progress |
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1 /**
2 * $Id: armcore.h,v 1.7 2005-12-26 03:54:55 nkeynes Exp $
3 *
4 * Interface definitions for the ARM CPU emulation core proper.
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
19 #ifndef dream_armcore_H
20 #define dream_armcore_H 1
22 #include "dream.h"
23 #include <stdint.h>
24 #include <stdio.h>
26 #define ARM_BASE_RATE 33 /* MHZ */
27 extern uint32_t arm_cpu_freq;
28 extern uint32_t arm_cpu_period;
30 #define ROTATE_RIGHT_LONG(operand,shift) ((((uint32_t)operand) >> shift) | ((operand<<(32-shift))) )
32 struct arm_registers {
33 uint32_t r[16]; /* Current register bank */
35 uint32_t cpsr;
36 uint32_t spsr;
38 /* Various banked versions of the registers. Note that these are used
39 * to save the registers for the named bank when leaving the mode, they're
40 * not actually used actively.
41 **/
42 uint32_t user_r[7]; /* User/System bank 8..14 */
43 uint32_t svc_r[3]; /* SVC bank 13..14, SPSR */
44 uint32_t abt_r[3]; /* ABT bank 13..14, SPSR */
45 uint32_t und_r[3]; /* UND bank 13..14, SPSR */
46 uint32_t irq_r[3]; /* IRQ bank 13..14, SPSR */
47 uint32_t fiq_r[8]; /* FIQ bank 8..14, SPSR */
49 uint32_t c,n,z,v,t;
51 /* "fake" registers */
52 uint32_t shift_c; /* used for temporary storage of shifter results */
53 uint32_t icount; /* Instruction counter */
54 };
56 #define CPSR_N 0x80000000 /* Negative flag */
57 #define CPSR_Z 0x40000000 /* Zero flag */
58 #define CPSR_C 0x20000000 /* Carry flag */
59 #define CPSR_V 0x10000000 /* Overflow flag */
60 #define CPSR_I 0x00000080 /* Interrupt disable bit */
61 #define CPSR_F 0x00000040 /* Fast interrupt disable bit */
62 #define CPSR_T 0x00000020 /* Thumb mode */
63 #define CPSR_MODE 0x0000001F /* Current execution mode */
65 #define MODE_USER 0x10 /* User mode */
66 #define MODE_FIQ 0x11 /* Fast IRQ mode */
67 #define MODE_IRQ 0x12 /* IRQ mode */
68 #define MODE_SVC 0x13 /* Supervisor mode */
69 #define MODE_ABT 0x17 /* Abort mode */
70 #define MODE_UND 0x1B /* Undefined mode */
71 #define MODE_SYS 0x1F /* System mode */
73 extern struct arm_registers armr;
75 #define CARRY_FLAG (armr.cpsr&CPSR_C)
77 /* ARM core functions */
78 void arm_reset( void );
79 uint32_t arm_run_slice( uint32_t nanosecs );
80 void arm_save_state( FILE *f );
81 int arm_load_state( FILE *f );
82 gboolean arm_execute_instruction( void );
84 /* ARM Memory */
85 int32_t arm_read_long( uint32_t addr );
86 int32_t arm_read_word( uint32_t addr );
87 int32_t arm_read_byte( uint32_t addr );
88 void arm_write_long( uint32_t addr, uint32_t val );
89 void arm_write_word( uint32_t addr, uint32_t val );
90 void arm_write_byte( uint32_t addr, uint32_t val );
91 int32_t arm_read_phys_word( uint32_t addr );
92 int arm_has_page( uint32_t addr );
94 #endif /* !dream_armcore_H */
.