lxdream 0.9.1| filename | src/sh4/sh4core.h |
| changeset | 32:bf0bc2c524b8 |
| prev | 30:89b30313d757 |
| next | 43:0cf3e339cc59 |
| author | nkeynes |
| date | Mon Dec 26 03:54:55 2005 +0000 (18 years ago) |
| permissions | -rw-r--r-- |
| last change | Remove modules.h - move definitions into dream.h Add source string to output list (taken from module name) ARM Work in progress |
| view | annotate | diff | log | raw |
1 /**
2 * $Id: sh4core.h,v 1.7 2005-12-26 03:10:23 nkeynes Exp $
3 *
4 * This file defines the public functions exported by the SH4 core, except
5 * for disassembly functions defined in sh4dasm.h
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #ifndef sh4core_H
21 #define sh4core_H 1
23 #include <glib/gtypes.h>
24 #include <stdint.h>
25 #include <stdio.h>
27 #ifdef __cplusplus
28 extern "C" {
29 #if 0
30 }
31 #endif
32 #endif
35 /**
36 * SH4 is running normally
37 */
38 #define SH4_STATE_RUNNING 1
39 /**
40 * SH4 is not executing instructions but all peripheral modules are still
41 * running
42 */
43 #define SH4_STATE_SLEEP 2
44 /**
45 * SH4 is not executing instructions, DMAC is halted, but all other peripheral
46 * modules are still running
47 */
48 #define SH4_STATE_DEEP_SLEEP 3
49 /**
50 * SH4 is not executing instructions and all peripheral modules are also
51 * stopped. As close as you can get to powered-off without actually being
52 * off.
53 */
54 #define SH4_STATE_STANDBY 4
57 struct sh4_registers {
58 uint32_t r[16];
59 uint32_t r_bank[8]; /* hidden banked registers */
60 uint32_t sr, gbr, ssr, spc, sgr, dbr, vbr;
61 uint32_t pr, pc, fpul, fpscr;
62 uint64_t mac;
63 uint32_t m, q, s, t; /* really boolean - 0 or 1 */
64 float fr[2][16];
66 int32_t store_queue[16]; /* technically 2 banks of 32 bytes */
68 uint32_t new_pc; /* Not a real register, but used to handle delay slots */
69 uint32_t icount; /* Also not a real register, instruction counter */
70 uint32_t int_pending; /* flag set by the INTC = pending priority level */
71 int in_delay_slot; /* flag to indicate the current instruction is in
72 * a delay slot (certain rules apply) */
73 int sh4_state; /* Current power-on state (one of the SH4_STATE_* values ) */
74 };
76 extern struct sh4_registers sh4r;
78 /* Public functions */
80 void sh4_init( void );
81 void sh4_reset( void );
82 void sh4_run( void );
83 void sh4_runto( uint32_t pc, uint32_t count );
84 void sh4_runfor( uint32_t count );
85 int sh4_isrunning( void );
86 void sh4_stop( void );
87 void sh4_set_pc( int );
88 gboolean sh4_execute_instruction( void );
89 void sh4_raise_exception( int, int );
90 void sh4_set_breakpoint( uint32_t pc, int type );
92 #define BREAK_ONESHOT 1
93 #define BREAK_PERM 2
95 /* SH4 Memory */
96 int32_t sh4_read_long( uint32_t addr );
97 int32_t sh4_read_word( uint32_t addr );
98 int32_t sh4_read_byte( uint32_t addr );
99 void sh4_write_long( uint32_t addr, uint32_t val );
100 void sh4_write_word( uint32_t addr, uint32_t val );
101 void sh4_write_byte( uint32_t addr, uint32_t val );
102 int32_t sh4_read_phys_word( uint32_t addr );
104 /* Peripheral functions */
105 void DMAC_run_slice( uint32_t );
106 void TMU_run_slice( uint32_t );
107 void SCIF_reset( void );
108 void SCIF_run_slice( uint32_t );
109 void SCIF_save_state( FILE *f );
110 int SCIF_load_state( FILE *f );
112 #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
113 #define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
114 #define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20)
115 #define SIGNEXT16(n) ((int32_t)((int16_t)(n)))
116 #define SIGNEXT32(n) ((int64_t)((int32_t)(n)))
117 #define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16)
119 /* Status Register (SR) bits */
120 #define SR_MD 0x40000000 /* Processor mode ( User=0, Privileged=1 ) */
121 #define SR_RB 0x20000000 /* Register bank (priviledged mode only) */
122 #define SR_BL 0x10000000 /* Exception/interupt block (1 = masked) */
123 #define SR_FD 0x00008000 /* FPU disable */
124 #define SR_M 0x00000200
125 #define SR_Q 0x00000100
126 #define SR_IMASK 0x000000F0 /* Interrupt mask level */
127 #define SR_S 0x00000002 /* Saturation operation for MAC instructions */
128 #define SR_T 0x00000001 /* True/false or carry/borrow */
129 #define SR_MASK 0x700083F3
130 #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */
132 #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)
133 #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)
134 #define SH4_INT_PENDING() (sh4r.int_pending && !sh4r.in_delay_slot)
136 #define FPSCR_FR 0x00200000 /* FPU register bank */
137 #define FPSCR_SZ 0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
138 #define FPSCR_PR 0x00080000 /* Precision (0=32 bites, 1=64 bits) */
139 #define FPSCR_DN 0x00040000 /* Denormalization mode (1 = treat as 0) */
140 #define FPSCR_CAUSE 0x0003F000
141 #define FPSCR_ENABLE 0x00000F80
142 #define FPSCR_FLAG 0x0000007C
143 #define FPSCR_RM 0x00000003 /* Rounding mode (0=nearest, 1=to zero) */
145 #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR)
146 #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
147 #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
149 #define FR sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21]
150 #define XF sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21]
152 /* Exceptions (for use with sh4_raise_exception) */
154 #define EX_ILLEGAL_INSTRUCTION 0x180, 0x100
155 #define EX_SLOT_ILLEGAL 0x1A0, 0x100
156 #define EX_TLB_MISS_READ 0x040, 0x400
157 #define EX_TLB_MISS_WRITE 0x060, 0x400
158 #define EX_INIT_PAGE_WRITE 0x080, 0x100
159 #define EX_TLB_PROT_READ 0x0A0, 0x100
160 #define EX_TLB_PROT_WRITE 0x0C0, 0x100
161 #define EX_DATA_ADDR_READ 0x0E0, 0x100
162 #define EX_DATA_ADDR_WRITE 0x100, 0x100
163 #define EX_FPU_EXCEPTION 0x120, 0x100
164 #define EX_TRAPA 0x160, 0x100
165 #define EX_BREAKPOINT 0x1E0, 0x100
166 #define EX_FPU_DISABLED 0x800, 0x100
167 #define EX_SLOT_FPU_DISABLED 0x820, 0x100
169 #define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val;
171 #ifdef __cplusplus
172 }
173 #endif
174 #endif
.