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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 133:249aeda31f02
prev127:4ba79389bb6d
next144:7f0714e89aaa
author nkeynes
date Thu Mar 30 11:30:59 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Unfubar the pvr event generation
Move state into pvr2_state structure for ease of save/load
view annotate diff log raw
     1 /**
     2  * $Id: pvr2.c,v 1.22 2006-03-30 11:30:59 nkeynes Exp $
     3  *
     4  * PVR2 (Video) Core module implementation and MMIO registers.
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    18 #define MODULE pvr2_module
    20 #include "dream.h"
    21 #include "video.h"
    22 #include "mem.h"
    23 #include "asic.h"
    24 #include "pvr2/pvr2.h"
    25 #include "sh4/sh4core.h"
    26 #define MMIO_IMPL
    27 #include "pvr2/pvr2mmio.h"
    29 char *video_base;
    31 static void pvr2_init( void );
    32 static void pvr2_reset( void );
    33 static uint32_t pvr2_run_slice( uint32_t );
    34 static void pvr2_save_state( FILE *f );
    35 static int pvr2_load_state( FILE *f );
    37 void pvr2_display_frame( void );
    39 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
    40 					pvr2_run_slice, NULL,
    41 					pvr2_save_state, pvr2_load_state };
    44 video_driver_t video_driver = NULL;
    46 struct video_timing {
    47     int fields_per_second;
    48     int total_lines;
    49     int retrace_lines;
    50     int line_time_ns;
    51 };
    53 struct video_timing pal_timing = { 50, 625, 65, 32000 };
    54 struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
    56 struct pvr2_state {
    57     uint32_t frame_count;
    58     uint32_t line_count;
    59     uint32_t line_remainder;
    60     uint32_t irq_vpos1;
    61     uint32_t irq_vpos2;
    62     gboolean retrace;
    63     struct video_timing timing;
    64 } pvr2_state;
    66 struct video_buffer video_buffer[2];
    67 int video_buffer_idx = 0;
    69 static void pvr2_init( void )
    70 {
    71     register_io_region( &mmio_region_PVR2 );
    72     register_io_region( &mmio_region_PVR2PAL );
    73     register_io_region( &mmio_region_PVR2TA );
    74     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
    75     texcache_init();
    76     pvr2_reset();
    77 }
    79 static void pvr2_reset( void )
    80 {
    81     pvr2_state.line_count = 0;
    82     pvr2_state.line_remainder = 0;
    83     pvr2_state.irq_vpos1 = 0;
    84     pvr2_state.irq_vpos2 = 0;
    85     pvr2_state.retrace = FALSE;
    86     pvr2_state.timing = ntsc_timing;
    87     video_buffer_idx = 0;
    89     pvr2_ta_init();
    90     pvr2_render_init();
    91     texcache_flush();
    92 }
    94 static void pvr2_save_state( FILE *f )
    95 {
    96     fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
    97 }
    99 static int pvr2_load_state( FILE *f )
   100 {
   101     fread( &pvr2_state, sizeof(pvr2_state), 1, f );
   102 }
   104 static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
   105 {
   106     pvr2_state.line_remainder += nanosecs;
   107     while( pvr2_state.line_remainder >= pvr2_state.timing.line_time_ns ) {
   108 	pvr2_state.line_remainder -= pvr2_state.timing.line_time_ns;
   110 	pvr2_state.line_count++;
   111 	if( pvr2_state.line_count == pvr2_state.timing.total_lines ) {
   112 	    asic_event( EVENT_RETRACE );
   113 	    pvr2_state.line_count = 0;
   114 	    pvr2_state.retrace = TRUE;
   115 	}
   117 	if( pvr2_state.line_count == pvr2_state.irq_vpos1 ) {
   118 	    asic_event( EVENT_SCANLINE1 );
   119 	} 
   120 	if( pvr2_state.line_count == pvr2_state.irq_vpos2 ) {
   121 	    asic_event( EVENT_SCANLINE2 );
   122 	}
   124 	if( pvr2_state.line_count == pvr2_state.timing.retrace_lines ) {
   125 	    if( pvr2_state.retrace ) {
   126 		pvr2_display_frame();
   127 		pvr2_state.retrace = FALSE;
   128 	    }
   129 	}
   130     }
   131     return nanosecs;
   132 }
   134 int pvr2_get_frame_count() 
   135 {
   136     return pvr2_state.frame_count;
   137 }
   139 void video_set_driver( video_driver_t driver )
   140 {
   141     if( video_driver != NULL && video_driver->shutdown_driver != NULL )
   142 	video_driver->shutdown_driver();
   144     video_driver = driver;
   145     if( driver->init_driver != NULL )
   146 	driver->init_driver();
   147     driver->set_display_format( 640, 480, COLFMT_RGB32 );
   148     driver->set_render_format( 640, 480, COLFMT_RGB32, FALSE );
   149     texcache_gl_init();
   150 }
   152 /**
   153  * Display the next frame, copying the current contents of video ram to
   154  * the window. If the video configuration has changed, first recompute the
   155  * new frame size/depth.
   156  */
   157 void pvr2_display_frame( void )
   158 {
   159     uint32_t display_addr = MMIO_READ( PVR2, DISPADDR1 );
   161     int dispsize = MMIO_READ( PVR2, DISPSIZE );
   162     int dispmode = MMIO_READ( PVR2, DISPMODE );
   163     int vidcfg = MMIO_READ( PVR2, DISPCFG );
   164     int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
   165     int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
   166     int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
   167     gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
   168     gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
   169     if( bEnabled ) {
   170 	video_buffer_t buffer = &video_buffer[video_buffer_idx];
   171 	video_buffer_idx = !video_buffer_idx;
   172 	video_buffer_t last = &video_buffer[video_buffer_idx];
   173 	buffer->rowstride = (vid_ppl + vid_stride) << 2;
   174 	buffer->data = video_base + MMIO_READ( PVR2, DISPADDR1 );
   175 	buffer->vres = vid_lpf;
   176 	if( interlaced ) buffer->vres <<= 1;
   177 	switch( (dispmode & DISPMODE_COL) >> 2 ) {
   178 	case 0: 
   179 	    buffer->colour_format = COLFMT_ARGB1555;
   180 	    buffer->hres = vid_ppl << 1; 
   181 	    break;
   182 	case 1: 
   183 	    buffer->colour_format = COLFMT_RGB565;
   184 	    buffer->hres = vid_ppl << 1; 
   185 	    break;
   186 	case 2:
   187 	    buffer->colour_format = COLFMT_RGB888;
   188 	    buffer->hres = (vid_ppl << 2) / 3; 
   189 	    break;
   190 	case 3: 
   191 	    buffer->colour_format = COLFMT_ARGB8888;
   192 	    buffer->hres = vid_ppl; 
   193 	    break;
   194 	}
   196 	if( video_driver != NULL ) {
   197 	    if( buffer->hres != last->hres ||
   198 		buffer->vres != last->vres ||
   199 		buffer->colour_format != last->colour_format) {
   200 		video_driver->set_display_format( buffer->hres, buffer->vres,
   201 						  buffer->colour_format );
   202 	    }
   203 	    if( MMIO_READ( PVR2, DISPCFG2 ) & 0x08 ) { /* Blanked */
   204 		uint32_t colour = MMIO_READ( PVR2, DISPBORDER );
   205 		video_driver->display_blank_frame( colour );
   206 	    } else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
   207 		video_driver->display_frame( buffer );
   208 	    }
   209 	}
   210     } else {
   211 	video_buffer_idx = 0;
   212 	video_buffer[0].hres = video_buffer[0].vres = 0;
   213     }
   214     pvr2_state.frame_count++;
   215 }
   217 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
   218 {
   219     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
   220         MMIO_WRITE( PVR2, reg, val );
   221         /* I don't want to hear about these */
   222         return;
   223     }
   225     INFO( "PVR2 write to %08X <= %08X [%s: %s]", reg, val, 
   226           MMIO_REGID(PVR2,reg), MMIO_REGDESC(PVR2,reg) );
   228     MMIO_WRITE( PVR2, reg, val );
   230     switch(reg) {
   231     case DISPADDR1:
   232 	if( pvr2_state.retrace ) {
   233 	    pvr2_display_frame();
   234 	    pvr2_state.retrace = FALSE;
   235 	}
   236 	break;
   237     case VPOS_IRQ:
   238 	pvr2_state.irq_vpos1 = (val >> 16) & 0x03FF;
   239 	pvr2_state.irq_vpos2 = val & 0x03FF;
   240 	break;
   241     case TAINIT:
   242 	if( val & 0x80000000 )
   243 	    pvr2_ta_init();
   244 	break;
   245     case RENDSTART:
   246 	if( val == 0xFFFFFFFF )
   247 	    pvr2_render_scene();
   248 	break;
   249     }
   250 }
   252 MMIO_REGION_READ_FN( PVR2, reg )
   253 {
   254     switch( reg ) {
   255         case BEAMPOS:
   256             return sh4r.icount&0x20 ? 0x2000 : 1;
   257         default:
   258             return MMIO_READ( PVR2, reg );
   259     }
   260 }
   262 MMIO_REGION_DEFFNS( PVR2PAL )
   264 void pvr2_set_base_address( uint32_t base ) 
   265 {
   266     mmio_region_PVR2_write( DISPADDR1, base );
   267 }
   272 int32_t mmio_region_PVR2TA_read( uint32_t reg )
   273 {
   274     return 0xFFFFFFFF;
   275 }
   277 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
   278 {
   279     pvr2_ta_write( &val, sizeof(uint32_t) );
   280 }
   283 void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
   284 {
   285     int bank_flag = (destaddr & 0x04) >> 2;
   286     uint32_t *banks[2];
   287     uint32_t *dwsrc;
   288     int i;
   290     destaddr = destaddr & 0x7FFFFF;
   291     if( destaddr + length > 0x800000 ) {
   292 	length = 0x800000 - destaddr;
   293     }
   295     for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
   296 	texcache_invalidate_page( i );
   297     }
   299     banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1)));
   300     banks[1] = banks[0] + 0x100000;
   301     if( bank_flag ) 
   302 	banks[0]++;
   304     /* Handle non-aligned start of source */
   305     if( destaddr & 0x03 ) {
   306 	char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
   307 	for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
   308 	    *dest++ = *src++;
   309 	}
   310 	bank_flag = !bank_flag;
   311     }
   313     dwsrc = (uint32_t *)src;
   314     while( length >= 4 ) {
   315 	*banks[bank_flag]++ = *dwsrc++;
   316 	bank_flag = !bank_flag;
   317 	length -= 4;
   318     }
   320     /* Handle non-aligned end of source */
   321     if( length ) {
   322 	src = (char *)dwsrc;
   323 	char *dest = (char *)banks[bank_flag];
   324 	while( length-- > 0 ) {
   325 	    *dest++ = *src++;
   326 	}
   327     }  
   329 }
   331 void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
   332 {
   333     int bank_flag = (srcaddr & 0x04) >> 2;
   334     uint32_t *banks[2];
   335     uint32_t *dwdest;
   336     int i;
   338     srcaddr = srcaddr & 0x7FFFFF;
   339     if( srcaddr + length > 0x800000 )
   340 	length = 0x800000 - srcaddr;
   342     banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1)));
   343     banks[1] = banks[0] + 0x100000;
   344     if( bank_flag )
   345 	banks[0]++;
   347     /* Handle non-aligned start of source */
   348     if( srcaddr & 0x03 ) {
   349 	char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
   350 	for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
   351 	    *dest++ = *src++;
   352 	}
   353 	bank_flag = !bank_flag;
   354     }
   356     dwdest = (uint32_t *)dest;
   357     while( length >= 4 ) {
   358 	*dwdest++ = *banks[bank_flag]++;
   359 	bank_flag = !bank_flag;
   360 	length -= 4;
   361     }
   363     /* Handle non-aligned end of source */
   364     if( length ) {
   365 	dest = (char *)dwdest;
   366 	char *src = (char *)banks[bank_flag];
   367 	while( length-- > 0 ) {
   368 	    *dest++ = *src++;
   369 	}
   370     }
   371 }
   373 void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f ) 
   374 {
   375     char tmp[length];
   376     pvr2_vram64_read( tmp, addr, length );
   377     fwrite_dump( tmp, length, f );
   378 }
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