filename | src/sh4/mem.h |
changeset | 2:42349f6ea216 |
prev | 1:eea311cfd33e |
author | nkeynes |
date | Thu Dec 08 13:38:00 2005 +0000 (18 years ago) |
permissions | -rw-r--r-- |
last change | Generalise the core debug window to allow multiple instances. Add cpu description structure to define different cpus for use by the debug window, in preparation for ARM implementation |
view | annotate | diff | log | raw |
1 #ifndef dream_sh4_mem_H
2 #define dream_sh4_mem_H
4 #include <stdint.h>
5 #include "sh4mmio.h"
7 #ifdef __cplusplus
8 extern "C" {
9 #if 0
10 }
11 #endif
12 #endif
14 typedef struct mem_region {
15 uint32_t base;
16 uint32_t size;
17 char *name;
18 char *mem;
19 int flags;
20 } *mem_region_t;
22 #define MAX_IO_REGIONS 24
23 #define MAX_MEM_REGIONS 8
25 #define MEM_REGION_MAIN "System RAM"
26 #define MEM_REGION_VIDEO "Video RAM"
27 #define MEM_REGION_AUDIO "Audio RAM"
28 #define MEM_REGION_AUDIO_SCRATCH "Audio Scratch RAM"
30 #define MB * (1024 * 1024)
31 #define KB * 1024
33 int32_t mem_read_long( uint32_t addr );
34 int32_t mem_read_word( uint32_t addr );
35 int32_t mem_read_byte( uint32_t addr );
36 void mem_write_long( uint32_t addr, uint32_t val );
37 void mem_write_word( uint32_t addr, uint32_t val );
38 void mem_write_byte( uint32_t addr, uint32_t val );
40 int32_t mem_read_phys_word( uint32_t addr );
41 void *mem_create_ram_region( uint32_t base, uint32_t size, char *name );
42 void *mem_load_rom( char *name, uint32_t base, uint32_t size, uint32_t crc );
43 char *mem_get_region( uint32_t addr );
44 char *mem_get_region_by_name( char *name );
45 void mem_set_cache_mode( int );
46 int mem_has_page( uint32_t addr );
48 void mem_init( void );
49 void mem_reset( void );
51 #define ENABLE_WATCH 1
53 #define WATCH_WRITE 1
54 #define WATCH_READ 2
55 #define WATCH_EXEC 3 /* AKA Breakpoint :) */
57 typedef struct watch_point *watch_point_t;
59 watch_point_t mem_new_watch( uint32_t start, uint32_t end, int flags );
60 void mem_delete_watch( watch_point_t watch );
61 watch_point_t mem_is_watched( uint32_t addr, int size, int op );
63 /* mmucr register bits */
64 #define MMUCR_AT 0x00000001 /* Address Translation enabled */
65 #define MMUCR_TI 0x00000004 /* TLB invalidate (always read as 0) */
66 #define MMUCR_SV 0x00000100 /* Single Virtual mode=1 / multiple virtual=0 */
67 #define MMUCR_SQMD 0x00000200 /* Store queue mode bit (0=user, 1=priv only) */
68 #define MMUCR_URC 0x0000FC00 /* UTLB access counter */
69 #define MMUCR_URB 0x00FC0000 /* UTLB entry boundary */
70 #define MMUCR_LRUI 0xFC000000 /* Least recently used ITLB */
71 #define MMUCR_MASK 0xFCFCFF05
72 #define MMUCR_RMASK 0xFCFCFF01 /* Read mask */
74 #define IS_MMU_ENABLED() (MMIO_READ(MMU, MMUCR)&MMUCR_AT)
76 /* ccr register bits */
77 #define CCR_IIX 0x00008000 /* IC index enable */
78 #define CCR_ICI 0x00000800 /* IC invalidation (always read as 0) */
79 #define CCR_ICE 0x00000100 /* IC enable */
80 #define CCR_OIX 0x00000080 /* OC index enable */
81 #define CCR_ORA 0x00000020 /* OC RAM enable */
82 #define CCR_OCI 0x00000008 /* OC invalidation (always read as 0) */
83 #define CCR_CB 0x00000004 /* Copy-back (P1 area cache write mode) */
84 #define CCR_WT 0x00000002 /* Write-through (P0,U0,P3 write mode) */
85 #define CCR_OCE 0x00000001 /* OC enable */
86 #define CCR_MASK 0x000089AF
87 #define CCR_RMASK 0x000081A7 /* Read mask */
89 #define MEM_OC_DISABLED 0
90 #define MEM_OC_INDEX0 CCR_ORA
91 #define MEM_OC_INDEX1 CCR_ORA|CCR_OIX
93 #ifdef __cplusplus
94 }
95 #endif
96 #endif
.