lxdream.org :: lxdream/src/pvr2/pvr2.c r850:28782ebbd01d

tree revision 850:28782ebbd01d

filename	src/pvr2/pvr2.c
changeset	850:28782ebbd01d
prev	805:b355f7b3ff2e
next	851:41e8ae2c114b
author	nkeynes
date	Mon Sep 08 07:56:33 2008 +0000 (12 years ago)
permissions	-rw-r--r--
last change	Add lightgun support

view

     1 /**

     2  * $Id$

     3  *

     4  * PVR2 (Video) Core module implementation and MMIO registers.

     5  *

     6  * Copyright (c) 2005 Nathan Keynes.

     7  *

     8  * This program is free software; you can redistribute it and/or modify

     9  * it under the terms of the GNU General Public License as published by

    10  * the Free Software Foundation; either version 2 of the License, or

    11  * (at your option) any later version.

    12  *

    13  * This program is distributed in the hope that it will be useful,

    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    16  * GNU General Public License for more details.

    17  */

    18 #define MODULE pvr2_module

    20 #include <assert.h>

    21 #include "dream.h"

    22 #include "eventq.h"

    23 #include "display.h"

    24 #include "mem.h"

    25 #include "asic.h"

    26 #include "clock.h"

    27 #include "pvr2/pvr2.h"

    28 #include "pvr2/pvr2mmio.h"

    29 #include "pvr2/scene.h"

    30 #include "sh4/sh4.h"

    31 #define MMIO_IMPL

    32 #include "pvr2/pvr2mmio.h"

    34 unsigned char *video_base;

    36 #define MAX_RENDER_BUFFERS 4

    38 #define HPOS_PER_FRAME 0

    39 #define HPOS_PER_LINECOUNT 1

    41 static void pvr2_init( void );

    42 static void pvr2_reset( void );

    43 static uint32_t pvr2_run_slice( uint32_t );

    44 static void pvr2_save_state( FILE *f );

    45 static int pvr2_load_state( FILE *f );

    46 static void pvr2_update_raster_posn( uint32_t nanosecs );

    47 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );

    48 static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );

    49 static render_buffer_t pvr2_next_render_buffer( );

    50 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame );

    51 uint32_t pvr2_get_sync_status();

    53 void pvr2_display_frame( void );

    55 static int output_colour_formats[] = { COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGR888, COLFMT_BGRA8888 };

    57 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,

    58         pvr2_run_slice, NULL,

    59         pvr2_save_state, pvr2_load_state };

    62 display_driver_t display_driver = NULL;

    64 struct pvr2_state {

    65     uint32_t frame_count;

    66     uint32_t line_count;

    67     uint32_t line_remainder;

    68     uint32_t cycles_run; /* Cycles already executed prior to main time slice */

    69     uint32_t irq_hpos_line;

    70     uint32_t irq_hpos_line_count;

    71     uint32_t irq_hpos_mode;

    72     uint32_t irq_hpos_time_ns; /* Time within the line */

    73     uint32_t irq_vpos1;

    74     uint32_t irq_vpos2;

    75     uint32_t odd_even_field; /* 1 = odd, 0 = even */

    76     int32_t palette_changed; /* TRUE if palette has changed since last render */

    77     uint32_t padding; /* FIXME: Remove in next DST version */

    78     /* timing */

    79     uint32_t dot_clock;

    80     uint32_t total_lines;

    81     uint32_t line_size;

    82     uint32_t line_time_ns;

    83     uint32_t vsync_lines;

    84     uint32_t hsync_width_ns;

    85     uint32_t front_porch_ns;

    86     uint32_t back_porch_ns;

    87     uint32_t retrace_start_line;

    88     uint32_t retrace_end_line;

    89     int32_t interlaced;

    90 } pvr2_state;

    92 static gchar *save_next_render_filename;

    93 static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];

    94 static uint32_t render_buffer_count = 0;

    95 static render_buffer_t displayed_render_buffer = NULL;

    96 static uint32_t displayed_border_colour = 0;

    98 /**

    99  * Event handler for the hpos callback

   100  */

   101 static void pvr2_hpos_callback( int eventid ) {

   102     asic_event( eventid );

   103     pvr2_update_raster_posn(sh4r.slice_cycle);

   104     if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {

   105         pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;

   106         while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {

   107             pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);

   108         }

   109     }

   110     pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1,

   111                                   pvr2_state.irq_hpos_time_ns );

   112 }

   114 /**

   115  * Event handler for the scanline callbacks. Fires the corresponding

   116  * ASIC event, and resets the timer for the next field.

   117  */

   118 static void pvr2_scanline_callback( int eventid )

   119 {

   120     asic_event( eventid );

   121     pvr2_update_raster_posn(sh4r.slice_cycle);

   122     if( eventid == EVENT_SCANLINE1 ) {

   123         pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );

   124     } else {

   125         pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );

   126     }

   127 }

   129 static void pvr2_gunpos_callback( int eventid )

   130 {

   131     pvr2_update_raster_posn(sh4r.slice_cycle);

   132     int hpos = pvr2_state.line_remainder * pvr2_state.dot_clock / 1000000;

   133     MMIO_WRITE( PVR2, GUNPOS, ((pvr2_state.line_count<<16)|(hpos&0x3FF)) );

   134     asic_event( EVENT_MAPLE_DMA );

   135 }

   137 static void pvr2_init( void )

   138 {

   139     int i;

   140     register_io_region( &mmio_region_PVR2 );

   141     register_io_region( &mmio_region_PVR2PAL );

   142     register_io_region( &mmio_region_PVR2TA );

   143     register_event_callback( EVENT_HPOS, pvr2_hpos_callback );

   144     register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );

   145     register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );

   146     register_event_callback( EVENT_GUNPOS, pvr2_gunpos_callback );

   147     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );

   148     texcache_init();

   149     pvr2_reset();

   150     pvr2_ta_reset();

   151     save_next_render_filename = NULL;

   152     for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {

   153         render_buffers[i] = NULL;

   154     }

   155     render_buffer_count = 0;

   156     displayed_render_buffer = NULL;

   157     displayed_border_colour = 0;

   158 }

   160 static void pvr2_reset( void )

   161 {

   162     int i;

   163     pvr2_state.line_count = 0;

   164     pvr2_state.line_remainder = 0;

   165     pvr2_state.cycles_run = 0;

   166     pvr2_state.irq_vpos1 = 0;

   167     pvr2_state.irq_vpos2 = 0;

   168     pvr2_state.dot_clock = PVR2_DOT_CLOCK;

   169     pvr2_state.back_porch_ns = 4000;

   170     pvr2_state.palette_changed = FALSE;

   171     mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );

   172     mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );

   173     mmio_region_PVR2_write( YUV_ADDR, 0 );

   174     mmio_region_PVR2_write( YUV_CFG, 0 );

   176     pvr2_ta_init();

   177     texcache_flush();

   178     if( display_driver ) {

   179         display_driver->display_blank(0);

   180         for( i=0; i<render_buffer_count; i++ ) {

   181             display_driver->destroy_render_buffer(render_buffers[i]);

   182             render_buffers[i] = NULL;

   183         }

   184         render_buffer_count = 0;

   185     }

   186 }

   188 void pvr2_save_render_buffer( FILE *f, render_buffer_t buffer )

   189 {

   190     struct frame_buffer fbuf;

   192     fbuf.width = buffer->width;

   193     fbuf.height = buffer->height;

   194     fbuf.rowstride = fbuf.width*3;

   195     fbuf.colour_format = COLFMT_BGR888;

   196     fbuf.inverted = buffer->inverted;

   197     fbuf.data = g_malloc0( buffer->width * buffer->height * 3 );

   199     display_driver->read_render_buffer( fbuf.data, buffer, fbuf.rowstride, COLFMT_BGR888 );

   200     write_png_to_stream( f, &fbuf );

   201     g_free( fbuf.data );

   203     fwrite( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );

   204     fwrite( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );

   205     fwrite( &buffer->address, sizeof(buffer->address), 1, f );

   206     fwrite( &buffer->scale, sizeof(buffer->scale), 1, f );

   207     int32_t flushed = (int32_t)buffer->flushed; // Force to 32-bits for save-file consistency

   208     fwrite( &flushed, sizeof(flushed), 1, f );

   210 }

   212 render_buffer_t pvr2_load_render_buffer( FILE *f )

   213 {

   214     frame_buffer_t frame = read_png_from_stream( f );

   215     if( frame == NULL ) {

   216         return NULL;

   217     }

   219     render_buffer_t buffer = pvr2_frame_buffer_to_render_buffer(frame);

   220     if( buffer != NULL ) {

   221         int32_t flushed;

   222         fread( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );

   223         fread( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );

   224         fread( &buffer->address, sizeof(buffer->address), 1, f );

   225         fread( &buffer->scale, sizeof(buffer->scale), 1, f );

   226         fread( &flushed, sizeof(flushed), 1, f );

   227         buffer->flushed = (gboolean)flushed;

   228     } else {

   229         fseek( f, sizeof(buffer->rowstride)+sizeof(buffer->colour_format)+

   230                 sizeof(buffer->address)+sizeof(buffer->scale)+

   231                 sizeof(int32_t), SEEK_CUR );

   232     }

   233     return buffer;

   234 }

   239 void pvr2_save_render_buffers( FILE *f )

   240 {

   241     int i;

   242     uint32_t has_frontbuffer;

   243     fwrite( &render_buffer_count, sizeof(render_buffer_count), 1, f );

   244     if( displayed_render_buffer != NULL ) {

   245         has_frontbuffer = 1;

   246         fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );

   247         pvr2_save_render_buffer( f, displayed_render_buffer );

   248     } else {

   249         has_frontbuffer = 0;

   250         fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );

   251     }

   253     for( i=0; i<render_buffer_count; i++ ) {

   254         if( render_buffers[i] != displayed_render_buffer && render_buffers[i] != NULL ) {

   255             pvr2_save_render_buffer( f, render_buffers[i] );

   256         }

   257     }

   258 }

   260 gboolean pvr2_load_render_buffers( FILE *f )

   261 {

   262     uint32_t count, has_frontbuffer;

   263     int i;

   265     fread( &count, sizeof(count), 1, f );

   266     if( count > MAX_RENDER_BUFFERS ) {

   267         return FALSE;

   268     }

   269     fread( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );

   270     for( i=0; i<render_buffer_count; i++ ) {

   271         display_driver->destroy_render_buffer(render_buffers[i]);

   272         render_buffers[i] = NULL;

   273     }

   274     render_buffer_count = 0;

   276     if( has_frontbuffer ) {

   277         displayed_render_buffer = pvr2_load_render_buffer(f);

   278         display_driver->display_render_buffer( displayed_render_buffer );

   279         count--;

   280     }

   282     for( i=0; i<count; i++ ) {

   283         pvr2_load_render_buffer( f );

   284     }

   285     return TRUE;

   286 }

   289 static void pvr2_save_state( FILE *f )

   290 {

   291     pvr2_save_render_buffers( f );

   292     fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );

   293     pvr2_ta_save_state( f );

   294     pvr2_yuv_save_state( f );

   295 }

   297 static int pvr2_load_state( FILE *f )

   298 {

   299     if( !pvr2_load_render_buffers(f) )

   300         return 1;

   301     if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )

   302         return 1;

   303     if( pvr2_ta_load_state(f) ) {

   304         return 1;

   305     }

   306     return pvr2_yuv_load_state(f);

   307 }

   309 /**

   310  * Update the current raster position to the given number of nanoseconds,

   311  * relative to the last time slice. (ie the raster will be adjusted forward

   312  * by nanosecs - nanosecs_already_run_this_timeslice)

   313  */

   314 static void pvr2_update_raster_posn( uint32_t nanosecs )

   315 {

   316     uint32_t old_line_count = pvr2_state.line_count;

   317     if( pvr2_state.line_time_ns == 0 ) {

   318         return; /* do nothing */

   319     }

   320     pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);

   321     pvr2_state.cycles_run = nanosecs;

   322     while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {

   323         pvr2_state.line_count ++;

   324         pvr2_state.line_remainder -= pvr2_state.line_time_ns;

   325     }

   327     if( pvr2_state.line_count >= pvr2_state.total_lines ) {

   328         pvr2_state.line_count -= pvr2_state.total_lines;

   329         if( pvr2_state.interlaced ) {

   330             pvr2_state.odd_even_field = !pvr2_state.odd_even_field;

   331         }

   332     }

   333     if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&

   334             (old_line_count < pvr2_state.retrace_end_line ||

   335                     old_line_count > pvr2_state.line_count) ) {

   336         pvr2_state.frame_count++;

   337         pvr2_display_frame();

   338     }

   339 }

   341 static uint32_t pvr2_run_slice( uint32_t nanosecs )

   342 {

   343     pvr2_update_raster_posn( nanosecs );

   344     pvr2_state.cycles_run = 0;

   345     return nanosecs;

   346 }

   348 int pvr2_get_frame_count()

   349 {

   350     return pvr2_state.frame_count;

   351 }

   353 void pvr2_redraw_display()

   354 {

   355     if( display_driver != NULL ) {

   356         if( displayed_render_buffer == NULL ) {

   357             display_driver->display_blank(displayed_border_colour);

   358         } else {

   359             display_driver->display_render_buffer(displayed_render_buffer);

   360         }

   361     }

   362 }

   364 gboolean pvr2_save_next_scene( const gchar *filename )

   365 {

   366     if( save_next_render_filename != NULL ) {

   367         g_free( save_next_render_filename );

   368     }

   369     save_next_render_filename = g_strdup(filename);

   370     return TRUE;

   371 }

   375 /**

   376  * Display the next frame, copying the current contents of video ram to

   377  * the window. If the video configuration has changed, first recompute the

   378  * new frame size/depth.

   379  */

   380 void pvr2_display_frame( void )

   381 {

   382     int dispmode = MMIO_READ( PVR2, DISP_MODE );

   383     int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );

   384     gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;

   386     if( display_driver == NULL ) {

   387         return; /* can't really do anything much */

   388     } else if( !bEnabled ) {

   389         /* Output disabled == black */

   390         displayed_render_buffer = NULL;

   391         displayed_border_colour = 0;

   392         display_driver->display_blank( 0 );

   393     } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) {

   394         /* Enabled but blanked - border colour */

   395         displayed_border_colour = MMIO_READ( PVR2, DISP_BORDER );

   396         displayed_render_buffer = NULL;

   397         display_driver->display_blank( displayed_border_colour );

   398     } else {

   399         /* Real output - determine dimensions etc */

   400         struct frame_buffer fbuf;

   401         uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );

   402         int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);

   403         int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;

   405         fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];

   406         fbuf.width = vid_ppl << 2 / colour_formats[fbuf.colour_format].bpp;

   407         fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;

   408         fbuf.size = vid_ppl << 2 * fbuf.height;

   409         fbuf.rowstride = (vid_ppl + vid_stride) << 2;

   411         /* Determine the field to display, and deinterlace if possible */

   412         if( pvr2_state.interlaced ) {

   413             if( vid_ppl == vid_stride ) { /* Magic deinterlace */

   414                 fbuf.height = fbuf.height << 1;

   415                 fbuf.rowstride = vid_ppl << 2;

   416                 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );

   417             } else {

   418                 /* Just display the field as is, folks. This is slightly tricky -

   419                  * we pick the field based on which frame is about to come through,

   420                  * which may not be the same as the odd_even_field.

   421                  */

   422                 gboolean oddfield = pvr2_state.odd_even_field;

   423                 if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {

   424                     oddfield = !oddfield;

   425                 }

   426                 if( oddfield ) {

   427                     fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );

   428                 } else {

   429                     fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );

   430                 }

   431             }

   432         } else {

   433             fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );

   434         }

   435         fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;

   436         fbuf.inverted = FALSE;

   437         fbuf.data = video_base + (fbuf.address&0x00FFFFFF);

   439         render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );

   440         if( rbuf == NULL ) {

   441             rbuf = pvr2_frame_buffer_to_render_buffer( &fbuf );

   442         }

   443         displayed_render_buffer = rbuf;

   444         if( rbuf != NULL ) {

   445             display_driver->display_render_buffer( rbuf );

   446         }

   447     }

   448 }

   450 /**

   451  * This has to handle every single register individually as they all get masked

   452  * off differently (and its easier to do it at write time)

   453  */

   454 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )

   455 {

   456     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */

   457         MMIO_WRITE( PVR2, reg, val );

   458         return;

   459     }

   461     switch(reg) {

   462     case PVRID:

   463     case PVRVER:

   464     case GUNPOS: /* Read only registers */

   465         break;

   466     case PVRRESET:

   467         val &= 0x00000007; /* Do stuff? */

   468         MMIO_WRITE( PVR2, reg, val );

   469         break;

   470     case RENDER_START: /* Don't really care what value */

   471         if( save_next_render_filename != NULL ) {

   472             if( pvr2_render_save_scene(save_next_render_filename) == 0 ) {

   473                 INFO( "Saved scene to %s", save_next_render_filename);

   474             }

   475             g_free( save_next_render_filename );

   476             save_next_render_filename = NULL;

   477         }

   478         pvr2_scene_read();

   479         render_buffer_t buffer = pvr2_next_render_buffer();

   480         if( buffer != NULL ) {

   481             pvr2_scene_render( buffer );

   482         }

   483         asic_event( EVENT_PVR_RENDER_DONE );

   484         break;

   485     case RENDER_POLYBASE:

   486         MMIO_WRITE( PVR2, reg, val&0x00F00000 );

   487         break;

   488     case RENDER_TSPCFG:

   489         MMIO_WRITE( PVR2, reg, val&0x00010101 );

   490         break;

   491     case DISP_BORDER:

   492         MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );

   493         break;

   494     case DISP_MODE:

   495         MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );

   496         break;

   497     case RENDER_MODE:

   498         MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );

   499         break;

   500     case RENDER_SIZE:

   501         MMIO_WRITE( PVR2, reg, val&0x000001FF );

   502         break;

   503     case DISP_ADDR1:

   504         val &= 0x00FFFFFC;

   505         MMIO_WRITE( PVR2, reg, val );

   506         pvr2_update_raster_posn(sh4r.slice_cycle);

   507         break;

   508     case DISP_ADDR2:

   509         MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );

   510         pvr2_update_raster_posn(sh4r.slice_cycle);

   511         break;

   512     case DISP_SIZE:

   513         MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );

   514         break;

   515     case RENDER_ADDR1:

   516     case RENDER_ADDR2:

   517         MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );

   518         break;

   519     case RENDER_HCLIP:

   520         MMIO_WRITE( PVR2, reg, val&0x07FF07FF );

   521         break;

   522     case RENDER_VCLIP:

   523         MMIO_WRITE( PVR2, reg, val&0x03FF03FF );

   524         break;

   525     case DISP_HPOSIRQ:

   526         MMIO_WRITE( PVR2, reg, val&0x03FF33FF );

   527         pvr2_state.irq_hpos_line = val & 0x03FF;

   528         pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;

   529         pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;

   530         switch( pvr2_state.irq_hpos_mode ) {

   531         case 3: /* Reserved - treat as 0 */

   532         case 0: /* Once per frame at specified line */

   533             pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;

   534             break;

   535         case 2: /* Once per line - as per-line-count */

   536             pvr2_state.irq_hpos_line = 1;

   537             pvr2_state.irq_hpos_mode = 1;

   538         case 1: /* Once per N lines */

   539             pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;

   540             pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) +

   541             pvr2_state.irq_hpos_line_count;

   542             while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {

   543                 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);

   544             }

   545             pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;

   546         }

   547         pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,

   548                                       pvr2_state.irq_hpos_time_ns );

   549         break;

   550         case DISP_VPOSIRQ:

   551             val = val & 0x03FF03FF;

   552             pvr2_state.irq_vpos1 = (val >> 16);

   553             pvr2_state.irq_vpos2 = val & 0x03FF;

   554             pvr2_update_raster_posn(sh4r.slice_cycle);

   555             pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );

   556             pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );

   557             MMIO_WRITE( PVR2, reg, val );

   558             break;

   559         case RENDER_NEARCLIP:

   560             MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );

   561             break;

   562         case RENDER_SHADOW:

   563             MMIO_WRITE( PVR2, reg, val&0x000001FF );

   564             break;

   565         case RENDER_OBJCFG:

   566             MMIO_WRITE( PVR2, reg, val&0x003FFFFF );

   567             break;

   568         case RENDER_TSPCLIP:

   569             MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );

   570             break;

   571         case RENDER_FARCLIP:

   572             MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );

   573             break;

   574         case RENDER_BGPLANE:

   575             MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );

   576             break;

   577         case RENDER_ISPCFG:

   578             MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );

   579             break;

   580         case VRAM_CFG1:

   581             MMIO_WRITE( PVR2, reg, val&0x000000FF );

   582             break;

   583         case VRAM_CFG2:

   584             MMIO_WRITE( PVR2, reg, val&0x003FFFFF );

   585             break;

   586         case VRAM_CFG3:

   587             MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );

   588             break;

   589         case RENDER_FOGTBLCOL:

   590         case RENDER_FOGVRTCOL:

   591             MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );

   592             break;

   593         case RENDER_FOGCOEFF:

   594             MMIO_WRITE( PVR2, reg, val&0x0000FFFF );

   595             break;

   596         case RENDER_CLAMPHI:

   597         case RENDER_CLAMPLO:

   598             MMIO_WRITE( PVR2, reg, val );

   599             break;

   600         case RENDER_TEXSIZE:

   601             MMIO_WRITE( PVR2, reg, val&0x00031F1F );

   602             break;

   603         case RENDER_PALETTE:

   604             MMIO_WRITE( PVR2, reg, val&0x00000003 );

   605             break;

   606         case RENDER_ALPHA_REF:

   607             MMIO_WRITE( PVR2, reg, val&0x000000FF );

   608             break;

   609             /********** CRTC registers *************/

   610         case DISP_HBORDER:

   611         case DISP_VBORDER:

   612             MMIO_WRITE( PVR2, reg, val&0x03FF03FF );

   613             break;

   614         case DISP_TOTAL:

   615             val = val & 0x03FF03FF;

   616             MMIO_WRITE( PVR2, reg, val );

   617             pvr2_update_raster_posn(sh4r.slice_cycle);

   618             pvr2_state.total_lines = (val >> 16) + 1;

   619             pvr2_state.line_size = (val & 0x03FF) + 1;

   620             pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;

   621             pvr2_state.retrace_end_line = 0x2A;

   622             pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;

   623             pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );

   624             pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );

   625             pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,

   626                                           pvr2_state.irq_hpos_time_ns );

   627             break;

   628         case DISP_SYNCCFG:

   629             MMIO_WRITE( PVR2, reg, val&0x000003FF );

   630             pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;

   631             break;

   632         case DISP_SYNCTIME:

   633             pvr2_state.vsync_lines = (val >> 8) & 0x0F;

   634             pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;

   635             MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );

   636             break;

   637         case DISP_CFG2:

   638             MMIO_WRITE( PVR2, reg, val&0x003F01FF );

   639             break;

   640         case DISP_HPOS:

   641             val = val & 0x03FF;

   642             pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;

   643             MMIO_WRITE( PVR2, reg, val );

   644             break;

   645         case DISP_VPOS:

   646             MMIO_WRITE( PVR2, reg, val&0x03FF03FF );

   647             break;

   649             /*********** Tile accelerator registers ***********/

   650         case TA_POLYPOS:

   651         case TA_LISTPOS:

   652             /* Readonly registers */

   653             break;

   654         case TA_TILEBASE:

   655         case TA_LISTEND:

   656         case TA_LISTBASE:

   657             MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );

   658             break;

   659         case RENDER_TILEBASE:

   660         case TA_POLYBASE:

   661         case TA_POLYEND:

   662             MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );

   663             break;

   664         case TA_TILESIZE:

   665             MMIO_WRITE( PVR2, reg, val&0x000F003F );

   666             break;

   667         case TA_TILECFG:

   668             MMIO_WRITE( PVR2, reg, val&0x00133333 );

   669             break;

   670         case TA_INIT:

   671             if( val & 0x80000000 )

   672                 pvr2_ta_init();

   673             break;

   674         case TA_REINIT:

   675             break;

   676             /**************** Scaler registers? ****************/

   677         case RENDER_SCALER:

   678             MMIO_WRITE( PVR2, reg, val&0x0007FFFF );

   679             break;

   681         case YUV_ADDR:

   682             val = val & 0x00FFFFF8;

   683             MMIO_WRITE( PVR2, reg, val );

   684             pvr2_yuv_init( val );

   685             break;

   686         case YUV_CFG:

   687             MMIO_WRITE( PVR2, reg, val&0x01013F3F );

   688             pvr2_yuv_set_config(val);

   689             break;

   691             /**************** Unknowns ***************/

   692         case PVRUNK1:

   693             MMIO_WRITE( PVR2, reg, val&0x000007FF );

   694             break;

   695         case PVRUNK2:

   696             MMIO_WRITE( PVR2, reg, val&0x00000007 );

   697             break;

   698         case PVRUNK3:

   699             MMIO_WRITE( PVR2, reg, val&0x000FFF3F );

   700             break;

   701         case PVRUNK5:

   702             MMIO_WRITE( PVR2, reg, val&0x0000FFFF );

   703             break;

   704         case PVRUNK7:

   705             MMIO_WRITE( PVR2, reg, val&0x00000001 );

   706             break;

   707         case PVRUNK8:

   708             MMIO_WRITE( PVR2, reg, val&0x0300FFFF );

   709             break;

   710     }

   711 }

   713 /**

   714  * Calculate the current read value of the syncstat register, using

   715  * the current SH4 clock time as an offset from the last timeslice.

   716  * The register reads (LSB to MSB) as:

   717  *     0..9  Current scan line

   718  *     10    Odd/even field (1 = odd, 0 = even)

   719  *     11    Display active (including border and overscan)

   720  *     12    Horizontal sync off

   721  *     13    Vertical sync off

   722  * Note this method is probably incorrect for anything other than straight

   723  * interlaced PAL/NTSC, and needs further testing.

   724  */

   725 uint32_t pvr2_get_sync_status()

   726 {

   727     pvr2_update_raster_posn(sh4r.slice_cycle);

   728     uint32_t result = pvr2_state.line_count;

   730     if( pvr2_state.odd_even_field ) {

   731         result |= 0x0400;

   732     }

   733     if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {

   734         if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {

   735             result |= 0x1000; /* !HSYNC */

   736         }

   737         if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {

   738             if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {

   739                 result |= 0x2800; /* Display active */

   740             } else {

   741                 result |= 0x2000; /* Front porch */

   742             }

   743         }

   744     } else {

   745         if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {

   746             if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {

   747                 result |= 0x3800; /* Display active */

   748             } else {

   749                 result |= 0x3000;

   750             }

   751         } else {

   752             result |= 0x1000; /* Back porch */

   753         }

   754     }

   755     return result;

   756 }

   758 /**

   759  * Schedule a "scanline" event. This actually goes off at

   760  * 2 * line in even fields and 2 * line + 1 in odd fields.

   761  * Otherwise this behaves as per pvr2_schedule_line_event().

   762  * The raster position should be updated before calling this

   763  * method.

   764  * @param eventid Event to fire at the specified time

   765  * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced

   766  *  displays).

   767  * @param hpos_ns Nanoseconds into the line at which to fire.

   768  */

   769 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )

   770 {

   771     uint32_t field = pvr2_state.odd_even_field;

   772     if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {

   773         field = !field;

   774     }

   775     if( hpos_ns > pvr2_state.line_time_ns ) {

   776         hpos_ns = pvr2_state.line_time_ns;

   777     }

   779     line <<= 1;

   780     if( field ) {

   781         line += 1;

   782     }

   784     if( line < pvr2_state.total_lines ) {

   785         uint32_t lines;

   786         uint32_t time;

   787         if( line <= pvr2_state.line_count ) {

   788             lines = (pvr2_state.total_lines - pvr2_state.line_count + line);

   789         } else {

   790             lines = (line - pvr2_state.line_count);

   791         }

   792         if( lines <= minimum_lines ) {

   793             lines += pvr2_state.total_lines;

   794         }

   795         time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;

   796         event_schedule( eventid, time );

   797     } else {

   798         event_cancel( eventid );

   799     }

   800 }

   802 void pvr2_queue_gun_event( int xpos, int ypos )

   803 {

   804     pvr2_update_raster_posn(sh4r.slice_cycle);

   805     pvr2_schedule_scanline_event( EVENT_GUNPOS, (ypos >> 1) + pvr2_state.vsync_lines, 0,

   806             (1000000 * xpos / pvr2_state.dot_clock) + pvr2_state.hsync_width_ns );

   807 }

   809 MMIO_REGION_READ_FN( PVR2, reg )

   810 {

   811     switch( reg ) {

   812     case DISP_SYNCSTAT:

   813         return pvr2_get_sync_status();

   814     default:

   815         return MMIO_READ( PVR2, reg );

   816     }

   817 }

   819 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )

   820 {

   821     MMIO_WRITE( PVR2PAL, reg, val );

   822     pvr2_state.palette_changed = TRUE;

   823 }

   825 void pvr2_check_palette_changed()

   826 {

   827     if( pvr2_state.palette_changed ) {

   828         texcache_invalidate_palette();

   829         pvr2_state.palette_changed = FALSE;

   830     }

   831 }

   833 MMIO_REGION_READ_DEFFN( PVR2PAL );

   835 void pvr2_set_base_address( uint32_t base )

   836 {

   837     mmio_region_PVR2_write( DISP_ADDR1, base );

   838 }

   843 int32_t mmio_region_PVR2TA_read( uint32_t reg )

   844 {

   845     return 0xFFFFFFFF;

   846 }

   848 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )

   849 {

   850     pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );

   851 }

   853 /**

   854  * Find the render buffer corresponding to the requested output frame

   855  * (does not consider texture renders).

   856  * @return the render_buffer if found, or null if no such buffer.

   857  *

   858  * Note: Currently does not consider "partial matches", ie partial

   859  * frame overlap - it probably needs to do this.

   860  */

   861 render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )

   862 {

   863     int i;

   864     for( i=0; i<render_buffer_count; i++ ) {

   865         if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {

   866             return render_buffers[i];

   867         }

   868     }

   869     return NULL;

   870 }

   872 /**

   873  * Allocate a render buffer with the requested parameters.

   874  * The order of preference is:

   875  *   1. An existing buffer with the same address. (not flushed unless the new

   876  * size is smaller than the old one).

   877  *   2. An existing buffer with the same size chosen by LRU order. Old buffer

   878  *       is flushed to vram.

   879  *   3. A new buffer if one can be created.

   880  *   4. The current display buff

   881  * Note: The current display field(s) will never be overwritten except as a last

   882  * resort.

   883  */

   884 render_buffer_t pvr2_alloc_render_buffer( sh4addr_t render_addr, int width, int height )

   885 {

   886     int i;

   887     render_buffer_t result = NULL;

   889     /* Check existing buffers for an available buffer */

   890     for( i=0; i<render_buffer_count; i++ ) {

   891         if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {

   892             /* needs to be the right dimensions */

   893             if( render_buffers[i]->address == render_addr ) {

   894                 if( displayed_render_buffer == render_buffers[i] ) {

   895                     /* Same address, but we can't use it because the

   896                      * display has it. Mark it as unaddressed for later.

   897                      */

   898                     render_buffers[i]->address = -1;

   899                 } else {

   900                     /* perfect */

   901                     result = render_buffers[i];

   902                     break;

   903                 }

   904             } else if( render_buffers[i]->address == -1 && result == NULL &&

   905                     displayed_render_buffer != render_buffers[i] ) {

   906                 result = render_buffers[i];

   907             }

   909         } else if( render_buffers[i]->address == render_addr ) {

   910             /* right address, wrong size - if it's larger, flush it, otherwise

   911              * nuke it quietly */

   912             if( render_buffers[i]->width * render_buffers[i]->height >

   913             width*height ) {

   914                 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );

   915             }

   916             render_buffers[i]->address = -1;

   917         }

   918     }

   920     /* Nothing available - make one */

   921     if( result == NULL ) {

   922         if( render_buffer_count == MAX_RENDER_BUFFERS ) {

   923             /* maximum buffers reached - need to throw one away */

   924             uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );

   925             uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );

   926             for( i=0; i<render_buffer_count; i++ ) {

   927                 if( render_buffers[i]->address != field1_addr &&

   928                         render_buffers[i]->address != field2_addr &&

   929                         render_buffers[i] != displayed_render_buffer ) {

   930                     /* Never throw away the current "front buffer(s)" */

   931                     result = render_buffers[i];

   932                     if( !result->flushed ) {

   933                         pvr2_render_buffer_copy_to_sh4( result );

   934                     }

   935                     if( result->width != width || result->height != height ) {

   936                         display_driver->destroy_render_buffer(render_buffers[i]);

   937                         result = display_driver->create_render_buffer(width,height,0);

   938                         render_buffers[i] = result;

   939                     }

   940                     break;

   941                 }

   942             }

   943         } else {

   944             result = display_driver->create_render_buffer(width,height,0);

   945             if( result != NULL ) {

   946                 render_buffers[render_buffer_count++] = result;

   947             }

   948         }

   949     }

   951     if( result != NULL ) {

   952         result->address = render_addr;

   953     }

   954     return result;

   955 }

   957 /**

   958  * Allocate a render buffer based on the current rendering settings

   959  */

   960 render_buffer_t pvr2_next_render_buffer()

   961 {

   962     render_buffer_t result = NULL;

   963     uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );

   964     uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );

   965     uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );

   966     uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;

   968     if( render_addr & 0x01000000 ) { /* vram64 */

   969         render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;

   970     } else { /* vram32 */

   971         render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;

   972     }

   974     int width = pvr2_scene_buffer_width();

   975     int height = pvr2_scene_buffer_height();

   976     int colour_format = pvr2_render_colour_format[render_mode&0x07];

   978     result = pvr2_alloc_render_buffer( render_addr, width, height );

   979     /* Setup the buffer */

   980     if( result != NULL ) {

   981         result->rowstride = render_stride;

   982         result->colour_format = colour_format;

   983         result->scale = render_scale;

   984         result->size = width * height * colour_formats[colour_format].bpp;

   985         result->flushed = FALSE;

   986         result->inverted = TRUE; // render buffers are inverted normally

   987     }

   988     return result;

   989 }

   991 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame )

   992 {

   993     render_buffer_t result = pvr2_alloc_render_buffer( frame->address, frame->width, frame->height );

   994     if( result != NULL ) {

   995         int bpp = colour_formats[frame->colour_format].bpp;

   996         result->rowstride = frame->rowstride;

   997         result->colour_format = frame->colour_format;

   998         result->scale = 0x400;

   999         result->size = frame->width * frame->height * bpp;

  1000         result->flushed = TRUE;

  1001         result->inverted = frame->inverted;

  1002         display_driver->load_frame_buffer( frame, result );

  1003     }

  1004     return result;

  1005 }

  1008 /**

  1009  * Invalidate any caching on the supplied address. Specifically, if it falls

  1010  * within any of the render buffers, flush the buffer back to PVR2 ram.

  1011  */

  1012 gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )

  1013 {

  1014     int i;

  1015     address = address & 0x1FFFFFFF;

  1016     for( i=0; i<render_buffer_count; i++ ) {

  1017         uint32_t bufaddr = render_buffers[i]->address;

  1018         if( bufaddr != -1 && bufaddr <= address &&

  1019                 (bufaddr + render_buffers[i]->size) > address ) {

  1020             if( !render_buffers[i]->flushed ) {

  1021                 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );

  1022                 render_buffers[i]->flushed = TRUE;

  1023             }

  1024             if( isWrite ) {

  1025                 render_buffers[i]->address = -1; /* Invalid */

  1026             }

  1027             return TRUE; /* should never have overlapping buffers */

  1028         }

  1029     }

  1030     return FALSE;

  1031 }