4 * PVR2 (Video) Core module implementation and MMIO registers.
6 * Copyright (c) 2005 Nathan Keynes.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 #define MODULE pvr2_module
27 #include "pvr2/pvr2.h"
28 #include "pvr2/pvr2mmio.h"
29 #include "pvr2/scene.h"
32 #include "pvr2/pvr2mmio.h"
34 unsigned char *video_base;
36 #define MAX_RENDER_BUFFERS 4
38 #define HPOS_PER_FRAME 0
39 #define HPOS_PER_LINECOUNT 1
41 static void pvr2_init( void );
42 static void pvr2_reset( void );
43 static uint32_t pvr2_run_slice( uint32_t );
44 static void pvr2_save_state( FILE *f );
45 static int pvr2_load_state( FILE *f );
46 static void pvr2_update_raster_posn( uint32_t nanosecs );
47 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
48 static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
49 static render_buffer_t pvr2_next_render_buffer( );
50 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame );
51 uint32_t pvr2_get_sync_status();
53 void pvr2_display_frame( void );
55 static int output_colour_formats[] = { COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGR888, COLFMT_BGRA8888 };
57 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,
59 pvr2_save_state, pvr2_load_state };
62 display_driver_t display_driver = NULL;
67 uint32_t line_remainder;
68 uint32_t cycles_run; /* Cycles already executed prior to main time slice */
69 uint32_t irq_hpos_line;
70 uint32_t irq_hpos_line_count;
71 uint32_t irq_hpos_mode;
72 uint32_t irq_hpos_time_ns; /* Time within the line */
75 uint32_t odd_even_field; /* 1 = odd, 0 = even */
76 int32_t palette_changed; /* TRUE if palette has changed since last render */
77 uint32_t padding; /* FIXME: Remove in next DST version */
82 uint32_t line_time_ns;
84 uint32_t hsync_width_ns;
85 uint32_t front_porch_ns;
86 uint32_t back_porch_ns;
87 uint32_t retrace_start_line;
88 uint32_t retrace_end_line;
92 static gchar *save_next_render_filename;
93 static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
94 static uint32_t render_buffer_count = 0;
95 static render_buffer_t displayed_render_buffer = NULL;
96 static uint32_t displayed_border_colour = 0;
99 * Event handler for the hpos callback
101 static void pvr2_hpos_callback( int eventid ) {
102 asic_event( eventid );
103 pvr2_update_raster_posn(sh4r.slice_cycle);
104 if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
105 pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
106 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
107 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
110 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1,
111 pvr2_state.irq_hpos_time_ns );
115 * Event handler for the scanline callbacks. Fires the corresponding
116 * ASIC event, and resets the timer for the next field.
118 static void pvr2_scanline_callback( int eventid )
120 asic_event( eventid );
121 pvr2_update_raster_posn(sh4r.slice_cycle);
122 if( eventid == EVENT_SCANLINE1 ) {
123 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
125 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
129 static void pvr2_gunpos_callback( int eventid )
131 pvr2_update_raster_posn(sh4r.slice_cycle);
132 int hpos = pvr2_state.line_remainder * pvr2_state.dot_clock / 1000000;
133 MMIO_WRITE( PVR2, GUNPOS, ((pvr2_state.line_count<<16)|(hpos&0x3FF)) );
134 asic_event( EVENT_MAPLE_DMA );
137 static void pvr2_init( void )
140 register_io_region( &mmio_region_PVR2 );
141 register_io_region( &mmio_region_PVR2PAL );
142 register_io_region( &mmio_region_PVR2TA );
143 register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
144 register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
145 register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
146 register_event_callback( EVENT_GUNPOS, pvr2_gunpos_callback );
147 video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
151 save_next_render_filename = NULL;
152 for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
153 render_buffers[i] = NULL;
155 render_buffer_count = 0;
156 displayed_render_buffer = NULL;
157 displayed_border_colour = 0;
160 static void pvr2_reset( void )
163 pvr2_state.line_count = 0;
164 pvr2_state.line_remainder = 0;
165 pvr2_state.cycles_run = 0;
166 pvr2_state.irq_vpos1 = 0;
167 pvr2_state.irq_vpos2 = 0;
168 pvr2_state.dot_clock = PVR2_DOT_CLOCK;
169 pvr2_state.back_porch_ns = 4000;
170 pvr2_state.palette_changed = FALSE;
171 mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
172 mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
173 mmio_region_PVR2_write( YUV_ADDR, 0 );
174 mmio_region_PVR2_write( YUV_CFG, 0 );
178 if( display_driver ) {
179 display_driver->display_blank(0);
180 for( i=0; i<render_buffer_count; i++ ) {
181 display_driver->destroy_render_buffer(render_buffers[i]);
182 render_buffers[i] = NULL;
184 render_buffer_count = 0;
188 void pvr2_save_render_buffer( FILE *f, render_buffer_t buffer )
190 struct frame_buffer fbuf;
192 fbuf.width = buffer->width;
193 fbuf.height = buffer->height;
194 fbuf.rowstride = fbuf.width*3;
195 fbuf.colour_format = COLFMT_BGR888;
196 fbuf.inverted = buffer->inverted;
197 fbuf.data = g_malloc0( buffer->width * buffer->height * 3 );
199 display_driver->read_render_buffer( fbuf.data, buffer, fbuf.rowstride, COLFMT_BGR888 );
200 write_png_to_stream( f, &fbuf );
203 fwrite( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
204 fwrite( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
205 fwrite( &buffer->address, sizeof(buffer->address), 1, f );
206 fwrite( &buffer->scale, sizeof(buffer->scale), 1, f );
207 int32_t flushed = (int32_t)buffer->flushed; // Force to 32-bits for save-file consistency
208 fwrite( &flushed, sizeof(flushed), 1, f );
212 render_buffer_t pvr2_load_render_buffer( FILE *f )
214 frame_buffer_t frame = read_png_from_stream( f );
215 if( frame == NULL ) {
219 render_buffer_t buffer = pvr2_frame_buffer_to_render_buffer(frame);
220 if( buffer != NULL ) {
222 fread( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
223 fread( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
224 fread( &buffer->address, sizeof(buffer->address), 1, f );
225 fread( &buffer->scale, sizeof(buffer->scale), 1, f );
226 fread( &flushed, sizeof(flushed), 1, f );
227 buffer->flushed = (gboolean)flushed;
229 fseek( f, sizeof(buffer->rowstride)+sizeof(buffer->colour_format)+
230 sizeof(buffer->address)+sizeof(buffer->scale)+
231 sizeof(int32_t), SEEK_CUR );
239 void pvr2_save_render_buffers( FILE *f )
242 uint32_t has_frontbuffer;
243 fwrite( &render_buffer_count, sizeof(render_buffer_count), 1, f );
244 if( displayed_render_buffer != NULL ) {
246 fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
247 pvr2_save_render_buffer( f, displayed_render_buffer );
250 fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
253 for( i=0; i<render_buffer_count; i++ ) {
254 if( render_buffers[i] != displayed_render_buffer && render_buffers[i] != NULL ) {
255 pvr2_save_render_buffer( f, render_buffers[i] );
260 gboolean pvr2_load_render_buffers( FILE *f )
262 uint32_t count, has_frontbuffer;
265 fread( &count, sizeof(count), 1, f );
266 if( count > MAX_RENDER_BUFFERS ) {
269 fread( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
270 for( i=0; i<render_buffer_count; i++ ) {
271 display_driver->destroy_render_buffer(render_buffers[i]);
272 render_buffers[i] = NULL;
274 render_buffer_count = 0;
276 if( has_frontbuffer ) {
277 displayed_render_buffer = pvr2_load_render_buffer(f);
278 display_driver->display_render_buffer( displayed_render_buffer );
282 for( i=0; i<count; i++ ) {
283 pvr2_load_render_buffer( f );
289 static void pvr2_save_state( FILE *f )
291 pvr2_save_render_buffers( f );
292 fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
293 pvr2_ta_save_state( f );
294 pvr2_yuv_save_state( f );
297 static int pvr2_load_state( FILE *f )
299 if( !pvr2_load_render_buffers(f) )
301 if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
303 if( pvr2_ta_load_state(f) ) {
306 return pvr2_yuv_load_state(f);
310 * Update the current raster position to the given number of nanoseconds,
311 * relative to the last time slice. (ie the raster will be adjusted forward
312 * by nanosecs - nanosecs_already_run_this_timeslice)
314 static void pvr2_update_raster_posn( uint32_t nanosecs )
316 uint32_t old_line_count = pvr2_state.line_count;
317 if( pvr2_state.line_time_ns == 0 ) {
318 return; /* do nothing */
320 pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
321 pvr2_state.cycles_run = nanosecs;
322 while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
323 pvr2_state.line_count ++;
324 pvr2_state.line_remainder -= pvr2_state.line_time_ns;
327 if( pvr2_state.line_count >= pvr2_state.total_lines ) {
328 pvr2_state.line_count -= pvr2_state.total_lines;
329 if( pvr2_state.interlaced ) {
330 pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
333 if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
334 (old_line_count < pvr2_state.retrace_end_line ||
335 old_line_count > pvr2_state.line_count) ) {
336 pvr2_state.frame_count++;
337 pvr2_display_frame();
341 static uint32_t pvr2_run_slice( uint32_t nanosecs )
343 pvr2_update_raster_posn( nanosecs );
344 pvr2_state.cycles_run = 0;
348 int pvr2_get_frame_count()
350 return pvr2_state.frame_count;
353 void pvr2_redraw_display()
355 if( display_driver != NULL ) {
356 if( displayed_render_buffer == NULL ) {
357 display_driver->display_blank(displayed_border_colour);
359 display_driver->display_render_buffer(displayed_render_buffer);
364 gboolean pvr2_save_next_scene( const gchar *filename )
366 if( save_next_render_filename != NULL ) {
367 g_free( save_next_render_filename );
369 save_next_render_filename = g_strdup(filename);
376 * Display the next frame, copying the current contents of video ram to
377 * the window. If the video configuration has changed, first recompute the
378 * new frame size/depth.
380 void pvr2_display_frame( void )
382 int dispmode = MMIO_READ( PVR2, DISP_MODE );
383 int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
384 gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
386 if( display_driver == NULL ) {
387 return; /* can't really do anything much */
388 } else if( !bEnabled ) {
389 /* Output disabled == black */
390 displayed_render_buffer = NULL;
391 displayed_border_colour = 0;
392 display_driver->display_blank( 0 );
393 } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) {
394 /* Enabled but blanked - border colour */
395 displayed_border_colour = MMIO_READ( PVR2, DISP_BORDER );
396 displayed_render_buffer = NULL;
397 display_driver->display_blank( displayed_border_colour );
399 /* Real output - determine dimensions etc */
400 struct frame_buffer fbuf;
401 uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
402 int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
403 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
405 fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
406 fbuf.width = vid_ppl << 2 / colour_formats[fbuf.colour_format].bpp;
407 fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
408 fbuf.size = vid_ppl << 2 * fbuf.height;
409 fbuf.rowstride = (vid_ppl + vid_stride) << 2;
411 /* Determine the field to display, and deinterlace if possible */
412 if( pvr2_state.interlaced ) {
413 if( vid_ppl == vid_stride ) { /* Magic deinterlace */
414 fbuf.height = fbuf.height << 1;
415 fbuf.rowstride = vid_ppl << 2;
416 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
418 /* Just display the field as is, folks. This is slightly tricky -
419 * we pick the field based on which frame is about to come through,
420 * which may not be the same as the odd_even_field.
422 gboolean oddfield = pvr2_state.odd_even_field;
423 if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
424 oddfield = !oddfield;
427 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
429 fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
433 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
435 fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
436 fbuf.inverted = FALSE;
437 fbuf.data = video_base + (fbuf.address&0x00FFFFFF);
439 render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
441 rbuf = pvr2_frame_buffer_to_render_buffer( &fbuf );
443 displayed_render_buffer = rbuf;
445 display_driver->display_render_buffer( rbuf );
451 * This has to handle every single register individually as they all get masked
452 * off differently (and its easier to do it at write time)
454 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
456 if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
457 MMIO_WRITE( PVR2, reg, val );
464 case GUNPOS: /* Read only registers */
467 val &= 0x00000007; /* Do stuff? */
468 MMIO_WRITE( PVR2, reg, val );
470 case RENDER_START: /* Don't really care what value */
471 if( save_next_render_filename != NULL ) {
472 if( pvr2_render_save_scene(save_next_render_filename) == 0 ) {
473 INFO( "Saved scene to %s", save_next_render_filename);
475 g_free( save_next_render_filename );
476 save_next_render_filename = NULL;
479 render_buffer_t buffer = pvr2_next_render_buffer();
480 if( buffer != NULL ) {
481 pvr2_scene_render( buffer );
483 asic_event( EVENT_PVR_RENDER_DONE );
485 case RENDER_POLYBASE:
486 MMIO_WRITE( PVR2, reg, val&0x00F00000 );
489 MMIO_WRITE( PVR2, reg, val&0x00010101 );
492 MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
495 MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
498 MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
501 MMIO_WRITE( PVR2, reg, val&0x000001FF );
505 MMIO_WRITE( PVR2, reg, val );
506 pvr2_update_raster_posn(sh4r.slice_cycle);
509 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
510 pvr2_update_raster_posn(sh4r.slice_cycle);
513 MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
517 MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
520 MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
523 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
526 MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
527 pvr2_state.irq_hpos_line = val & 0x03FF;
528 pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
529 pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
530 switch( pvr2_state.irq_hpos_mode ) {
531 case 3: /* Reserved - treat as 0 */
532 case 0: /* Once per frame at specified line */
533 pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
535 case 2: /* Once per line - as per-line-count */
536 pvr2_state.irq_hpos_line = 1;
537 pvr2_state.irq_hpos_mode = 1;
538 case 1: /* Once per N lines */
539 pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
540 pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) +
541 pvr2_state.irq_hpos_line_count;
542 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
543 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
545 pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
547 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
548 pvr2_state.irq_hpos_time_ns );
551 val = val & 0x03FF03FF;
552 pvr2_state.irq_vpos1 = (val >> 16);
553 pvr2_state.irq_vpos2 = val & 0x03FF;
554 pvr2_update_raster_posn(sh4r.slice_cycle);
555 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
556 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
557 MMIO_WRITE( PVR2, reg, val );
559 case RENDER_NEARCLIP:
560 MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
563 MMIO_WRITE( PVR2, reg, val&0x000001FF );
566 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
569 MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
572 MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
575 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
578 MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
581 MMIO_WRITE( PVR2, reg, val&0x000000FF );
584 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
587 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
589 case RENDER_FOGTBLCOL:
590 case RENDER_FOGVRTCOL:
591 MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
593 case RENDER_FOGCOEFF:
594 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
598 MMIO_WRITE( PVR2, reg, val );
601 MMIO_WRITE( PVR2, reg, val&0x00031F1F );
604 MMIO_WRITE( PVR2, reg, val&0x00000003 );
606 case RENDER_ALPHA_REF:
607 MMIO_WRITE( PVR2, reg, val&0x000000FF );
609 /********** CRTC registers *************/
612 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
615 val = val & 0x03FF03FF;
616 MMIO_WRITE( PVR2, reg, val );
617 pvr2_update_raster_posn(sh4r.slice_cycle);
618 pvr2_state.total_lines = (val >> 16) + 1;
619 pvr2_state.line_size = (val & 0x03FF) + 1;
620 pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
621 pvr2_state.retrace_end_line = 0x2A;
622 pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
623 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
624 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
625 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
626 pvr2_state.irq_hpos_time_ns );
629 MMIO_WRITE( PVR2, reg, val&0x000003FF );
630 pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
633 pvr2_state.vsync_lines = (val >> 8) & 0x0F;
634 pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
635 MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
638 MMIO_WRITE( PVR2, reg, val&0x003F01FF );
642 pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
643 MMIO_WRITE( PVR2, reg, val );
646 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
649 /*********** Tile accelerator registers ***********/
652 /* Readonly registers */
657 MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
659 case RENDER_TILEBASE:
662 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
665 MMIO_WRITE( PVR2, reg, val&0x000F003F );
668 MMIO_WRITE( PVR2, reg, val&0x00133333 );
671 if( val & 0x80000000 )
676 /**************** Scaler registers? ****************/
678 MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
682 val = val & 0x00FFFFF8;
683 MMIO_WRITE( PVR2, reg, val );
684 pvr2_yuv_init( val );
687 MMIO_WRITE( PVR2, reg, val&0x01013F3F );
688 pvr2_yuv_set_config(val);
691 /**************** Unknowns ***************/
693 MMIO_WRITE( PVR2, reg, val&0x000007FF );
696 MMIO_WRITE( PVR2, reg, val&0x00000007 );
699 MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
702 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
705 MMIO_WRITE( PVR2, reg, val&0x00000001 );
708 MMIO_WRITE( PVR2, reg, val&0x0300FFFF );
714 * Calculate the current read value of the syncstat register, using
715 * the current SH4 clock time as an offset from the last timeslice.
716 * The register reads (LSB to MSB) as:
717 * 0..9 Current scan line
718 * 10 Odd/even field (1 = odd, 0 = even)
719 * 11 Display active (including border and overscan)
720 * 12 Horizontal sync off
721 * 13 Vertical sync off
722 * Note this method is probably incorrect for anything other than straight
723 * interlaced PAL/NTSC, and needs further testing.
725 uint32_t pvr2_get_sync_status()
727 pvr2_update_raster_posn(sh4r.slice_cycle);
728 uint32_t result = pvr2_state.line_count;
730 if( pvr2_state.odd_even_field ) {
733 if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
734 if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
735 result |= 0x1000; /* !HSYNC */
737 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
738 if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
739 result |= 0x2800; /* Display active */
741 result |= 0x2000; /* Front porch */
745 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
746 if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
747 result |= 0x3800; /* Display active */
752 result |= 0x1000; /* Back porch */
759 * Schedule a "scanline" event. This actually goes off at
760 * 2 * line in even fields and 2 * line + 1 in odd fields.
761 * Otherwise this behaves as per pvr2_schedule_line_event().
762 * The raster position should be updated before calling this
764 * @param eventid Event to fire at the specified time
765 * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
767 * @param hpos_ns Nanoseconds into the line at which to fire.
769 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
771 uint32_t field = pvr2_state.odd_even_field;
772 if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
775 if( hpos_ns > pvr2_state.line_time_ns ) {
776 hpos_ns = pvr2_state.line_time_ns;
784 if( line < pvr2_state.total_lines ) {
787 if( line <= pvr2_state.line_count ) {
788 lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
790 lines = (line - pvr2_state.line_count);
792 if( lines <= minimum_lines ) {
793 lines += pvr2_state.total_lines;
795 time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
796 event_schedule( eventid, time );
798 event_cancel( eventid );
802 void pvr2_queue_gun_event( int xpos, int ypos )
804 pvr2_update_raster_posn(sh4r.slice_cycle);
805 pvr2_schedule_scanline_event( EVENT_GUNPOS, (ypos >> 1) + pvr2_state.vsync_lines, 0,
806 (1000000 * xpos / pvr2_state.dot_clock) + pvr2_state.hsync_width_ns );
809 MMIO_REGION_READ_FN( PVR2, reg )
813 return pvr2_get_sync_status();
815 return MMIO_READ( PVR2, reg );
819 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
821 MMIO_WRITE( PVR2PAL, reg, val );
822 pvr2_state.palette_changed = TRUE;
825 void pvr2_check_palette_changed()
827 if( pvr2_state.palette_changed ) {
828 texcache_invalidate_palette();
829 pvr2_state.palette_changed = FALSE;
833 MMIO_REGION_READ_DEFFN( PVR2PAL );
835 void pvr2_set_base_address( uint32_t base )
837 mmio_region_PVR2_write( DISP_ADDR1, base );
843 int32_t mmio_region_PVR2TA_read( uint32_t reg )
848 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
850 pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );
854 * Find the render buffer corresponding to the requested output frame
855 * (does not consider texture renders).
856 * @return the render_buffer if found, or null if no such buffer.
858 * Note: Currently does not consider "partial matches", ie partial
859 * frame overlap - it probably needs to do this.
861 render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
864 for( i=0; i<render_buffer_count; i++ ) {
865 if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
866 return render_buffers[i];
873 * Allocate a render buffer with the requested parameters.
874 * The order of preference is:
875 * 1. An existing buffer with the same address. (not flushed unless the new
876 * size is smaller than the old one).
877 * 2. An existing buffer with the same size chosen by LRU order. Old buffer
878 * is flushed to vram.
879 * 3. A new buffer if one can be created.
880 * 4. The current display buff
881 * Note: The current display field(s) will never be overwritten except as a last
884 render_buffer_t pvr2_alloc_render_buffer( sh4addr_t render_addr, int width, int height )
887 render_buffer_t result = NULL;
889 /* Check existing buffers for an available buffer */
890 for( i=0; i<render_buffer_count; i++ ) {
891 if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
892 /* needs to be the right dimensions */
893 if( render_buffers[i]->address == render_addr ) {
894 if( displayed_render_buffer == render_buffers[i] ) {
895 /* Same address, but we can't use it because the
896 * display has it. Mark it as unaddressed for later.
898 render_buffers[i]->address = -1;
901 result = render_buffers[i];
904 } else if( render_buffers[i]->address == -1 && result == NULL &&
905 displayed_render_buffer != render_buffers[i] ) {
906 result = render_buffers[i];
909 } else if( render_buffers[i]->address == render_addr ) {
910 /* right address, wrong size - if it's larger, flush it, otherwise
912 if( render_buffers[i]->width * render_buffers[i]->height >
914 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
916 render_buffers[i]->address = -1;
920 /* Nothing available - make one */
921 if( result == NULL ) {
922 if( render_buffer_count == MAX_RENDER_BUFFERS ) {
923 /* maximum buffers reached - need to throw one away */
924 uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
925 uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
926 for( i=0; i<render_buffer_count; i++ ) {
927 if( render_buffers[i]->address != field1_addr &&
928 render_buffers[i]->address != field2_addr &&
929 render_buffers[i] != displayed_render_buffer ) {
930 /* Never throw away the current "front buffer(s)" */
931 result = render_buffers[i];
932 if( !result->flushed ) {
933 pvr2_render_buffer_copy_to_sh4( result );
935 if( result->width != width || result->height != height ) {
936 display_driver->destroy_render_buffer(render_buffers[i]);
937 result = display_driver->create_render_buffer(width,height,0);
938 render_buffers[i] = result;
944 result = display_driver->create_render_buffer(width,height,0);
945 if( result != NULL ) {
946 render_buffers[render_buffer_count++] = result;
951 if( result != NULL ) {
952 result->address = render_addr;
958 * Allocate a render buffer based on the current rendering settings
960 render_buffer_t pvr2_next_render_buffer()
962 render_buffer_t result = NULL;
963 uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
964 uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
965 uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
966 uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
968 if( render_addr & 0x01000000 ) { /* vram64 */
969 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
970 } else { /* vram32 */
971 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
974 int width = pvr2_scene_buffer_width();
975 int height = pvr2_scene_buffer_height();
976 int colour_format = pvr2_render_colour_format[render_mode&0x07];
978 result = pvr2_alloc_render_buffer( render_addr, width, height );
979 /* Setup the buffer */
980 if( result != NULL ) {
981 result->rowstride = render_stride;
982 result->colour_format = colour_format;
983 result->scale = render_scale;
984 result->size = width * height * colour_formats[colour_format].bpp;
985 result->flushed = FALSE;
986 result->inverted = TRUE; // render buffers are inverted normally
991 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame )
993 render_buffer_t result = pvr2_alloc_render_buffer( frame->address, frame->width, frame->height );
994 if( result != NULL ) {
995 int bpp = colour_formats[frame->colour_format].bpp;
996 result->rowstride = frame->rowstride;
997 result->colour_format = frame->colour_format;
998 result->scale = 0x400;
999 result->size = frame->width * frame->height * bpp;
1000 result->flushed = TRUE;
1001 result->inverted = frame->inverted;
1002 display_driver->load_frame_buffer( frame, result );
1009 * Invalidate any caching on the supplied address. Specifically, if it falls
1010 * within any of the render buffers, flush the buffer back to PVR2 ram.
1012 gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
1015 address = address & 0x1FFFFFFF;
1016 for( i=0; i<render_buffer_count; i++ ) {
1017 uint32_t bufaddr = render_buffers[i]->address;
1018 if( bufaddr != -1 && bufaddr <= address &&
1019 (bufaddr + render_buffers[i]->size) > address ) {
1020 if( !render_buffers[i]->flushed ) {
1021 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
1022 render_buffers[i]->flushed = TRUE;
1025 render_buffers[i]->address = -1; /* Invalid */
1027 return TRUE; /* should never have overlapping buffers */
.