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lxdream.org :: lxdream/src/sh4/sh4.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4.c
changeset 586:2a3ba82cf243
prev526:ba3da45b5754
next591:7b9612fd2395
author nkeynes
date Tue Jan 15 20:50:23 2008 +0000 (14 years ago)
permissions -rw-r--r--
last change Merged lxdream-mmu r570:596 to trunk
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 parent module for all CPU modes and SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "dreamcast.h"
    24 #include "sh4/sh4core.h"
    25 #include "sh4/sh4mmio.h"
    26 #include "sh4/intc.h"
    27 #include "sh4/xltcache.h"
    28 #include "sh4/sh4stat.h"
    29 #include "mem.h"
    30 #include "clock.h"
    31 #include "syscall.h"
    33 void sh4_init( void );
    34 void sh4_xlat_init( void );
    35 void sh4_reset( void );
    36 void sh4_start( void );
    37 void sh4_stop( void );
    38 void sh4_save_state( FILE *f );
    39 int sh4_load_state( FILE *f );
    41 uint32_t sh4_run_slice( uint32_t );
    42 uint32_t sh4_xlat_run_slice( uint32_t );
    44 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    45 				       NULL, sh4_run_slice, sh4_stop,
    46 				       sh4_save_state, sh4_load_state };
    48 struct sh4_registers sh4r;
    49 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    50 int sh4_breakpoint_count = 0;
    51 sh4ptr_t sh4_main_ram;
    52 static gboolean sh4_use_translator = FALSE;
    53 struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 };
    55 void sh4_set_use_xlat( gboolean use )
    56 {
    57 // No-op if the translator was not built
    58 #ifdef SH4_TRANSLATOR
    59     if( use ) {
    60 	xlat_cache_init();
    61 	sh4_x86_init();
    62 	sh4_module.run_time_slice = sh4_xlat_run_slice;
    63     } else {
    64 	sh4_module.run_time_slice = sh4_run_slice;
    65     }
    66     sh4_use_translator = use;
    67 #endif
    68 }
    70 gboolean sh4_is_using_xlat()
    71 {
    72     return sh4_use_translator;
    73 }
    75 void sh4_init(void)
    76 {
    77     register_io_regions( mmio_list_sh4mmio );
    78     sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
    79     MMU_init();
    80     sh4_reset();
    81 }
    83 void sh4_reset(void)
    84 {
    85     if(	sh4_use_translator ) {
    86 	xlat_flush_cache();
    87     }
    89     /* zero everything out, for the sake of having a consistent state. */
    90     memset( &sh4r, 0, sizeof(sh4r) );
    92     /* Resume running if we were halted */
    93     sh4r.sh4_state = SH4_STATE_RUNNING;
    95     sh4r.pc    = 0xA0000000;
    96     sh4r.new_pc= 0xA0000002;
    97     sh4r.vbr   = 0x00000000;
    98     sh4r.fpscr = 0x00040001;
    99     sh4r.sr    = 0x700000F0;
   100     sh4r.fr_bank = &sh4r.fr[0][0];
   102     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
   103     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
   105     /* Peripheral modules */
   106     CPG_reset();
   107     INTC_reset();
   108     MMU_reset();
   109     TMU_reset();
   110     SCIF_reset();
   111     sh4_stats_reset();
   112 }
   114 void sh4_stop(void)
   115 {
   116     if(	sh4_use_translator ) {
   117 	/* If we were running with the translator, update new_pc and in_delay_slot */
   118 	sh4r.new_pc = sh4r.pc+2;
   119 	sh4r.in_delay_slot = FALSE;
   120     }
   122 }
   124 void sh4_save_state( FILE *f )
   125 {
   126     if(	sh4_use_translator ) {
   127 	/* If we were running with the translator, update new_pc and in_delay_slot */
   128 	sh4r.new_pc = sh4r.pc+2;
   129 	sh4r.in_delay_slot = FALSE;
   130     }
   132     fwrite( &sh4r, sizeof(sh4r), 1, f );
   133     MMU_save_state( f );
   134     INTC_save_state( f );
   135     TMU_save_state( f );
   136     SCIF_save_state( f );
   137 }
   139 int sh4_load_state( FILE * f )
   140 {
   141     if(	sh4_use_translator ) {
   142 	xlat_flush_cache();
   143     }
   144     fread( &sh4r, sizeof(sh4r), 1, f );
   145     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0]; // Fixup internal FR pointer
   146     MMU_load_state( f );
   147     INTC_load_state( f );
   148     TMU_load_state( f );
   149     return SCIF_load_state( f );
   150 }
   153 void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
   154 {
   155     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   156     sh4_breakpoints[sh4_breakpoint_count].type = type;
   157     if( sh4_use_translator ) {
   158 	xlat_invalidate_word( pc );
   159     }
   160     sh4_breakpoint_count++;
   161 }
   163 gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
   164 {
   165     int i;
   167     for( i=0; i<sh4_breakpoint_count; i++ ) {
   168 	if( sh4_breakpoints[i].address == pc && 
   169 	    sh4_breakpoints[i].type == type ) {
   170 	    while( ++i < sh4_breakpoint_count ) {
   171 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   172 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   173 	    }
   174 	    if( sh4_use_translator ) {
   175 		xlat_invalidate_word( pc );
   176 	    }
   177 	    sh4_breakpoint_count--;
   178 	    return TRUE;
   179 	}
   180     }
   181     return FALSE;
   182 }
   184 int sh4_get_breakpoint( uint32_t pc )
   185 {
   186     int i;
   187     for( i=0; i<sh4_breakpoint_count; i++ ) {
   188 	if( sh4_breakpoints[i].address == pc )
   189 	    return sh4_breakpoints[i].type;
   190     }
   191     return 0;
   192 }
   194 void sh4_set_pc( int pc )
   195 {
   196     sh4r.pc = pc;
   197     sh4r.new_pc = pc+2;
   198 }
   201 /******************************* Support methods ***************************/
   203 static void sh4_switch_banks( )
   204 {
   205     uint32_t tmp[8];
   207     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   208     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   209     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   210 }
   212 void sh4_write_sr( uint32_t newval )
   213 {
   214     int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
   215     int newbank = (newval&SR_MDRB) == SR_MDRB;
   216     if( oldbank != newbank )
   217         sh4_switch_banks();
   218     sh4r.sr = newval;
   219     sh4r.t = (newval&SR_T) ? 1 : 0;
   220     sh4r.s = (newval&SR_S) ? 1 : 0;
   221     sh4r.m = (newval&SR_M) ? 1 : 0;
   222     sh4r.q = (newval&SR_Q) ? 1 : 0;
   223     intc_mask_changed();
   224 }
   226 uint32_t sh4_read_sr( void )
   227 {
   228     /* synchronize sh4r.sr with the various bitflags */
   229     sh4r.sr &= SR_MQSTMASK;
   230     if( sh4r.t ) sh4r.sr |= SR_T;
   231     if( sh4r.s ) sh4r.sr |= SR_S;
   232     if( sh4r.m ) sh4r.sr |= SR_M;
   233     if( sh4r.q ) sh4r.sr |= SR_Q;
   234     return sh4r.sr;
   235 }
   239 #define RAISE( x, v ) do{			\
   240     if( sh4r.vbr == 0 ) { \
   241         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   242         dreamcast_stop(); return FALSE;	\
   243     } else { \
   244         sh4r.spc = sh4r.pc;	\
   245         sh4r.ssr = sh4_read_sr(); \
   246         sh4r.sgr = sh4r.r[15]; \
   247         MMIO_WRITE(MMU,EXPEVT,x); \
   248         sh4r.pc = sh4r.vbr + v; \
   249         sh4r.new_pc = sh4r.pc + 2; \
   250         sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   251 	if( sh4r.in_delay_slot ) { \
   252 	    sh4r.in_delay_slot = 0; \
   253 	    sh4r.spc -= 2; \
   254 	} \
   255     } \
   256     return TRUE; } while(0)
   258 /**
   259  * Raise a general CPU exception for the specified exception code.
   260  * (NOT for TRAPA or TLB exceptions)
   261  */
   262 gboolean sh4_raise_exception( int code )
   263 {
   264     RAISE( code, EXV_EXCEPTION );
   265 }
   267 /**
   268  * Raise a CPU reset exception with the specified exception code.
   269  */
   270 gboolean sh4_raise_reset( int code )
   271 {
   272     // FIXME: reset modules as per "manual reset"
   273     sh4_reset();
   274     MMIO_WRITE(MMU,EXPEVT,code);
   275     sh4r.vbr = 0;
   276     sh4r.pc = 0xA0000000;
   277     sh4r.new_pc = sh4r.pc + 2;
   278     sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
   279 		  &(~SR_FD) );
   280 }
   282 gboolean sh4_raise_trap( int trap )
   283 {
   284     MMIO_WRITE( MMU, TRA, trap<<2 );
   285     RAISE( EXC_TRAP, EXV_EXCEPTION );
   286 }
   288 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
   289     if( sh4r.in_delay_slot ) {
   290 	return sh4_raise_exception(slot_code);
   291     } else {
   292 	return sh4_raise_exception(normal_code);
   293     }
   294 }
   296 gboolean sh4_raise_tlb_exception( int code )
   297 {
   298     RAISE( code, EXV_TLBMISS );
   299 }
   301 void sh4_accept_interrupt( void )
   302 {
   303     uint32_t code = intc_accept_interrupt();
   304     sh4r.ssr = sh4_read_sr();
   305     sh4r.spc = sh4r.pc;
   306     sh4r.sgr = sh4r.r[15];
   307     sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   308     MMIO_WRITE( MMU, INTEVT, code );
   309     sh4r.pc = sh4r.vbr + 0x600;
   310     sh4r.new_pc = sh4r.pc + 2;
   311     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   312 }
   314 void signsat48( void )
   315 {
   316     if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
   317 	sh4r.mac = 0xFFFF800000000000LL;
   318     else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
   319 	sh4r.mac = 0x00007FFFFFFFFFFFLL;
   320 }
   322 void sh4_fsca( uint32_t anglei, float *fr )
   323 {
   324     float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
   325     *fr++ = cosf(angle);
   326     *fr = sinf(angle);
   327 }
   329 void sh4_sleep(void)
   330 {
   331     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   332 	sh4r.sh4_state = SH4_STATE_STANDBY;
   333     } else {
   334 	sh4r.sh4_state = SH4_STATE_SLEEP;
   335     }
   336 }
   338 /**
   339  * Compute the matrix tranform of fv given the matrix xf.
   340  * Both fv and xf are word-swapped as per the sh4r.fr banks
   341  */
   342 void sh4_ftrv( float *target, float *xf )
   343 {
   344     float fv[4] = { target[1], target[0], target[3], target[2] };
   345     target[1] = xf[1] * fv[0] + xf[5]*fv[1] +
   346 	xf[9]*fv[2] + xf[13]*fv[3];
   347     target[0] = xf[0] * fv[0] + xf[4]*fv[1] +
   348 	xf[8]*fv[2] + xf[12]*fv[3];
   349     target[3] = xf[3] * fv[0] + xf[7]*fv[1] +
   350 	xf[11]*fv[2] + xf[15]*fv[3];
   351     target[2] = xf[2] * fv[0] + xf[6]*fv[1] +
   352 	xf[10]*fv[2] + xf[14]*fv[3];
   353 }
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