2 * $Id: sh4core.c,v 1.25 2006-03-22 11:58:01 nkeynes Exp $
4 * SH4 emulation core, and parent module for all the SH4 peripheral
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE sh4_module
23 #include "sh4/sh4core.h"
24 #include "sh4/sh4mmio.h"
30 #define MAX_INT 0x7FFFFFFF
31 #define MIN_INT 0x80000000
32 #define MAX_INTF 2147483647.0
33 #define MIN_INTF -2147483648.0
35 /* CPU-generated exception code/vector pairs */
36 #define EXC_POWER_RESET 0x000 /* vector special */
37 #define EXC_MANUAL_RESET 0x020
38 #define EXC_SLOT_ILLEGAL 0x1A0
39 #define EXC_ILLEGAL 0x180
40 #define EXV_ILLEGAL 0x100
41 #define EXC_TRAP 0x160
42 #define EXV_TRAP 0x100
43 #define EXC_FPDISABLE 0x800
44 #define EXV_FPDISABLE 0x100
46 /********************** SH4 Module Definition ****************************/
48 void sh4_init( void );
49 void sh4_reset( void );
50 uint32_t sh4_run_slice( uint32_t );
51 void sh4_start( void );
52 void sh4_stop( void );
53 void sh4_save_state( FILE *f );
54 int sh4_load_state( FILE *f );
56 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
57 NULL, sh4_run_slice, sh4_stop,
58 sh4_save_state, sh4_load_state };
60 struct sh4_registers sh4r;
64 register_io_regions( mmio_list_sh4mmio );
71 /* zero everything out, for the sake of having a consistent state. */
72 memset( &sh4r, 0, sizeof(sh4r) );
74 /* Resume running if we were halted */
75 sh4r.sh4_state = SH4_STATE_RUNNING;
78 sh4r.new_pc= 0xA0000002;
79 sh4r.vbr = 0x00000000;
80 sh4r.fpscr = 0x00040001;
83 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
84 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
86 /* Peripheral modules */
91 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
92 static int sh4_breakpoint_count = 0;
94 void sh4_set_breakpoint( uint32_t pc, int type )
96 sh4_breakpoints[sh4_breakpoint_count].address = pc;
97 sh4_breakpoints[sh4_breakpoint_count].type = type;
98 sh4_breakpoint_count++;
101 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
105 for( i=0; i<sh4_breakpoint_count; i++ ) {
106 if( sh4_breakpoints[i].address == pc &&
107 sh4_breakpoints[i].type == type ) {
108 while( ++i < sh4_breakpoint_count ) {
109 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
110 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
112 sh4_breakpoint_count--;
119 int sh4_get_breakpoint( uint32_t pc )
122 for( i=0; i<sh4_breakpoint_count; i++ ) {
123 if( sh4_breakpoints[i].address == pc )
124 return sh4_breakpoints[i].type;
129 uint32_t sh4_run_slice( uint32_t nanosecs )
131 int target = sh4r.icount + nanosecs / sh4_cpu_period;
132 int start = sh4r.icount;
135 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
136 if( sh4r.int_pending != 0 )
137 sh4r.sh4_state = SH4_STATE_RUNNING;;
140 for( sh4r.slice_cycle = 0; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
141 if( !sh4_execute_instruction() )
143 #ifdef ENABLE_DEBUG_MODE
144 for( i=0; i<sh4_breakpoint_count; i++ ) {
145 if( sh4_breakpoints[i].address == sh4r.pc ) {
149 if( i != sh4_breakpoint_count ) {
151 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
152 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
158 /* If we aborted early, but the cpu is still technically running,
159 * we're doing a hard abort - cut the timeslice back to what we
162 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
163 nanosecs = sh4r.slice_cycle;
165 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
166 TMU_run_slice( nanosecs );
167 SCIF_run_slice( nanosecs );
169 sh4r.icount += sh4r.slice_cycle / sh4_cpu_period;
178 void sh4_save_state( FILE *f )
180 fwrite( &sh4r, sizeof(sh4r), 1, f );
182 SCIF_save_state( f );
185 int sh4_load_state( FILE * f )
187 fread( &sh4r, sizeof(sh4r), 1, f );
189 return SCIF_load_state( f );
192 /********************** SH4 emulation core ****************************/
194 void sh4_set_pc( int pc )
200 #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
201 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
203 #define RAISE( x, v ) do{ \
204 if( sh4r.vbr == 0 ) { \
205 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
206 dreamcast_stop(); return FALSE; \
208 sh4r.spc = sh4r.pc + 2; \
209 sh4r.ssr = sh4_read_sr(); \
210 sh4r.sgr = sh4r.r[15]; \
211 MMIO_WRITE(MMU,EXPEVT,x); \
212 sh4r.pc = sh4r.vbr + v; \
213 sh4r.new_pc = sh4r.pc + 2; \
214 sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
216 return TRUE; } while(0)
218 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
219 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
220 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
221 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
222 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
223 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
225 #define MEM_FR_READ( addr, reg ) *((uint32_t *)&FR(reg)) = sh4_read_long(addr)
227 #define MEM_DR_READ( addr, reg ) do { \
228 *((uint32_t *)&FR((reg) & 0x0E)) = sh4_read_long(addr); \
229 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4); } while(0)
231 #define MEM_FR_WRITE( addr, reg ) sh4_write_long( addr, *((uint32_t *)&FR((reg))) )
233 #define MEM_DR_WRITE( addr, reg ) do { \
234 sh4_write_long( addr, *((uint32_t *)&FR((reg)&0x0E)) ); \
235 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); } while(0)
237 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
239 #define MEM_FP_READ( addr, reg ) if( IS_FPU_DOUBLESIZE() ) MEM_DR_READ(addr, reg ); else MEM_FR_READ( addr, reg )
241 #define MEM_FP_WRITE( addr, reg ) if( IS_FPU_DOUBLESIZE() ) MEM_DR_WRITE(addr, reg ); else MEM_FR_WRITE( addr, reg )
243 #define CHECK( x, c, v ) if( !x ) RAISE( c, v )
244 #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
245 #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
246 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
247 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }
249 static void sh4_switch_banks( )
253 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
254 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
255 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
258 static void sh4_load_sr( uint32_t newval )
260 if( (newval ^ sh4r.sr) & SR_RB )
263 sh4r.t = (newval&SR_T) ? 1 : 0;
264 sh4r.s = (newval&SR_S) ? 1 : 0;
265 sh4r.m = (newval&SR_M) ? 1 : 0;
266 sh4r.q = (newval&SR_Q) ? 1 : 0;
270 static uint32_t sh4_read_sr( void )
272 /* synchronize sh4r.sr with the various bitflags */
273 sh4r.sr &= SR_MQSTMASK;
274 if( sh4r.t ) sh4r.sr |= SR_T;
275 if( sh4r.s ) sh4r.sr |= SR_S;
276 if( sh4r.m ) sh4r.sr |= SR_M;
277 if( sh4r.q ) sh4r.sr |= SR_Q;
280 /* function for external use */
281 void sh4_raise_exception( int code, int vector )
286 static void sh4_accept_interrupt( void )
288 uint32_t code = intc_accept_interrupt();
289 sh4r.ssr = sh4_read_sr();
291 sh4r.sgr = sh4r.r[15];
292 sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
293 MMIO_WRITE( MMU, INTEVT, code );
294 sh4r.pc = sh4r.vbr + 0x600;
295 sh4r.new_pc = sh4r.pc + 2;
296 // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
299 gboolean sh4_execute_instruction( void )
311 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
312 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
313 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
314 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
315 #define DISP8(ir) (ir&0x00FF)
316 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
317 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
318 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
319 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
320 #define FRNn(ir) ((ir&0x0F00)>>8)
321 #define FRMn(ir) ((ir&0x00F0)>>4)
322 #define DRNn(ir) ((ir&0x0E00)>>9)
323 #define DRMn(ir) ((ir&0x00E0)>>5)
324 #define FVN(ir) ((ir&0x0C00)>>8)
325 #define FVM(ir) ((ir&0x0300)>>6)
326 #define FRN(ir) FR(FRNn(ir))
327 #define FRM(ir) FR(FRMn(ir))
328 #define FRNi(ir) (*((uint32_t *)&FR(FRNn(ir))))
329 #define FRMi(ir) (*((uint32_t *)&FR(FRMn(ir))))
330 #define DRN(ir) DRb(DRNn(ir), ir&0x0100)
331 #define DRM(ir) DRb(DRMn(ir),ir&0x0010)
332 #define DRNi(ir) (*((uint64_t *)&DR(FRNn(ir))))
333 #define DRMi(ir) (*((uint64_t *)&DR(FRMn(ir))))
334 #define FPULf *((float *)&sh4r.fpul)
335 #define FPULi (sh4r.fpul)
337 if( SH4_INT_PENDING() )
338 sh4_accept_interrupt();
341 if( pc > 0xFFFFFF00 ) {
343 syscall_invoke( pc );
344 sh4r.in_delay_slot = 0;
345 pc = sh4r.pc = sh4r.pr;
346 sh4r.new_pc = sh4r.pc + 2;
348 ir = MEM_READ_WORD(pc);
351 switch( (ir&0xF000)>>12 ) {
352 case 0: /* 0000nnnnmmmmxxxx */
353 switch( ir&0x000F ) {
355 switch( (ir&0x00F0)>>4 ) {
356 case 0: /* STC SR, Rn */
358 RN(ir) = sh4_read_sr();
360 case 1: /* STC GBR, Rn */
363 case 2: /* STC VBR, Rn */
367 case 3: /* STC SSR, Rn */
371 case 4: /* STC SPC, Rn */
375 case 8: case 9: case 10: case 11: case 12: case 13:
376 case 14: case 15:/* STC Rm_bank, Rn */
378 RN(ir) = RN_BANK(ir);
384 switch( (ir&0x00F0)>>4 ) {
385 case 0: /* BSRF Rn */
386 CHECKDEST( pc + 4 + RN(ir) );
388 sh4r.in_delay_slot = 1;
389 sh4r.pr = sh4r.pc + 4;
390 sh4r.pc = sh4r.new_pc;
391 sh4r.new_pc = pc + 4 + RN(ir);
393 case 2: /* BRAF Rn */
394 CHECKDEST( pc + 4 + RN(ir) );
396 sh4r.in_delay_slot = 1;
397 sh4r.pc = sh4r.new_pc;
398 sh4r.new_pc = pc + 4 + RN(ir);
400 case 8: /* PREF [Rn] */
402 if( (tmp & 0xFC000000) == 0xE0000000 ) {
403 /* Store queue operation */
404 int queue = (tmp&0x20)>>2;
405 int32_t *src = &sh4r.store_queue[queue];
406 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
407 uint32_t target = tmp&0x03FFFFE0 | hi;
408 mem_copy_to_sh4( target, src, 32 );
409 //if( (target &0xFF000000) != 0x04000000 )
410 // WARN( "Executed SQ%c => %08X",
411 // (queue == 0 ? '0' : '1'), target );
414 case 9: /* OCBI [Rn] */
415 case 10:/* OCBP [Rn] */
416 case 11:/* OCBWB [Rn] */
419 case 12:/* MOVCA.L R0, [Rn] */
424 case 4: /* MOV.B Rm, [R0 + Rn] */
425 MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
427 case 5: /* MOV.W Rm, [R0 + Rn] */
428 MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
430 case 6: /* MOV.L Rm, [R0 + Rn] */
431 MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
433 case 7: /* MUL.L Rm, Rn */
434 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
438 switch( (ir&0x0FF0)>>4 ) {
460 if( (ir&0x00F0) == 0x20 ) /* MOVT Rn */
462 else if( ir == 0x0019 ) /* DIV0U */
463 sh4r.m = sh4r.q = sh4r.t = 0;
464 else if( ir == 0x0009 )
469 switch( (ir&0x00F0) >> 4 ) {
470 case 0: /* STS MACH, Rn */
471 RN(ir) = sh4r.mac >> 32;
473 case 1: /* STS MACL, Rn */
474 RN(ir) = (uint32_t)sh4r.mac;
476 case 2: /* STS PR, Rn */
479 case 3: /* STC SGR, Rn */
483 case 5:/* STS FPUL, Rn */
486 case 6: /* STS FPSCR, Rn */
489 case 15:/* STC DBR, Rn */
497 switch( (ir&0x0FF0)>>4 ) {
499 CHECKDEST( sh4r.pr );
501 sh4r.in_delay_slot = 1;
502 sh4r.pc = sh4r.new_pc;
503 sh4r.new_pc = sh4r.pr;
506 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
507 sh4r.sh4_state = SH4_STATE_STANDBY;
509 sh4r.sh4_state = SH4_STATE_SLEEP;
511 return FALSE; /* Halt CPU */
514 CHECKDEST( sh4r.spc );
516 sh4r.in_delay_slot = 1;
517 sh4r.pc = sh4r.new_pc;
518 sh4r.new_pc = sh4r.spc;
519 sh4_load_sr( sh4r.ssr );
524 case 12:/* MOV.B [R0+R%d], R%d */
525 RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
527 case 13:/* MOV.W [R0+R%d], R%d */
528 RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
530 case 14:/* MOV.L [R0+R%d], R%d */
531 RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
533 case 15:/* MAC.L [Rm++], [Rn++] */
534 tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
535 SIGNEXT32(MEM_READ_LONG(RN(ir))) );
537 /* 48-bit Saturation. Yuch */
538 tmpl += SIGNEXT48(sh4r.mac);
539 if( tmpl < 0xFFFF800000000000LL )
540 tmpl = 0xFFFF800000000000LL;
541 else if( tmpl > 0x00007FFFFFFFFFFFLL )
542 tmpl = 0x00007FFFFFFFFFFFLL;
543 sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
544 (tmpl&0x0000FFFFFFFFFFFFLL);
545 } else sh4r.mac = tmpl;
554 case 1: /* 0001nnnnmmmmdddd */
555 /* MOV.L Rm, [Rn + disp4*4] */
556 MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) );
558 case 2: /* 0010nnnnmmmmxxxx */
559 switch( ir&0x000F ) {
560 case 0: /* MOV.B Rm, [Rn] */
561 MEM_WRITE_BYTE( RN(ir), RM(ir) );
563 case 1: /* MOV.W Rm, [Rn] */
564 MEM_WRITE_WORD( RN(ir), RM(ir) );
566 case 2: /* MOV.L Rm, [Rn] */
567 MEM_WRITE_LONG( RN(ir), RM(ir) );
571 case 4: /* MOV.B Rm, [--Rn] */
573 MEM_WRITE_BYTE( RN(ir), RM(ir) );
575 case 5: /* MOV.W Rm, [--Rn] */
577 MEM_WRITE_WORD( RN(ir), RM(ir) );
579 case 6: /* MOV.L Rm, [--Rn] */
581 MEM_WRITE_LONG( RN(ir), RM(ir) );
583 case 7: /* DIV0S Rm, Rn */
586 sh4r.t = sh4r.q ^ sh4r.m;
588 case 8: /* TST Rm, Rn */
589 sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
591 case 9: /* AND Rm, Rn */
594 case 10:/* XOR Rm, Rn */
597 case 11:/* OR Rm, Rn */
600 case 12:/* CMP/STR Rm, Rn */
601 /* set T = 1 if any byte in RM & RN is the same */
602 tmp = RM(ir) ^ RN(ir);
603 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
604 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
606 case 13:/* XTRCT Rm, Rn */
607 RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
609 case 14:/* MULU.W Rm, Rn */
610 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
611 (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
613 case 15:/* MULS.W Rm, Rn */
614 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
615 (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
619 case 3: /* 0011nnnnmmmmxxxx */
620 switch( ir&0x000F ) {
621 case 0: /* CMP/EQ Rm, Rn */
622 sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
624 case 2: /* CMP/HS Rm, Rn */
625 sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
627 case 3: /* CMP/GE Rm, Rn */
628 sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
630 case 4: { /* DIV1 Rm, Rn */
631 /* This is just from the sh4p manual with some
632 * simplifications (someone want to check it's correct? :)
633 * Why they couldn't just provide a real DIV instruction...
634 * Please oh please let the translator batch these things
635 * up into a single DIV... */
636 uint32_t tmp0, tmp1, tmp2, dir;
638 dir = sh4r.q ^ sh4r.m;
639 sh4r.q = (RN(ir) >> 31);
641 RN(ir) = (RN(ir) << 1) | sh4r.t;
645 tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
648 tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
650 sh4r.q ^= sh4r.m ^ tmp1;
651 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
653 case 5: /* DMULU.L Rm, Rn */
654 sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
656 case 6: /* CMP/HI Rm, Rn */
657 sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
659 case 7: /* CMP/GT Rm, Rn */
660 sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
662 case 8: /* SUB Rm, Rn */
665 case 10:/* SUBC Rm, Rn */
667 RN(ir) = RN(ir) - RM(ir) - sh4r.t;
668 sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
670 case 11:/* SUBV Rm, Rn */
673 case 12:/* ADD Rm, Rn */
676 case 13:/* DMULS.L Rm, Rn */
677 sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
679 case 14:/* ADDC Rm, Rn */
681 RN(ir) += RM(ir) + sh4r.t;
682 sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
684 case 15:/* ADDV Rm, Rn */
690 case 4: /* 0100nnnnxxxxxxxx */
691 switch( ir&0x00FF ) {
692 case 0x00: /* SHLL Rn */
693 sh4r.t = RN(ir) >> 31;
696 case 0x01: /* SHLR Rn */
697 sh4r.t = RN(ir) & 0x00000001;
700 case 0x02: /* STS.L MACH, [--Rn] */
702 MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
704 case 0x03: /* STC.L SR, [--Rn] */
707 MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
709 case 0x04: /* ROTL Rn */
710 sh4r.t = RN(ir) >> 31;
714 case 0x05: /* ROTR Rn */
715 sh4r.t = RN(ir) & 0x00000001;
717 RN(ir) |= (sh4r.t << 31);
719 case 0x06: /* LDS.L [Rn++], MACH */
720 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
721 (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
724 case 0x07: /* LDC.L [Rn++], SR */
726 sh4_load_sr( MEM_READ_LONG(RN(ir)) );
729 case 0x08: /* SHLL2 Rn */
732 case 0x09: /* SHLR2 Rn */
735 case 0x0A: /* LDS Rn, MACH */
736 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
737 (((uint64_t)RN(ir))<<32);
739 case 0x0B: /* JSR [Rn] */
742 sh4r.in_delay_slot = 1;
743 sh4r.pc = sh4r.new_pc;
744 sh4r.new_pc = RN(ir);
747 case 0x0E: /* LDC Rn, SR */
749 sh4_load_sr( RN(ir) );
751 case 0x10: /* DT Rn */
753 sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
755 case 0x11: /* CMP/PZ Rn */
756 sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
758 case 0x12: /* STS.L MACL, [--Rn] */
760 MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
762 case 0x13: /* STC.L GBR, [--Rn] */
764 MEM_WRITE_LONG( RN(ir), sh4r.gbr );
766 case 0x15: /* CMP/PL Rn */
767 sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
769 case 0x16: /* LDS.L [Rn++], MACL */
770 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
771 (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
774 case 0x17: /* LDC.L [Rn++], GBR */
775 sh4r.gbr = MEM_READ_LONG(RN(ir));
778 case 0x18: /* SHLL8 Rn */
781 case 0x19: /* SHLR8 Rn */
784 case 0x1A: /* LDS Rn, MACL */
785 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
786 (uint64_t)((uint32_t)(RN(ir)));
788 case 0x1B: /* TAS.B [Rn] */
789 tmp = MEM_READ_BYTE( RN(ir) );
790 sh4r.t = ( tmp == 0 ? 1 : 0 );
791 MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
793 case 0x1E: /* LDC Rn, GBR */
796 case 0x20: /* SHAL Rn */
797 sh4r.t = RN(ir) >> 31;
800 case 0x21: /* SHAR Rn */
801 sh4r.t = RN(ir) & 0x00000001;
802 RN(ir) = ((int32_t)RN(ir)) >> 1;
804 case 0x22: /* STS.L PR, [--Rn] */
806 MEM_WRITE_LONG( RN(ir), sh4r.pr );
808 case 0x23: /* STC.L VBR, [--Rn] */
811 MEM_WRITE_LONG( RN(ir), sh4r.vbr );
813 case 0x24: /* ROTCL Rn */
819 case 0x25: /* ROTCR Rn */
820 tmp = RN(ir) & 0x00000001;
822 RN(ir) |= (sh4r.t << 31 );
825 case 0x26: /* LDS.L [Rn++], PR */
826 sh4r.pr = MEM_READ_LONG( RN(ir) );
829 case 0x27: /* LDC.L [Rn++], VBR */
831 sh4r.vbr = MEM_READ_LONG(RN(ir));
834 case 0x28: /* SHLL16 Rn */
837 case 0x29: /* SHLR16 Rn */
840 case 0x2A: /* LDS Rn, PR */
843 case 0x2B: /* JMP [Rn] */
846 sh4r.in_delay_slot = 1;
847 sh4r.pc = sh4r.new_pc;
848 sh4r.new_pc = RN(ir);
850 case 0x2E: /* LDC Rn, VBR */
854 case 0x32: /* STC.L SGR, [--Rn] */
857 MEM_WRITE_LONG( RN(ir), sh4r.sgr );
859 case 0x33: /* STC.L SSR, [--Rn] */
862 MEM_WRITE_LONG( RN(ir), sh4r.ssr );
864 case 0x37: /* LDC.L [Rn++], SSR */
866 sh4r.ssr = MEM_READ_LONG(RN(ir));
869 case 0x3E: /* LDC Rn, SSR */
873 case 0x43: /* STC.L SPC, [--Rn] */
876 MEM_WRITE_LONG( RN(ir), sh4r.spc );
878 case 0x47: /* LDC.L [Rn++], SPC */
880 sh4r.spc = MEM_READ_LONG(RN(ir));
883 case 0x4E: /* LDC Rn, SPC */
887 case 0x52: /* STS.L FPUL, [--Rn] */
889 MEM_WRITE_LONG( RN(ir), sh4r.fpul );
891 case 0x56: /* LDS.L [Rn++], FPUL */
892 sh4r.fpul = MEM_READ_LONG(RN(ir));
895 case 0x5A: /* LDS Rn, FPUL */
898 case 0x62: /* STS.L FPSCR, [--Rn] */
900 MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
902 case 0x66: /* LDS.L [Rn++], FPSCR */
903 sh4r.fpscr = MEM_READ_LONG(RN(ir));
906 case 0x6A: /* LDS Rn, FPSCR */
909 case 0xF2: /* STC.L DBR, [--Rn] */
912 MEM_WRITE_LONG( RN(ir), sh4r.dbr );
914 case 0xF6: /* LDC.L [Rn++], DBR */
916 sh4r.dbr = MEM_READ_LONG(RN(ir));
919 case 0xFA: /* LDC Rn, DBR */
923 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
924 case 0xD3: case 0xE3: case 0xF3: /* STC.L Rn_BANK, [--Rn] */
927 MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
929 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
930 case 0xD7: case 0xE7: case 0xF7: /* LDC.L [Rn++], Rn_BANK */
932 RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
935 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
936 case 0xDE: case 0xEE: case 0xFE: /* LDC Rm, Rn_BANK */
938 RN_BANK(ir) = RM(ir);
941 if( (ir&0x000F) == 0x0F ) {
942 /* MAC.W [Rm++], [Rn++] */
943 tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
944 SIGNEXT16(MEM_READ_WORD(RN(ir)));
948 } else sh4r.mac += SIGNEXT32(tmp);
951 } else if( (ir&0x000F) == 0x0C ) {
954 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
955 else if( (tmp & 0x1F) == 0 )
956 RN(ir) = ((int32_t)RN(ir)) >> 31;
958 RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
959 } else if( (ir&0x000F) == 0x0D ) {
962 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
963 else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
964 else RN(ir) >>= (((~tmp) & 0x1F)+1);
968 case 5: /* 0101nnnnmmmmdddd */
969 /* MOV.L [Rm + disp4*4], Rn */
970 RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) );
972 case 6: /* 0110xxxxxxxxxxxx */
973 switch( ir&0x000f ) {
974 case 0: /* MOV.B [Rm], Rn */
975 RN(ir) = MEM_READ_BYTE( RM(ir) );
977 case 1: /* MOV.W [Rm], Rn */
978 RN(ir) = MEM_READ_WORD( RM(ir) );
980 case 2: /* MOV.L [Rm], Rn */
981 RN(ir) = MEM_READ_LONG( RM(ir) );
983 case 3: /* MOV Rm, Rn */
986 case 4: /* MOV.B [Rm++], Rn */
987 RN(ir) = MEM_READ_BYTE( RM(ir) );
990 case 5: /* MOV.W [Rm++], Rn */
991 RN(ir) = MEM_READ_WORD( RM(ir) );
994 case 6: /* MOV.L [Rm++], Rn */
995 RN(ir) = MEM_READ_LONG( RM(ir) );
998 case 7: /* NOT Rm, Rn */
1001 case 8: /* SWAP.B Rm, Rn */
1002 RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
1003 ((RM(ir)&0x000000FF)<<8);
1005 case 9: /* SWAP.W Rm, Rn */
1006 RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
1008 case 10:/* NEGC Rm, Rn */
1010 RN(ir) = tmp - sh4r.t;
1011 sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
1013 case 11:/* NEG Rm, Rn */
1014 RN(ir) = 0 - RM(ir);
1016 case 12:/* EXTU.B Rm, Rn */
1017 RN(ir) = RM(ir)&0x000000FF;
1019 case 13:/* EXTU.W Rm, Rn */
1020 RN(ir) = RM(ir)&0x0000FFFF;
1022 case 14:/* EXTS.B Rm, Rn */
1023 RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
1025 case 15:/* EXTS.W Rm, Rn */
1026 RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
1030 case 7: /* 0111nnnniiiiiiii */
1034 case 8: /* 1000xxxxxxxxxxxx */
1035 switch( (ir&0x0F00) >> 8 ) {
1036 case 0: /* MOV.B R0, [Rm + disp4] */
1037 MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
1039 case 1: /* MOV.W R0, [Rm + disp4*2] */
1040 MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 );
1042 case 4: /* MOV.B [Rm + disp4], R0 */
1043 R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
1045 case 5: /* MOV.W [Rm + disp4*2], R0 */
1046 R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) );
1048 case 8: /* CMP/EQ imm, R0 */
1049 sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
1051 case 9: /* BT disp8 */
1054 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1055 sh4r.pc += (PCDISP8(ir)<<1) + 4;
1056 sh4r.new_pc = sh4r.pc + 2;
1060 case 11:/* BF disp8 */
1063 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1064 sh4r.pc += (PCDISP8(ir)<<1) + 4;
1065 sh4r.new_pc = sh4r.pc + 2;
1069 case 13:/* BT/S disp8 */
1072 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1073 sh4r.in_delay_slot = 1;
1074 sh4r.pc = sh4r.new_pc;
1075 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1076 sh4r.in_delay_slot = 1;
1080 case 15:/* BF/S disp8 */
1083 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1084 sh4r.in_delay_slot = 1;
1085 sh4r.pc = sh4r.new_pc;
1086 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1093 case 9: /* 1001xxxxxxxxxxxx */
1094 /* MOV.W [disp8*2 + pc + 4], Rn */
1095 RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) );
1097 case 10:/* 1010dddddddddddd */
1099 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
1101 sh4r.in_delay_slot = 1;
1102 sh4r.pc = sh4r.new_pc;
1103 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1105 case 11:/* 1011dddddddddddd */
1107 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
1109 sh4r.in_delay_slot = 1;
1111 sh4r.pc = sh4r.new_pc;
1112 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1114 case 12:/* 1100xxxxdddddddd */
1115 switch( (ir&0x0F00)>>8 ) {
1116 case 0: /* MOV.B R0, [GBR + disp8] */
1117 MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
1119 case 1: /* MOV.W R0, [GBR + disp8*2] */
1120 MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 );
1122 case 2: /*MOV.L R0, [GBR + disp8*4] */
1123 MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 );
1125 case 3: /* TRAPA imm8 */
1127 sh4r.in_delay_slot = 1;
1128 MMIO_WRITE( MMU, TRA, UIMM8(ir)<<2 );
1129 RAISE( EXC_TRAP, EXV_TRAP );
1131 case 4: /* MOV.B [GBR + disp8], R0 */
1132 R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
1134 case 5: /* MOV.W [GBR + disp8*2], R0 */
1135 R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) );
1137 case 6: /* MOV.L [GBR + disp8*4], R0 */
1138 R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) );
1140 case 7: /* MOVA disp8 + pc&~3 + 4, R0 */
1141 R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
1143 case 8: /* TST imm8, R0 */
1144 sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
1146 case 9: /* AND imm8, R0 */
1149 case 10:/* XOR imm8, R0 */
1152 case 11:/* OR imm8, R0 */
1155 case 12:/* TST.B imm8, [R0+GBR] */
1156 sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
1158 case 13:/* AND.B imm8, [R0+GBR] */
1159 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1160 UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
1162 case 14:/* XOR.B imm8, [R0+GBR] */
1163 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1164 UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
1166 case 15:/* OR.B imm8, [R0+GBR] */
1167 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1168 UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
1172 case 13:/* 1101nnnndddddddd */
1173 /* MOV.L [disp8*4 + pc&~3 + 4], Rn */
1174 RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 );
1176 case 14:/* 1110nnnniiiiiiii */
1180 case 15:/* 1111xxxxxxxxxxxx */
1182 if( IS_FPU_DOUBLEPREC() ) {
1183 switch( ir&0x000F ) {
1184 case 0: /* FADD FRm, FRn */
1187 case 1: /* FSUB FRm, FRn */
1190 case 2: /* FMUL FRm, FRn */
1191 DRN(ir) = DRN(ir) * DRM(ir);
1193 case 3: /* FDIV FRm, FRn */
1194 DRN(ir) = DRN(ir) / DRM(ir);
1196 case 4: /* FCMP/EQ FRm, FRn */
1197 sh4r.t = ( DRN(ir) == DRM(ir) ? 1 : 0 );
1199 case 5: /* FCMP/GT FRm, FRn */
1200 sh4r.t = ( DRN(ir) > DRM(ir) ? 1 : 0 );
1202 case 6: /* FMOV.S [Rm+R0], FRn */
1203 MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
1205 case 7: /* FMOV.S FRm, [Rn+R0] */
1206 MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
1208 case 8: /* FMOV.S [Rm], FRn */
1209 MEM_FP_READ( RM(ir), FRNn(ir) );
1211 case 9: /* FMOV.S [Rm++], FRn */
1212 MEM_FP_READ( RM(ir), FRNn(ir) );
1215 case 10:/* FMOV.S FRm, [Rn] */
1216 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1218 case 11:/* FMOV.S FRm, [--Rn] */
1220 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1222 case 12:/* FMOV FRm, FRn */
1223 if( IS_FPU_DOUBLESIZE() )
1229 switch( (ir&0x00F0) >> 4 ) {
1230 case 0: /* FSTS FPUL, FRn */
1233 case 1: /* FLDS FRn,FPUL */
1236 case 2: /* FLOAT FPUL, FRn */
1237 DRN(ir) = (float)FPULi;
1239 case 3: /* FTRC FRn, FPUL */
1241 if( dtmp >= MAX_INTF )
1243 else if( dtmp <= MIN_INTF )
1246 FPULi = (int32_t)dtmp;
1248 case 4: /* FNEG FRn */
1251 case 5: /* FABS FRn */
1252 DRN(ir) = fabs(DRN(ir));
1254 case 6: /* FSQRT FRn */
1255 DRN(ir) = sqrt(DRN(ir));
1257 case 7: /* FSRRA FRn */
1258 DRN(ir) = 1.0/sqrt(DRN(ir));
1260 case 8: /* FLDI0 FRn */
1263 case 9: /* FLDI1 FRn */
1266 case 10: /* FCNVSD FPUL, DRn */
1267 DRN(ir) = (double)FPULf;
1269 case 11: /* FCNVDS DRn, FPUL */
1270 FPULf = (float)DRN(ir);
1272 case 14:/* FIPR FVm, FVn */
1276 if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
1279 else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
1280 float angle = (((float)(short)(FPULi>>16)) +
1281 ((float)(FPULi&16)/65536.0)) *
1284 DR(reg) = sinf(angle);
1285 DR(reg+1) = cosf(angle);
1288 else if( ir == 0xFBFD ) {
1290 sh4r.fpscr ^= FPSCR_FR;
1293 else if( ir == 0xF3FD ) {
1295 sh4r.fpscr ^= FPSCR_SZ;
1301 case 14:/* FMAC FR0, FRm, FRn */
1302 DRN(ir) += DRM(ir)*DR0;
1306 } else { /* Single precision */
1307 switch( ir&0x000F ) {
1308 case 0: /* FADD FRm, FRn */
1311 case 1: /* FSUB FRm, FRn */
1314 case 2: /* FMUL FRm, FRn */
1315 FRN(ir) = FRN(ir) * FRM(ir);
1317 case 3: /* FDIV FRm, FRn */
1318 FRN(ir) = FRN(ir) / FRM(ir);
1320 case 4: /* FCMP/EQ FRm, FRn */
1321 sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
1323 case 5: /* FCMP/GT FRm, FRn */
1324 sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
1326 case 6: /* FMOV.S [Rm+R0], FRn */
1327 MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
1329 case 7: /* FMOV.S FRm, [Rn+R0] */
1330 MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
1332 case 8: /* FMOV.S [Rm], FRn */
1333 MEM_FP_READ( RM(ir), FRNn(ir) );
1335 case 9: /* FMOV.S [Rm++], FRn */
1336 MEM_FP_READ( RM(ir), FRNn(ir) );
1339 case 10:/* FMOV.S FRm, [Rn] */
1340 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1342 case 11:/* FMOV.S FRm, [--Rn] */
1344 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1346 case 12:/* FMOV FRm, FRn */
1347 if( IS_FPU_DOUBLESIZE() )
1353 switch( (ir&0x00F0) >> 4 ) {
1354 case 0: /* FSTS FPUL, FRn */
1357 case 1: /* FLDS FRn,FPUL */
1360 case 2: /* FLOAT FPUL, FRn */
1361 FRN(ir) = (float)FPULi;
1363 case 3: /* FTRC FRn, FPUL */
1365 if( ftmp >= MAX_INTF )
1367 else if( ftmp <= MIN_INTF )
1370 FPULi = (int32_t)ftmp;
1372 case 4: /* FNEG FRn */
1375 case 5: /* FABS FRn */
1376 FRN(ir) = fabsf(FRN(ir));
1378 case 6: /* FSQRT FRn */
1379 FRN(ir) = sqrtf(FRN(ir));
1381 case 7: /* FSRRA FRn */
1382 FRN(ir) = 1.0/sqrtf(FRN(ir));
1384 case 8: /* FLDI0 FRn */
1387 case 9: /* FLDI1 FRn */
1390 case 10: /* FCNVSD FPUL, DRn */
1393 case 11: /* FCNVDS DRn, FPUL */
1396 case 14:/* FIPR FVm, FVn */
1397 /* FIXME: This is not going to be entirely accurate
1398 * as the SH4 instruction is less precise. Also
1399 * need to check for 0s and infinities.
1404 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
1405 FR(tmp+1)*FR(tmp2+1) +
1406 FR(tmp+2)*FR(tmp2+2) +
1407 FR(tmp+3)*FR(tmp2+3);
1411 if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
1413 float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
1414 FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
1415 XF(8)*fv[2] + XF(12)*fv[3];
1416 FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
1417 XF(9)*fv[2] + XF(13)*fv[3];
1418 FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
1419 XF(10)*fv[2] + XF(14)*fv[3];
1420 FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
1421 XF(11)*fv[2] + XF(15)*fv[3];
1424 else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
1425 float angle = (((float)(short)(FPULi>>16)) +
1426 (((float)(FPULi&0xFFFF))/65536.0)) *
1429 FR(reg) = sinf(angle);
1430 FR(reg+1) = cosf(angle);
1433 else if( ir == 0xFBFD ) {
1435 sh4r.fpscr ^= FPSCR_FR;
1438 else if( ir == 0xF3FD ) {
1440 sh4r.fpscr ^= FPSCR_SZ;
1446 case 14:/* FMAC FR0, FRm, FRn */
1447 FRN(ir) += FRM(ir)*FR0;
1454 sh4r.pc = sh4r.new_pc;
1456 sh4r.in_delay_slot = 0;
.