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lxdream.org :: lxdream/src/sh4/sh4core.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.c
changeset 312:2c34bdc36cbd
prev302:96b5cc24309c
next359:c588dce7ebde
author nkeynes
date Tue Jan 23 08:17:06 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Save/restore MMU state (specifically the OC cache ram) correctly
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     1 /**
     2  * $Id: sh4core.c,v 1.40 2007-01-23 08:17:06 nkeynes Exp $
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "sh4/sh4core.h"
    24 #include "sh4/sh4mmio.h"
    25 #include "sh4/intc.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "syscall.h"
    30 #define SH4_CALLTRACE 1
    32 #define MAX_INT 0x7FFFFFFF
    33 #define MIN_INT 0x80000000
    34 #define MAX_INTF 2147483647.0
    35 #define MIN_INTF -2147483648.0
    37 /* CPU-generated exception code/vector pairs */
    38 #define EXC_POWER_RESET  0x000 /* vector special */
    39 #define EXC_MANUAL_RESET 0x020
    40 #define EXC_READ_ADDR_ERR 0x0E0
    41 #define EXC_WRITE_ADDR_ERR 0x100
    42 #define EXC_SLOT_ILLEGAL 0x1A0
    43 #define EXC_ILLEGAL      0x180
    44 #define EXC_TRAP         0x160
    45 #define EXC_FPDISABLE    0x800
    46 #define EXC_SLOT_FPDISABLE 0x820
    48 #define EXV_EXCEPTION    0x100  /* General exception vector */
    49 #define EXV_TLBMISS      0x400  /* TLB-miss exception vector */
    50 #define EXV_INTERRUPT    0x600  /* External interrupt vector */
    52 /********************** SH4 Module Definition ****************************/
    54 void sh4_init( void );
    55 void sh4_reset( void );
    56 uint32_t sh4_run_slice( uint32_t );
    57 void sh4_start( void );
    58 void sh4_stop( void );
    59 void sh4_save_state( FILE *f );
    60 int sh4_load_state( FILE *f );
    61 static void sh4_accept_interrupt( void );
    63 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    64 				       NULL, sh4_run_slice, sh4_stop,
    65 				       sh4_save_state, sh4_load_state };
    67 struct sh4_registers sh4r;
    69 void sh4_init(void)
    70 {
    71     register_io_regions( mmio_list_sh4mmio );
    72     MMU_init();
    73     sh4_reset();
    74 }
    76 void sh4_reset(void)
    77 {
    78     /* zero everything out, for the sake of having a consistent state. */
    79     memset( &sh4r, 0, sizeof(sh4r) );
    81     /* Resume running if we were halted */
    82     sh4r.sh4_state = SH4_STATE_RUNNING;
    84     sh4r.pc    = 0xA0000000;
    85     sh4r.new_pc= 0xA0000002;
    86     sh4r.vbr   = 0x00000000;
    87     sh4r.fpscr = 0x00040001;
    88     sh4r.sr    = 0x700000F0;
    90     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
    91     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
    93     /* Peripheral modules */
    94     CPG_reset();
    95     INTC_reset();
    96     MMU_reset();
    97     TMU_reset();
    98     SCIF_reset();
    99 }
   101 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
   102 static int sh4_breakpoint_count = 0;
   103 static uint16_t *sh4_icache = NULL;
   104 static uint32_t sh4_icache_addr = 0;
   106 void sh4_set_breakpoint( uint32_t pc, int type )
   107 {
   108     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   109     sh4_breakpoints[sh4_breakpoint_count].type = type;
   110     sh4_breakpoint_count++;
   111 }
   113 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
   114 {
   115     int i;
   117     for( i=0; i<sh4_breakpoint_count; i++ ) {
   118 	if( sh4_breakpoints[i].address == pc && 
   119 	    sh4_breakpoints[i].type == type ) {
   120 	    while( ++i < sh4_breakpoint_count ) {
   121 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   122 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   123 	    }
   124 	    sh4_breakpoint_count--;
   125 	    return TRUE;
   126 	}
   127     }
   128     return FALSE;
   129 }
   131 int sh4_get_breakpoint( uint32_t pc )
   132 {
   133     int i;
   134     for( i=0; i<sh4_breakpoint_count; i++ ) {
   135 	if( sh4_breakpoints[i].address == pc )
   136 	    return sh4_breakpoints[i].type;
   137     }
   138     return 0;
   139 }
   141 uint32_t sh4_run_slice( uint32_t nanosecs ) 
   142 {
   143     int i;
   144     sh4r.slice_cycle = 0;
   146     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
   147 	if( sh4r.event_pending < nanosecs ) {
   148 	    sh4r.sh4_state = SH4_STATE_RUNNING;
   149 	    sh4r.slice_cycle = sh4r.event_pending;
   150 	}
   151     }
   153     if( sh4_breakpoint_count == 0 ) {
   154 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
   155 	    if( SH4_EVENT_PENDING() ) {
   156 		if( sh4r.event_types & PENDING_EVENT ) {
   157 		    event_execute();
   158 		}
   159 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
   160 		if( sh4r.event_types & PENDING_IRQ ) {
   161 		    sh4_accept_interrupt();
   162 		}
   163 	    }
   164 	    if( !sh4_execute_instruction() ) {
   165 		break;
   166 	    }
   167 	}
   168     } else {
   169 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
   170 	    if( SH4_EVENT_PENDING() ) {
   171 		if( sh4r.event_types & PENDING_EVENT ) {
   172 		    event_execute();
   173 		}
   174 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
   175 		if( sh4r.event_types & PENDING_IRQ ) {
   176 		    sh4_accept_interrupt();
   177 		}
   178 	    }
   180 	    if( !sh4_execute_instruction() )
   181 		break;
   182 #ifdef ENABLE_DEBUG_MODE
   183 	    for( i=0; i<sh4_breakpoint_count; i++ ) {
   184 		if( sh4_breakpoints[i].address == sh4r.pc ) {
   185 		    break;
   186 		}
   187 	    }
   188 	    if( i != sh4_breakpoint_count ) {
   189 		dreamcast_stop();
   190 		if( sh4_breakpoints[i].type == BREAK_ONESHOT )
   191 		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
   192 		break;
   193 	    }
   194 #endif	
   195 	}
   196     }
   198     /* If we aborted early, but the cpu is still technically running,
   199      * we're doing a hard abort - cut the timeslice back to what we
   200      * actually executed
   201      */
   202     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   203 	nanosecs = sh4r.slice_cycle;
   204     }
   205     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   206 	TMU_run_slice( nanosecs );
   207 	SCIF_run_slice( nanosecs );
   208     }
   209     return nanosecs;
   210 }
   212 void sh4_stop(void)
   213 {
   215 }
   217 void sh4_save_state( FILE *f )
   218 {
   219     fwrite( &sh4r, sizeof(sh4r), 1, f );
   220     MMU_save_state( f );
   221     INTC_save_state( f );
   222     TMU_save_state( f );
   223     SCIF_save_state( f );
   224 }
   226 int sh4_load_state( FILE * f )
   227 {
   228     fread( &sh4r, sizeof(sh4r), 1, f );
   229     MMU_load_state( f );
   230     INTC_load_state( f );
   231     TMU_load_state( f );
   232     return SCIF_load_state( f );
   233 }
   235 /********************** SH4 emulation core  ****************************/
   237 void sh4_set_pc( int pc )
   238 {
   239     sh4r.pc = pc;
   240     sh4r.new_pc = pc+2;
   241 }
   243 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
   244 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
   246 #if(SH4_CALLTRACE == 1)
   247 #define MAX_CALLSTACK 32
   248 static struct call_stack {
   249     sh4addr_t call_addr;
   250     sh4addr_t target_addr;
   251     sh4addr_t stack_pointer;
   252 } call_stack[MAX_CALLSTACK];
   254 static int call_stack_depth = 0;
   255 int sh4_call_trace_on = 0;
   257 static inline trace_call( sh4addr_t source, sh4addr_t dest ) 
   258 {
   259     if( call_stack_depth < MAX_CALLSTACK ) {
   260 	call_stack[call_stack_depth].call_addr = source;
   261 	call_stack[call_stack_depth].target_addr = dest;
   262 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   263     }
   264     call_stack_depth++;
   265 }
   267 static inline trace_return( sh4addr_t source, sh4addr_t dest )
   268 {
   269     if( call_stack_depth > 0 ) {
   270 	call_stack_depth--;
   271     }
   272 }
   274 void fprint_stack_trace( FILE *f )
   275 {
   276     int i = call_stack_depth -1;
   277     if( i >= MAX_CALLSTACK )
   278 	i = MAX_CALLSTACK - 1;
   279     for( ; i >= 0; i-- ) {
   280 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   281 		 (call_stack_depth - i), call_stack[i].call_addr,
   282 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   283     }
   284 }
   286 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   287 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   288 #else
   289 #define TRACE_CALL( dest, rts ) 
   290 #define TRACE_RETURN( source, dest )
   291 #endif
   293 #define RAISE( x, v ) do{			\
   294     if( sh4r.vbr == 0 ) { \
   295         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   296         dreamcast_stop(); return FALSE;	\
   297     } else { \
   298         sh4r.spc = sh4r.pc;	\
   299         sh4r.ssr = sh4_read_sr(); \
   300         sh4r.sgr = sh4r.r[15]; \
   301         MMIO_WRITE(MMU,EXPEVT,x); \
   302         sh4r.pc = sh4r.vbr + v; \
   303         sh4r.new_pc = sh4r.pc + 2; \
   304         sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   305 	if( sh4r.in_delay_slot ) { \
   306 	    sh4r.in_delay_slot = 0; \
   307 	    sh4r.spc -= 2; \
   308 	} \
   309     } \
   310     return TRUE; } while(0)
   312 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
   313 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
   314 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
   315 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
   316 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
   317 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
   319 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   321 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
   322 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
   324 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
   325 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_READ_ADDR_ERR )
   326 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_READ_ADDR_ERR )
   327 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_WRITE_ADDR_ERR )
   328 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_WRITE_ADDR_ERR )
   330 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) return sh4_raise_slot_exception( EXC_FPDISABLE, EXC_SLOT_FPDISABLE )
   331 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
   332 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
   334 static void sh4_switch_banks( )
   335 {
   336     uint32_t tmp[8];
   338     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   339     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   340     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   341 }
   343 static void sh4_load_sr( uint32_t newval )
   344 {
   345     if( (newval ^ sh4r.sr) & SR_RB )
   346         sh4_switch_banks();
   347     sh4r.sr = newval;
   348     sh4r.t = (newval&SR_T) ? 1 : 0;
   349     sh4r.s = (newval&SR_S) ? 1 : 0;
   350     sh4r.m = (newval&SR_M) ? 1 : 0;
   351     sh4r.q = (newval&SR_Q) ? 1 : 0;
   352     intc_mask_changed();
   353 }
   355 static void sh4_write_float( uint32_t addr, int reg )
   356 {
   357     if( IS_FPU_DOUBLESIZE() ) {
   358 	if( reg & 1 ) {
   359 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
   360 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
   361 	} else {
   362 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 
   363 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
   364 	}
   365     } else {
   366 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
   367     }
   368 }
   370 static void sh4_read_float( uint32_t addr, int reg )
   371 {
   372     if( IS_FPU_DOUBLESIZE() ) {
   373 	if( reg & 1 ) {
   374 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
   375 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
   376 	} else {
   377 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   378 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
   379 	}
   380     } else {
   381 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   382     }
   383 }
   385 static uint32_t sh4_read_sr( void )
   386 {
   387     /* synchronize sh4r.sr with the various bitflags */
   388     sh4r.sr &= SR_MQSTMASK;
   389     if( sh4r.t ) sh4r.sr |= SR_T;
   390     if( sh4r.s ) sh4r.sr |= SR_S;
   391     if( sh4r.m ) sh4r.sr |= SR_M;
   392     if( sh4r.q ) sh4r.sr |= SR_Q;
   393     return sh4r.sr;
   394 }
   396 /**
   397  * Raise a general CPU exception for the specified exception code.
   398  * (NOT for TRAPA or TLB exceptions)
   399  */
   400 gboolean sh4_raise_exception( int code )
   401 {
   402     RAISE( code, EXV_EXCEPTION );
   403 }
   405 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
   406     if( sh4r.in_delay_slot ) {
   407 	return sh4_raise_exception(slot_code);
   408     } else {
   409 	return sh4_raise_exception(normal_code);
   410     }
   411 }
   413 gboolean sh4_raise_tlb_exception( int code )
   414 {
   415     RAISE( code, EXV_TLBMISS );
   416 }
   418 static void sh4_accept_interrupt( void )
   419 {
   420     uint32_t code = intc_accept_interrupt();
   421     sh4r.ssr = sh4_read_sr();
   422     sh4r.spc = sh4r.pc;
   423     sh4r.sgr = sh4r.r[15];
   424     sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   425     MMIO_WRITE( MMU, INTEVT, code );
   426     sh4r.pc = sh4r.vbr + 0x600;
   427     sh4r.new_pc = sh4r.pc + 2;
   428     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   429 }
   431 gboolean sh4_execute_instruction( void )
   432 {
   433     uint32_t pc;
   434     unsigned short ir;
   435     uint32_t tmp;
   436     uint64_t tmpl;
   437     float ftmp;
   438     double dtmp;
   440 #define R0 sh4r.r[0]
   441 #define FR0 FR(0)
   442 #define DR0 DR(0)
   443 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
   444 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
   445 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
   446 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
   447 #define DISP8(ir) (ir&0x00FF)
   448 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
   449 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
   450 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
   451 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
   452 #define FRNn(ir) ((ir&0x0F00)>>8)
   453 #define FRMn(ir) ((ir&0x00F0)>>4)
   454 #define DRNn(ir) ((ir&0x0E00)>>9)
   455 #define DRMn(ir) ((ir&0x00E0)>>5)
   456 #define FVN(ir) ((ir&0x0C00)>>8)
   457 #define FVM(ir) ((ir&0x0300)>>6)
   458 #define FRN(ir) FR(FRNn(ir))
   459 #define FRM(ir) FR(FRMn(ir))
   460 #define FRNi(ir) (*((uint32_t *)&FR(FRNn(ir))))
   461 #define FRMi(ir) (*((uint32_t *)&FR(FRMn(ir))))
   462 #define DRN(ir) DRb(DRNn(ir), ir&0x0100)
   463 #define DRM(ir) DRb(DRMn(ir),ir&0x0010)
   464 #define DRNi(ir) (*((uint64_t *)&DR(FRNn(ir))))
   465 #define DRMi(ir) (*((uint64_t *)&DR(FRMn(ir))))
   466 #define FPULf   *((float *)&sh4r.fpul)
   467 #define FPULi    (sh4r.fpul)
   469     pc = sh4r.pc;
   470     if( pc > 0xFFFFFF00 ) {
   471 	/* SYSCALL Magic */
   472 	syscall_invoke( pc );
   473 	sh4r.in_delay_slot = 0;
   474 	pc = sh4r.pc = sh4r.pr;
   475 	sh4r.new_pc = sh4r.pc + 2;
   476     }
   477     CHECKRALIGN16(pc);
   479     /* Read instruction */
   480     uint32_t pageaddr = pc >> 12;
   481     if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
   482 	ir = sh4_icache[(pc&0xFFF)>>1];
   483     } else {
   484 	sh4_icache = (uint16_t *)mem_get_page(pc);
   485 	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
   486 	    /* If someone's actually been so daft as to try to execute out of an IO
   487 	     * region, fallback on the full-blown memory read
   488 	     */
   489 	    sh4_icache = NULL;
   490 	    ir = MEM_READ_WORD(pc);
   491 	} else {
   492 	    sh4_icache_addr = pageaddr;
   493 	    ir = sh4_icache[(pc&0xFFF)>>1];
   494 	}
   495     }
   497     switch( (ir&0xF000)>>12 ) {
   498         case 0: /* 0000nnnnmmmmxxxx */
   499             switch( ir&0x000F ) {
   500                 case 2:
   501                     switch( (ir&0x00F0)>>4 ) {
   502                         case 0: /* STC     SR, Rn */
   503                             CHECKPRIV();
   504                             RN(ir) = sh4_read_sr();
   505                             break;
   506                         case 1: /* STC     GBR, Rn */
   507                             RN(ir) = sh4r.gbr;
   508                             break;
   509                         case 2: /* STC     VBR, Rn */
   510                             CHECKPRIV();
   511                             RN(ir) = sh4r.vbr;
   512                             break;
   513                         case 3: /* STC     SSR, Rn */
   514                             CHECKPRIV();
   515                             RN(ir) = sh4r.ssr;
   516                             break;
   517                         case 4: /* STC     SPC, Rn */
   518                             CHECKPRIV();
   519                             RN(ir) = sh4r.spc;
   520                             break;
   521                         case 8: case 9: case 10: case 11: case 12: case 13:
   522                         case 14: case 15:/* STC     Rm_bank, Rn */
   523                             CHECKPRIV();
   524                             RN(ir) = RN_BANK(ir);
   525                             break;
   526                         default: UNDEF(ir);
   527                     }
   528                     break;
   529                 case 3:
   530                     switch( (ir&0x00F0)>>4 ) {
   531                         case 0: /* BSRF    Rn */
   532                             CHECKSLOTILLEGAL();
   533                             CHECKDEST( pc + 4 + RN(ir) );
   534                             sh4r.in_delay_slot = 1;
   535                             sh4r.pr = sh4r.pc + 4;
   536                             sh4r.pc = sh4r.new_pc;
   537                             sh4r.new_pc = pc + 4 + RN(ir);
   538 			    TRACE_CALL( pc, sh4r.new_pc );
   539                             return TRUE;
   540                         case 2: /* BRAF    Rn */
   541                             CHECKSLOTILLEGAL();
   542                             CHECKDEST( pc + 4 + RN(ir) );
   543                             sh4r.in_delay_slot = 1;
   544                             sh4r.pc = sh4r.new_pc;
   545                             sh4r.new_pc = pc + 4 + RN(ir);
   546                             return TRUE;
   547                         case 8: /* PREF    [Rn] */
   548                             tmp = RN(ir);
   549                             if( (tmp & 0xFC000000) == 0xE0000000 ) {
   550                                 /* Store queue operation */
   551                                 int queue = (tmp&0x20)>>2;
   552                                 int32_t *src = &sh4r.store_queue[queue];
   553                                 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
   554                                 uint32_t target = tmp&0x03FFFFE0 | hi;
   555                                 mem_copy_to_sh4( target, src, 32 );
   556                             }
   557                             break;
   558                         case 9: /* OCBI    [Rn] */
   559                         case 10:/* OCBP    [Rn] */
   560                         case 11:/* OCBWB   [Rn] */
   561                             /* anything? */
   562                             break;
   563                         case 12:/* MOVCA.L R0, [Rn] */
   564 			    tmp = RN(ir);
   565 			    CHECKWALIGN32(tmp);
   566 			    MEM_WRITE_LONG( tmp, R0 );
   567 			    break;
   568                         default: UNDEF(ir);
   569                     }
   570                     break;
   571                 case 4: /* MOV.B   Rm, [R0 + Rn] */
   572                     MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
   573                     break;
   574                 case 5: /* MOV.W   Rm, [R0 + Rn] */
   575 		    CHECKWALIGN16( R0 + RN(ir) );
   576                     MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
   577                     break;
   578                 case 6: /* MOV.L   Rm, [R0 + Rn] */
   579 		    CHECKWALIGN32( R0 + RN(ir) );
   580                     MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
   581                     break;
   582                 case 7: /* MUL.L   Rm, Rn */
   583                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   584                         (RM(ir) * RN(ir));
   585                     break;
   586                 case 8: 
   587                     switch( (ir&0x0FF0)>>4 ) {
   588                         case 0: /* CLRT    */
   589                             sh4r.t = 0;
   590                             break;
   591                         case 1: /* SETT    */
   592                             sh4r.t = 1;
   593                             break;
   594                         case 2: /* CLRMAC  */
   595                             sh4r.mac = 0;
   596                             break;
   597                         case 3: /* LDTLB   */
   598                             break;
   599                         case 4: /* CLRS    */
   600                             sh4r.s = 0;
   601                             break;
   602                         case 5: /* SETS    */
   603                             sh4r.s = 1;
   604                             break;
   605                         default: UNDEF(ir);
   606                     }
   607                     break;
   608                 case 9: 
   609                     if( (ir&0x00F0) == 0x20 ) /* MOVT    Rn */
   610                         RN(ir) = sh4r.t;
   611                     else if( ir == 0x0019 ) /* DIV0U   */
   612                         sh4r.m = sh4r.q = sh4r.t = 0;
   613                     else if( ir == 0x0009 )
   614                         /* NOP     */;
   615                     else UNDEF(ir);
   616                     break;
   617                 case 10:
   618                     switch( (ir&0x00F0) >> 4 ) {
   619                         case 0: /* STS     MACH, Rn */
   620                             RN(ir) = sh4r.mac >> 32;
   621                             break;
   622                         case 1: /* STS     MACL, Rn */
   623                             RN(ir) = (uint32_t)sh4r.mac;
   624                             break;
   625                         case 2: /* STS     PR, Rn */
   626                             RN(ir) = sh4r.pr;
   627                             break;
   628                         case 3: /* STC     SGR, Rn */
   629                             CHECKPRIV();
   630                             RN(ir) = sh4r.sgr;
   631                             break;
   632                         case 5:/* STS      FPUL, Rn */
   633                             RN(ir) = sh4r.fpul;
   634                             break;
   635                         case 6: /* STS     FPSCR, Rn */
   636                             RN(ir) = sh4r.fpscr;
   637                             break;
   638                         case 15:/* STC     DBR, Rn */
   639                             CHECKPRIV();
   640                             RN(ir) = sh4r.dbr;
   641                             break;
   642                         default: UNDEF(ir);
   643                     }
   644                     break;
   645                 case 11:
   646                     switch( (ir&0x0FF0)>>4 ) {
   647                         case 0: /* RTS     */
   648                             CHECKSLOTILLEGAL();
   649                             CHECKDEST( sh4r.pr );
   650                             sh4r.in_delay_slot = 1;
   651                             sh4r.pc = sh4r.new_pc;
   652                             sh4r.new_pc = sh4r.pr;
   653                             TRACE_RETURN( pc, sh4r.new_pc );
   654                             return TRUE;
   655                         case 1: /* SLEEP   */
   656 			    if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   657 				sh4r.sh4_state = SH4_STATE_STANDBY;
   658 			    } else {
   659 				sh4r.sh4_state = SH4_STATE_SLEEP;
   660 			    }
   661 			    return FALSE; /* Halt CPU */
   662                         case 2: /* RTE     */
   663                             CHECKPRIV();
   664                             CHECKDEST( sh4r.spc );
   665                             CHECKSLOTILLEGAL();
   666                             sh4r.in_delay_slot = 1;
   667                             sh4r.pc = sh4r.new_pc;
   668                             sh4r.new_pc = sh4r.spc;
   669                             sh4_load_sr( sh4r.ssr );
   670                             return TRUE;
   671                         default:UNDEF(ir);
   672                     }
   673                     break;
   674                 case 12:/* MOV.B   [R0+R%d], R%d */
   675                     RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
   676                     break;
   677                 case 13:/* MOV.W   [R0+R%d], R%d */
   678 		    CHECKRALIGN16( R0 + RM(ir) );
   679                     RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
   680                     break;
   681                 case 14:/* MOV.L   [R0+R%d], R%d */
   682 		    CHECKRALIGN32( R0 + RM(ir) );
   683                     RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
   684                     break;
   685                 case 15:/* MAC.L   [Rm++], [Rn++] */
   686 		    CHECKRALIGN32( RM(ir) );
   687 		    CHECKRALIGN32( RN(ir) );
   688                     tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
   689                                   SIGNEXT32(MEM_READ_LONG(RN(ir))) );
   690                     if( sh4r.s ) {
   691                         /* 48-bit Saturation. Yuch */
   692                         tmpl += SIGNEXT48(sh4r.mac);
   693                         if( tmpl < 0xFFFF800000000000LL )
   694                             tmpl = 0xFFFF800000000000LL;
   695                         else if( tmpl > 0x00007FFFFFFFFFFFLL )
   696                             tmpl = 0x00007FFFFFFFFFFFLL;
   697                         sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
   698                             (tmpl&0x0000FFFFFFFFFFFFLL);
   699                     } else sh4r.mac = tmpl;
   701                     RM(ir) += 4;
   702                     RN(ir) += 4;
   704                     break;
   705                 default: UNDEF(ir);
   706             }
   707             break;
   708         case 1: /* 0001nnnnmmmmdddd */
   709             /* MOV.L   Rm, [Rn + disp4*4] */
   710 	    tmp = RN(ir) + (DISP4(ir)<<2);
   711 	    CHECKWALIGN32( tmp );
   712             MEM_WRITE_LONG( tmp, RM(ir) );
   713             break;
   714         case 2: /* 0010nnnnmmmmxxxx */
   715             switch( ir&0x000F ) {
   716                 case 0: /* MOV.B   Rm, [Rn] */
   717                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   718                     break;
   719                 case 1: /* MOV.W   Rm, [Rn] */
   720                	    CHECKWALIGN16( RN(ir) );
   721 		    MEM_WRITE_WORD( RN(ir), RM(ir) );
   722                     break;
   723                 case 2: /* MOV.L   Rm, [Rn] */
   724 		    CHECKWALIGN32( RN(ir) );
   725                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   726                     break;
   727                 case 3: UNDEF(ir);
   728                     break;
   729                 case 4: /* MOV.B   Rm, [--Rn] */
   730                     RN(ir) --;
   731                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   732                     break;
   733                 case 5: /* MOV.W   Rm, [--Rn] */
   734                     RN(ir) -= 2;
   735 		    CHECKWALIGN16( RN(ir) );
   736                     MEM_WRITE_WORD( RN(ir), RM(ir) );
   737                     break;
   738                 case 6: /* MOV.L   Rm, [--Rn] */
   739                     RN(ir) -= 4;
   740 		    CHECKWALIGN32( RN(ir) );
   741                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   742                     break;
   743                 case 7: /* DIV0S   Rm, Rn */
   744                     sh4r.q = RN(ir)>>31;
   745                     sh4r.m = RM(ir)>>31;
   746                     sh4r.t = sh4r.q ^ sh4r.m;
   747                     break;
   748                 case 8: /* TST     Rm, Rn */
   749                     sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
   750                     break;
   751                 case 9: /* AND     Rm, Rn */
   752                     RN(ir) &= RM(ir);
   753                     break;
   754                 case 10:/* XOR     Rm, Rn */
   755                     RN(ir) ^= RM(ir);
   756                     break;
   757                 case 11:/* OR      Rm, Rn */
   758                     RN(ir) |= RM(ir);
   759                     break;
   760                 case 12:/* CMP/STR Rm, Rn */
   761                     /* set T = 1 if any byte in RM & RN is the same */
   762                     tmp = RM(ir) ^ RN(ir);
   763                     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   764                               (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   765                     break;
   766                 case 13:/* XTRCT   Rm, Rn */
   767                     RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
   768                     break;
   769                 case 14:/* MULU.W  Rm, Rn */
   770                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   771                         (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
   772                     break;
   773                 case 15:/* MULS.W  Rm, Rn */
   774                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   775                         (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
   776                     break;
   777             }
   778             break;
   779         case 3: /* 0011nnnnmmmmxxxx */
   780             switch( ir&0x000F ) {
   781                 case 0: /* CMP/EQ  Rm, Rn */
   782                     sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
   783                     break;
   784                 case 2: /* CMP/HS  Rm, Rn */
   785                     sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
   786                     break;
   787                 case 3: /* CMP/GE  Rm, Rn */
   788                     sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
   789                     break;
   790                 case 4: { /* DIV1    Rm, Rn */
   791                     /* This is just from the sh4p manual with some
   792                      * simplifications (someone want to check it's correct? :)
   793                      * Why they couldn't just provide a real DIV instruction...
   794                      * Please oh please let the translator batch these things
   795                      * up into a single DIV... */
   796                     uint32_t tmp0, tmp1, tmp2, dir;
   798                     dir = sh4r.q ^ sh4r.m;
   799                     sh4r.q = (RN(ir) >> 31);
   800                     tmp2 = RM(ir);
   801                     RN(ir) = (RN(ir) << 1) | sh4r.t;
   802                     tmp0 = RN(ir);
   803                     if( dir ) {
   804                         RN(ir) += tmp2;
   805                         tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
   806                     } else {
   807                         RN(ir) -= tmp2;
   808                         tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
   809                     }
   810                     sh4r.q ^= sh4r.m ^ tmp1;
   811                     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   812                     break; }
   813                 case 5: /* DMULU.L Rm, Rn */
   814                     sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
   815                     break;
   816                 case 6: /* CMP/HI  Rm, Rn */
   817                     sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
   818                     break;
   819                 case 7: /* CMP/GT  Rm, Rn */
   820                     sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
   821                     break;
   822                 case 8: /* SUB     Rm, Rn */
   823                     RN(ir) -= RM(ir);
   824                     break;
   825                 case 10:/* SUBC    Rm, Rn */
   826                     tmp = RN(ir);
   827                     RN(ir) = RN(ir) - RM(ir) - sh4r.t;
   828                     sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
   829                     break;
   830                 case 11:/* SUBV    Rm, Rn */
   831                     UNIMP(ir);
   832                     break;
   833                 case 12:/* ADD     Rm, Rn */
   834                     RN(ir) += RM(ir);
   835                     break;
   836                 case 13:/* DMULS.L Rm, Rn */
   837                     sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
   838                     break;
   839                 case 14:/* ADDC    Rm, Rn */
   840                     tmp = RN(ir);
   841                     RN(ir) += RM(ir) + sh4r.t;
   842                     sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
   843                     break;
   844                 case 15:/* ADDV    Rm, Rn */
   845 		    tmp = RN(ir) + RM(ir);
   846 		    sh4r.t = ( (RN(ir)>>31) == (RM(ir)>>31) && ((RN(ir)>>31) != (tmp>>31)) );
   847 		    RN(ir) = tmp;
   848                     break;
   849                 default: UNDEF(ir);
   850             }
   851             break;
   852         case 4: /* 0100nnnnxxxxxxxx */
   853             switch( ir&0x00FF ) {
   854                 case 0x00: /* SHLL    Rn */
   855                     sh4r.t = RN(ir) >> 31;
   856                     RN(ir) <<= 1;
   857                     break;
   858                 case 0x01: /* SHLR    Rn */
   859                     sh4r.t = RN(ir) & 0x00000001;
   860                     RN(ir) >>= 1;
   861                     break;
   862                 case 0x02: /* STS.L   MACH, [--Rn] */
   863                     RN(ir) -= 4;
   864 		    CHECKWALIGN32( RN(ir) );
   865                     MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
   866                     break;
   867                 case 0x03: /* STC.L   SR, [--Rn] */
   868                     CHECKPRIV();
   869                     RN(ir) -= 4;
   870 		    CHECKWALIGN32( RN(ir) );
   871                     MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
   872                     break;
   873                 case 0x04: /* ROTL    Rn */
   874                     sh4r.t = RN(ir) >> 31;
   875                     RN(ir) <<= 1;
   876                     RN(ir) |= sh4r.t;
   877                     break;
   878                 case 0x05: /* ROTR    Rn */
   879                     sh4r.t = RN(ir) & 0x00000001;
   880                     RN(ir) >>= 1;
   881                     RN(ir) |= (sh4r.t << 31);
   882                     break;
   883                 case 0x06: /* LDS.L   [Rn++], MACH */
   884 		    CHECKRALIGN32( RN(ir) );
   885                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   886                         (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
   887                     RN(ir) += 4;
   888                     break;
   889                 case 0x07: /* LDC.L   [Rn++], SR */
   890 		    CHECKSLOTILLEGAL();
   891                     CHECKPRIV();
   892 		    CHECKWALIGN32( RN(ir) );
   893                     sh4_load_sr( MEM_READ_LONG(RN(ir)) );
   894                     RN(ir) +=4;
   895                     break;
   896                 case 0x08: /* SHLL2   Rn */
   897                     RN(ir) <<= 2;
   898                     break;
   899                 case 0x09: /* SHLR2   Rn */
   900                     RN(ir) >>= 2;
   901                     break;
   902                 case 0x0A: /* LDS     Rn, MACH */
   903                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   904                         (((uint64_t)RN(ir))<<32);
   905                     break;
   906                 case 0x0B: /* JSR     [Rn] */
   907                     CHECKDEST( RN(ir) );
   908                     CHECKSLOTILLEGAL();
   909                     sh4r.in_delay_slot = 1;
   910                     sh4r.pc = sh4r.new_pc;
   911                     sh4r.new_pc = RN(ir);
   912                     sh4r.pr = pc + 4;
   913 		    TRACE_CALL( pc, sh4r.new_pc );
   914                     return TRUE;
   915                 case 0x0E: /* LDC     Rn, SR */
   916 		    CHECKSLOTILLEGAL();
   917                     CHECKPRIV();
   918                     sh4_load_sr( RN(ir) );
   919                     break;
   920                 case 0x10: /* DT      Rn */
   921                     RN(ir) --;
   922                     sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
   923                     break;
   924                 case 0x11: /* CMP/PZ  Rn */
   925                     sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
   926                     break;
   927                 case 0x12: /* STS.L   MACL, [--Rn] */
   928                     RN(ir) -= 4;
   929 		    CHECKWALIGN32( RN(ir) );
   930                     MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
   931                     break;
   932                 case 0x13: /* STC.L   GBR, [--Rn] */
   933                     RN(ir) -= 4;
   934 		    CHECKWALIGN32( RN(ir) );
   935                     MEM_WRITE_LONG( RN(ir), sh4r.gbr );
   936                     break;
   937                 case 0x15: /* CMP/PL  Rn */
   938                     sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
   939                     break;
   940                 case 0x16: /* LDS.L   [Rn++], MACL */
   941 		    CHECKRALIGN32( RN(ir) );
   942                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   943                         (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
   944                     RN(ir) += 4;
   945                     break;
   946                 case 0x17: /* LDC.L   [Rn++], GBR */
   947 		    CHECKRALIGN32( RN(ir) );
   948                     sh4r.gbr = MEM_READ_LONG(RN(ir));
   949                     RN(ir) +=4;
   950                     break;
   951                 case 0x18: /* SHLL8   Rn */
   952                     RN(ir) <<= 8;
   953                     break;
   954                 case 0x19: /* SHLR8   Rn */
   955                     RN(ir) >>= 8;
   956                     break;
   957                 case 0x1A: /* LDS     Rn, MACL */
   958                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   959                         (uint64_t)((uint32_t)(RN(ir)));
   960                     break;
   961                 case 0x1B: /* TAS.B   [Rn] */
   962                     tmp = MEM_READ_BYTE( RN(ir) );
   963                     sh4r.t = ( tmp == 0 ? 1 : 0 );
   964                     MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
   965                     break;
   966                 case 0x1E: /* LDC     Rn, GBR */
   967                     sh4r.gbr = RN(ir);
   968                     break;
   969                 case 0x20: /* SHAL    Rn */
   970                     sh4r.t = RN(ir) >> 31;
   971                     RN(ir) <<= 1;
   972                     break;
   973                 case 0x21: /* SHAR    Rn */
   974                     sh4r.t = RN(ir) & 0x00000001;
   975                     RN(ir) = ((int32_t)RN(ir)) >> 1;
   976                     break;
   977                 case 0x22: /* STS.L   PR, [--Rn] */
   978                     RN(ir) -= 4;
   979 		    CHECKWALIGN32( RN(ir) );
   980                     MEM_WRITE_LONG( RN(ir), sh4r.pr );
   981                     break;
   982                 case 0x23: /* STC.L   VBR, [--Rn] */
   983                     CHECKPRIV();
   984                     RN(ir) -= 4;
   985 		    CHECKWALIGN32( RN(ir) );
   986                     MEM_WRITE_LONG( RN(ir), sh4r.vbr );
   987                     break;
   988                 case 0x24: /* ROTCL   Rn */
   989                     tmp = RN(ir) >> 31;
   990                     RN(ir) <<= 1;
   991                     RN(ir) |= sh4r.t;
   992                     sh4r.t = tmp;
   993                     break;
   994                 case 0x25: /* ROTCR   Rn */
   995                     tmp = RN(ir) & 0x00000001;
   996                     RN(ir) >>= 1;
   997                     RN(ir) |= (sh4r.t << 31 );
   998                     sh4r.t = tmp;
   999                     break;
  1000                 case 0x26: /* LDS.L   [Rn++], PR */
  1001 		    CHECKRALIGN32( RN(ir) );
  1002                     sh4r.pr = MEM_READ_LONG( RN(ir) );
  1003                     RN(ir) += 4;
  1004                     break;
  1005                 case 0x27: /* LDC.L   [Rn++], VBR */
  1006                     CHECKPRIV();
  1007 		    CHECKRALIGN32( RN(ir) );
  1008                     sh4r.vbr = MEM_READ_LONG(RN(ir));
  1009                     RN(ir) +=4;
  1010                     break;
  1011                 case 0x28: /* SHLL16  Rn */
  1012                     RN(ir) <<= 16;
  1013                     break;
  1014                 case 0x29: /* SHLR16  Rn */
  1015                     RN(ir) >>= 16;
  1016                     break;
  1017                 case 0x2A: /* LDS     Rn, PR */
  1018                     sh4r.pr = RN(ir);
  1019                     break;
  1020                 case 0x2B: /* JMP     [Rn] */
  1021                     CHECKDEST( RN(ir) );
  1022                     CHECKSLOTILLEGAL();
  1023                     sh4r.in_delay_slot = 1;
  1024                     sh4r.pc = sh4r.new_pc;
  1025                     sh4r.new_pc = RN(ir);
  1026                     return TRUE;
  1027                 case 0x2E: /* LDC     Rn, VBR */
  1028                     CHECKPRIV();
  1029                     sh4r.vbr = RN(ir);
  1030                     break;
  1031                 case 0x32: /* STC.L   SGR, [--Rn] */
  1032                     CHECKPRIV();
  1033                     RN(ir) -= 4;
  1034 		    CHECKWALIGN32( RN(ir) );
  1035                     MEM_WRITE_LONG( RN(ir), sh4r.sgr );
  1036                     break;
  1037                 case 0x33: /* STC.L   SSR, [--Rn] */
  1038                     CHECKPRIV();
  1039                     RN(ir) -= 4;
  1040 		    CHECKWALIGN32( RN(ir) );
  1041                     MEM_WRITE_LONG( RN(ir), sh4r.ssr );
  1042                     break;
  1043                 case 0x37: /* LDC.L   [Rn++], SSR */
  1044                     CHECKPRIV();
  1045 		    CHECKRALIGN32( RN(ir) );
  1046                     sh4r.ssr = MEM_READ_LONG(RN(ir));
  1047                     RN(ir) +=4;
  1048                     break;
  1049                 case 0x3E: /* LDC     Rn, SSR */
  1050                     CHECKPRIV();
  1051                     sh4r.ssr = RN(ir);
  1052                     break;
  1053                 case 0x43: /* STC.L   SPC, [--Rn] */
  1054                     CHECKPRIV();
  1055                     RN(ir) -= 4;
  1056 		    CHECKWALIGN32( RN(ir) );
  1057                     MEM_WRITE_LONG( RN(ir), sh4r.spc );
  1058                     break;
  1059                 case 0x47: /* LDC.L   [Rn++], SPC */
  1060                     CHECKPRIV();
  1061 		    CHECKRALIGN32( RN(ir) );
  1062                     sh4r.spc = MEM_READ_LONG(RN(ir));
  1063                     RN(ir) +=4;
  1064                     break;
  1065                 case 0x4E: /* LDC     Rn, SPC */
  1066                     CHECKPRIV();
  1067                     sh4r.spc = RN(ir);
  1068                     break;
  1069                 case 0x52: /* STS.L   FPUL, [--Rn] */
  1070                     RN(ir) -= 4;
  1071 		    CHECKWALIGN32( RN(ir) );
  1072                     MEM_WRITE_LONG( RN(ir), sh4r.fpul );
  1073                     break;
  1074                 case 0x56: /* LDS.L   [Rn++], FPUL */
  1075 		    CHECKRALIGN32( RN(ir) );
  1076                     sh4r.fpul = MEM_READ_LONG(RN(ir));
  1077                     RN(ir) +=4;
  1078                     break;
  1079                 case 0x5A: /* LDS     Rn, FPUL */
  1080                     sh4r.fpul = RN(ir);
  1081                     break;
  1082                 case 0x62: /* STS.L   FPSCR, [--Rn] */
  1083                     RN(ir) -= 4;
  1084 		    CHECKWALIGN32( RN(ir) );
  1085                     MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
  1086                     break;
  1087                 case 0x66: /* LDS.L   [Rn++], FPSCR */
  1088 		    CHECKRALIGN32( RN(ir) );
  1089                     sh4r.fpscr = MEM_READ_LONG(RN(ir));
  1090                     RN(ir) +=4;
  1091                     break;
  1092                 case 0x6A: /* LDS     Rn, FPSCR */
  1093                     sh4r.fpscr = RN(ir);
  1094                     break;
  1095                 case 0xF2: /* STC.L   DBR, [--Rn] */
  1096                     CHECKPRIV();
  1097                     RN(ir) -= 4;
  1098 		    CHECKWALIGN32( RN(ir) );
  1099                     MEM_WRITE_LONG( RN(ir), sh4r.dbr );
  1100                     break;
  1101                 case 0xF6: /* LDC.L   [Rn++], DBR */
  1102                     CHECKPRIV();
  1103 		    CHECKRALIGN32( RN(ir) );
  1104                     sh4r.dbr = MEM_READ_LONG(RN(ir));
  1105                     RN(ir) +=4;
  1106                     break;
  1107                 case 0xFA: /* LDC     Rn, DBR */
  1108                     CHECKPRIV();
  1109                     sh4r.dbr = RN(ir);
  1110                     break;
  1111                 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
  1112                 case 0xD3: case 0xE3: case 0xF3: /* STC.L   Rn_BANK, [--Rn] */
  1113                     CHECKPRIV();
  1114                     RN(ir) -= 4;
  1115 		    CHECKWALIGN32( RN(ir) );
  1116                     MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
  1117                     break;
  1118                 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
  1119                 case 0xD7: case 0xE7: case 0xF7: /* LDC.L   [Rn++], Rn_BANK */
  1120                     CHECKPRIV();
  1121 		    CHECKRALIGN32( RN(ir) );
  1122                     RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
  1123                     RN(ir) += 4;
  1124                     break;
  1125                 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
  1126                 case 0xDE: case 0xEE: case 0xFE: /* LDC     Rm, Rn_BANK */
  1127                     CHECKPRIV();
  1128                     RN_BANK(ir) = RM(ir);
  1129                     break;
  1130                 default:
  1131                     if( (ir&0x000F) == 0x0F ) {
  1132                         /* MAC.W   [Rm++], [Rn++] */
  1133 			CHECKRALIGN16( RN(ir) );
  1134 			CHECKRALIGN16( RM(ir) );
  1135                         tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
  1136                             SIGNEXT16(MEM_READ_WORD(RN(ir)));
  1137                         if( sh4r.s ) {
  1138                             /* FIXME */
  1139                             UNIMP(ir);
  1140                         } else sh4r.mac += SIGNEXT32(tmp);
  1141                         RM(ir) += 2;
  1142                         RN(ir) += 2;
  1143                     } else if( (ir&0x000F) == 0x0C ) {
  1144                         /* SHAD    Rm, Rn */
  1145                         tmp = RM(ir);
  1146                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
  1147                         else if( (tmp & 0x1F) == 0 )  
  1148 			  RN(ir) = ((int32_t)RN(ir)) >> 31;
  1149                         else 
  1150 			  RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
  1151                     } else if( (ir&0x000F) == 0x0D ) {
  1152                         /* SHLD    Rm, Rn */
  1153                         tmp = RM(ir);
  1154                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
  1155                         else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
  1156                         else RN(ir) >>= (((~tmp) & 0x1F)+1);
  1157                     } else UNDEF(ir);
  1159             break;
  1160         case 5: /* 0101nnnnmmmmdddd */
  1161             /* MOV.L   [Rm + disp4*4], Rn */
  1162 	    tmp = RM(ir) + (DISP4(ir)<<2);
  1163 	    CHECKRALIGN32( tmp );
  1164             RN(ir) = MEM_READ_LONG( tmp );
  1165             break;
  1166         case 6: /* 0110xxxxxxxxxxxx */
  1167             switch( ir&0x000f ) {
  1168                 case 0: /* MOV.B   [Rm], Rn */
  1169                     RN(ir) = MEM_READ_BYTE( RM(ir) );
  1170                     break;
  1171                 case 1: /* MOV.W   [Rm], Rn */
  1172 		    CHECKRALIGN16( RM(ir) );
  1173                     RN(ir) = MEM_READ_WORD( RM(ir) );
  1174                     break;
  1175                 case 2: /* MOV.L   [Rm], Rn */
  1176 		    CHECKRALIGN32( RM(ir) );
  1177                     RN(ir) = MEM_READ_LONG( RM(ir) );
  1178                     break;
  1179                 case 3: /* MOV     Rm, Rn */
  1180                     RN(ir) = RM(ir);
  1181                     break;
  1182                 case 4: /* MOV.B   [Rm++], Rn */
  1183                     RN(ir) = MEM_READ_BYTE( RM(ir) );
  1184                     RM(ir) ++;
  1185                     break;
  1186                 case 5: /* MOV.W   [Rm++], Rn */
  1187 		    CHECKRALIGN16( RM(ir) );
  1188                     RN(ir) = MEM_READ_WORD( RM(ir) );
  1189                     RM(ir) += 2;
  1190                     break;
  1191                 case 6: /* MOV.L   [Rm++], Rn */
  1192 		    CHECKRALIGN32( RM(ir) );
  1193                     RN(ir) = MEM_READ_LONG( RM(ir) );
  1194                     RM(ir) += 4;
  1195                     break;
  1196                 case 7: /* NOT     Rm, Rn */
  1197                     RN(ir) = ~RM(ir);
  1198                     break;
  1199                 case 8: /* SWAP.B  Rm, Rn */
  1200                     RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
  1201                         ((RM(ir)&0x000000FF)<<8);
  1202                     break;
  1203                 case 9: /* SWAP.W  Rm, Rn */
  1204                     RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
  1205                     break;
  1206                 case 10:/* NEGC    Rm, Rn */
  1207                     tmp = 0 - RM(ir);
  1208                     RN(ir) = tmp - sh4r.t;
  1209                     sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
  1210                     break;
  1211                 case 11:/* NEG     Rm, Rn */
  1212                     RN(ir) = 0 - RM(ir);
  1213                     break;
  1214                 case 12:/* EXTU.B  Rm, Rn */
  1215                     RN(ir) = RM(ir)&0x000000FF;
  1216                     break;
  1217                 case 13:/* EXTU.W  Rm, Rn */
  1218                     RN(ir) = RM(ir)&0x0000FFFF;
  1219                     break;
  1220                 case 14:/* EXTS.B  Rm, Rn */
  1221                     RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
  1222                     break;
  1223                 case 15:/* EXTS.W  Rm, Rn */
  1224                     RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
  1225                     break;
  1227             break;
  1228         case 7: /* 0111nnnniiiiiiii */
  1229             /* ADD    imm8, Rn */
  1230             RN(ir) += IMM8(ir);
  1231             break;
  1232         case 8: /* 1000xxxxxxxxxxxx */
  1233             switch( (ir&0x0F00) >> 8 ) {
  1234                 case 0: /* MOV.B   R0, [Rm + disp4] */
  1235                     MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
  1236                     break;
  1237                 case 1: /* MOV.W   R0, [Rm + disp4*2] */
  1238 		    tmp = RM(ir) + (DISP4(ir)<<1);
  1239 		    CHECKWALIGN16( tmp );
  1240                     MEM_WRITE_WORD( tmp, R0 );
  1241                     break;
  1242                 case 4: /* MOV.B   [Rm + disp4], R0 */
  1243                     R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
  1244                     break;
  1245                 case 5: /* MOV.W   [Rm + disp4*2], R0 */
  1246 		    tmp = RM(ir) + (DISP4(ir)<<1);
  1247 		    CHECKRALIGN16( tmp );
  1248                     R0 = MEM_READ_WORD( tmp );
  1249                     break;
  1250                 case 8: /* CMP/EQ  imm, R0 */
  1251                     sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
  1252                     break;
  1253                 case 9: /* BT      disp8 */
  1254                     CHECKSLOTILLEGAL();
  1255                     if( sh4r.t ) {
  1256                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1257                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
  1258                         sh4r.new_pc = sh4r.pc + 2;
  1259                         return TRUE;
  1261                     break;
  1262                 case 11:/* BF      disp8 */
  1263                     CHECKSLOTILLEGAL();
  1264                     if( !sh4r.t ) {
  1265                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1266                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
  1267                         sh4r.new_pc = sh4r.pc + 2;
  1268                         return TRUE;
  1270                     break;
  1271                 case 13:/* BT/S    disp8 */
  1272                     CHECKSLOTILLEGAL();
  1273                     if( sh4r.t ) {
  1274                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1275                         sh4r.in_delay_slot = 1;
  1276                         sh4r.pc = sh4r.new_pc;
  1277                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
  1278                         sh4r.in_delay_slot = 1;
  1279                         return TRUE;
  1281                     break;
  1282                 case 15:/* BF/S    disp8 */
  1283                     CHECKSLOTILLEGAL();
  1284                     if( !sh4r.t ) {
  1285                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1286                         sh4r.in_delay_slot = 1;
  1287                         sh4r.pc = sh4r.new_pc;
  1288                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
  1289                         return TRUE;
  1291                     break;
  1292                 default: UNDEF(ir);
  1294             break;
  1295         case 9: /* 1001xxxxxxxxxxxx */
  1296             /* MOV.W   [disp8*2 + pc + 4], Rn */
  1297 	    CHECKSLOTILLEGAL();
  1298 	    tmp = pc + 4 + (DISP8(ir)<<1);
  1299             RN(ir) = MEM_READ_WORD( tmp );
  1300             break;
  1301         case 10:/* 1010dddddddddddd */
  1302             /* BRA     disp12 */
  1303             CHECKSLOTILLEGAL();
  1304             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 );
  1305             sh4r.in_delay_slot = 1;
  1306             sh4r.pc = sh4r.new_pc;
  1307             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
  1308             return TRUE;
  1309         case 11:/* 1011dddddddddddd */
  1310             /* BSR     disp12 */
  1311             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 );
  1312 	    CHECKSLOTILLEGAL();
  1313             sh4r.in_delay_slot = 1;
  1314             sh4r.pr = pc + 4;
  1315             sh4r.pc = sh4r.new_pc;
  1316             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
  1317 	    TRACE_CALL( pc, sh4r.new_pc );
  1318             return TRUE;
  1319         case 12:/* 1100xxxxdddddddd */
  1320         switch( (ir&0x0F00)>>8 ) {
  1321                 case 0: /* MOV.B  R0, [GBR + disp8] */
  1322                     MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
  1323                     break;
  1324                 case 1: /* MOV.W  R0, [GBR + disp8*2] */
  1325 		    tmp = sh4r.gbr + (DISP8(ir)<<1);
  1326 		    CHECKWALIGN16( tmp );
  1327                     MEM_WRITE_WORD( tmp, R0 );
  1328                     break;
  1329                 case  2: /*MOV.L   R0, [GBR + disp8*4] */
  1330 		    tmp = sh4r.gbr + (DISP8(ir)<<2);
  1331 		    CHECKWALIGN32( tmp );
  1332                     MEM_WRITE_LONG( tmp, R0 );
  1333                     break;
  1334                 case 3: /* TRAPA   imm8 */
  1335                     CHECKSLOTILLEGAL();
  1336                     MMIO_WRITE( MMU, TRA, UIMM8(ir)<<2 );
  1337 		    sh4r.pc += 2;
  1338                     sh4_raise_exception( EXC_TRAP );
  1339                     break;
  1340                 case 4: /* MOV.B   [GBR + disp8], R0 */
  1341                     R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
  1342                     break;
  1343                 case 5: /* MOV.W   [GBR + disp8*2], R0 */
  1344 		    tmp = sh4r.gbr + (DISP8(ir)<<1);
  1345 		    CHECKRALIGN16( tmp );
  1346                     R0 = MEM_READ_WORD( tmp );
  1347                     break;
  1348                 case 6: /* MOV.L   [GBR + disp8*4], R0 */
  1349 		    tmp = sh4r.gbr + (DISP8(ir)<<2);
  1350 		    CHECKRALIGN32( tmp );
  1351                     R0 = MEM_READ_LONG( tmp );
  1352                     break;
  1353                 case 7: /* MOVA    disp8 + pc&~3 + 4, R0 */
  1354 		    CHECKSLOTILLEGAL();
  1355                     R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
  1356                     break;
  1357                 case 8: /* TST     imm8, R0 */
  1358                     sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
  1359                     break;
  1360                 case 9: /* AND     imm8, R0 */
  1361                     R0 &= UIMM8(ir);
  1362                     break;
  1363                 case 10:/* XOR     imm8, R0 */
  1364                     R0 ^= UIMM8(ir);
  1365                     break;
  1366                 case 11:/* OR      imm8, R0 */
  1367                     R0 |= UIMM8(ir);
  1368                     break;
  1369                 case 12:/* TST.B   imm8, [R0+GBR] */		    
  1370                     sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
  1371                     break;
  1372                 case 13:/* AND.B   imm8, [R0+GBR] */
  1373                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1374                                     UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
  1375                     break;
  1376                 case 14:/* XOR.B   imm8, [R0+GBR] */
  1377                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1378                                     UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
  1379                     break;
  1380                 case 15:/* OR.B    imm8, [R0+GBR] */
  1381                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1382                                     UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
  1383                     break;
  1385             break;
  1386         case 13:/* 1101nnnndddddddd */
  1387             /* MOV.L   [disp8*4 + pc&~3 + 4], Rn */
  1388 	    CHECKSLOTILLEGAL();
  1389 	    tmp = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
  1390             RN(ir) = MEM_READ_LONG( tmp );
  1391             break;
  1392         case 14:/* 1110nnnniiiiiiii */
  1393             /* MOV     imm8, Rn */
  1394             RN(ir) = IMM8(ir);
  1395             break;
  1396         case 15:/* 1111xxxxxxxxxxxx */
  1397             CHECKFPUEN();
  1398 	    if( IS_FPU_DOUBLEPREC() ) {
  1399 		switch( ir&0x000F ) {
  1400                 case 0: /* FADD    FRm, FRn */
  1401                     DRN(ir) += DRM(ir);
  1402                     break;
  1403                 case 1: /* FSUB    FRm, FRn */
  1404                     DRN(ir) -= DRM(ir);
  1405                     break;
  1406                 case 2: /* FMUL    FRm, FRn */
  1407                     DRN(ir) = DRN(ir) * DRM(ir);
  1408                     break;
  1409                 case 3: /* FDIV    FRm, FRn */
  1410                     DRN(ir) = DRN(ir) / DRM(ir);
  1411                     break;
  1412                 case 4: /* FCMP/EQ FRm, FRn */
  1413                     sh4r.t = ( DRN(ir) == DRM(ir) ? 1 : 0 );
  1414                     break;
  1415                 case 5: /* FCMP/GT FRm, FRn */
  1416                     sh4r.t = ( DRN(ir) > DRM(ir) ? 1 : 0 );
  1417                     break;
  1418                 case 6: /* FMOV.S  [Rm+R0], FRn */
  1419                     MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
  1420                     break;
  1421                 case 7: /* FMOV.S  FRm, [Rn+R0] */
  1422                     MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
  1423                     break;
  1424                 case 8: /* FMOV.S  [Rm], FRn */
  1425                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1426                     break;
  1427                 case 9: /* FMOV.S  [Rm++], FRn */
  1428                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1429                     RM(ir) += FP_WIDTH;
  1430                     break;
  1431                 case 10:/* FMOV.S  FRm, [Rn] */
  1432                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1433                     break;
  1434                 case 11:/* FMOV.S  FRm, [--Rn] */
  1435                     RN(ir) -= FP_WIDTH;
  1436                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1437                     break;
  1438                 case 12:/* FMOV    FRm, FRn */
  1439 		    if( IS_FPU_DOUBLESIZE() )
  1440 			DRN(ir) = DRM(ir);
  1441 		    else
  1442 			FRN(ir) = FRM(ir);
  1443                     break;
  1444                 case 13:
  1445                     switch( (ir&0x00F0) >> 4 ) {
  1446 		    case 0: /* FSTS    FPUL, FRn */
  1447 			FRN(ir) = FPULf;
  1448 			break;
  1449 		    case 1: /* FLDS    FRn,FPUL */
  1450 			FPULf = FRN(ir);
  1451 			break;
  1452 		    case 2: /* FLOAT   FPUL, FRn */
  1453 			DRN(ir) = (float)FPULi;
  1454 			break;
  1455 		    case 3: /* FTRC    FRn, FPUL */
  1456 			dtmp = DRN(ir);
  1457 			if( dtmp >= MAX_INTF )
  1458 			    FPULi = MAX_INT;
  1459 			else if( dtmp <= MIN_INTF )
  1460 			    FPULi = MIN_INT;
  1461 			else 
  1462 			    FPULi = (int32_t)dtmp;
  1463 			break;
  1464 		    case 4: /* FNEG    FRn */
  1465 			DRN(ir) = -DRN(ir);
  1466 			break;
  1467 		    case 5: /* FABS    FRn */
  1468 			DRN(ir) = fabs(DRN(ir));
  1469 			break;
  1470 		    case 6: /* FSQRT   FRn */
  1471 			DRN(ir) = sqrt(DRN(ir));
  1472 			break;
  1473 		    case 7: /* FSRRA FRn */
  1474 			/* NO-OP when PR=1 */
  1475 			break;
  1476 		    case 8: /* FLDI0   FRn */
  1477 			DRN(ir) = 0.0;
  1478 			break;
  1479 		    case 9: /* FLDI1   FRn */
  1480 			DRN(ir) = 1.0;
  1481 			break;
  1482 		    case 10: /* FCNVSD FPUL, DRn */
  1483 			if( ! IS_FPU_DOUBLESIZE() )
  1484 			    DRN(ir) = (double)FPULf;
  1485 			break;
  1486 		    case 11: /* FCNVDS DRn, FPUL */
  1487 			if( ! IS_FPU_DOUBLESIZE() )
  1488 			    FPULf = (float)DRN(ir);
  1489 			break;
  1490 		    case 14:/* FIPR    FVm, FVn */
  1491 			/* NO-OP when PR=1 */
  1492 			break;
  1493 		    case 15:
  1494 			if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
  1495 			    /* NO-OP when PR=1 */
  1496 			    break;
  1498 			else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */	
  1499 			    /* NO-OP when PR=1 */
  1500 			    break;
  1502 			else if( ir == 0xFBFD ) {
  1503 			    /* FRCHG   */
  1504 			    sh4r.fpscr ^= FPSCR_FR;
  1505 			    break;
  1507 			else if( ir == 0xF3FD ) {
  1508 			    /* FSCHG   */
  1509 			    sh4r.fpscr ^= FPSCR_SZ;
  1510 			    break;
  1512 		    default: UNDEF(ir);
  1514                     break;
  1515                 case 14:/* FMAC    FR0, FRm, FRn */
  1516                     DRN(ir) += DRM(ir)*DR0;
  1517                     break;
  1518                 default: UNDEF(ir);
  1520 	    } else { /* Single precision */
  1521 		switch( ir&0x000F ) {
  1522                 case 0: /* FADD    FRm, FRn */
  1523                     FRN(ir) += FRM(ir);
  1524                     break;
  1525                 case 1: /* FSUB    FRm, FRn */
  1526                     FRN(ir) -= FRM(ir);
  1527                     break;
  1528                 case 2: /* FMUL    FRm, FRn */
  1529                     FRN(ir) = FRN(ir) * FRM(ir);
  1530                     break;
  1531                 case 3: /* FDIV    FRm, FRn */
  1532                     FRN(ir) = FRN(ir) / FRM(ir);
  1533                     break;
  1534                 case 4: /* FCMP/EQ FRm, FRn */
  1535                     sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
  1536                     break;
  1537                 case 5: /* FCMP/GT FRm, FRn */
  1538                     sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
  1539                     break;
  1540                 case 6: /* FMOV.S  [Rm+R0], FRn */
  1541                     MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
  1542                     break;
  1543                 case 7: /* FMOV.S  FRm, [Rn+R0] */
  1544                     MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
  1545                     break;
  1546                 case 8: /* FMOV.S  [Rm], FRn */
  1547                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1548                     break;
  1549                 case 9: /* FMOV.S  [Rm++], FRn */
  1550                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1551                     RM(ir) += FP_WIDTH;
  1552                     break;
  1553                 case 10:/* FMOV.S  FRm, [Rn] */
  1554                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1555                     break;
  1556                 case 11:/* FMOV.S  FRm, [--Rn] */
  1557                     RN(ir) -= FP_WIDTH;
  1558                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1559                     break;
  1560                 case 12:/* FMOV    FRm, FRn */
  1561 		    if( IS_FPU_DOUBLESIZE() )
  1562 			DRN(ir) = DRM(ir);
  1563 		    else
  1564 			FRN(ir) = FRM(ir);
  1565                     break;
  1566                 case 13:
  1567                     switch( (ir&0x00F0) >> 4 ) {
  1568 		    case 0: /* FSTS    FPUL, FRn */
  1569 			FRN(ir) = FPULf;
  1570 			break;
  1571 		    case 1: /* FLDS    FRn,FPUL */
  1572 			FPULf = FRN(ir);
  1573 			break;
  1574 		    case 2: /* FLOAT   FPUL, FRn */
  1575 			FRN(ir) = (float)FPULi;
  1576 			break;
  1577 		    case 3: /* FTRC    FRn, FPUL */
  1578 			ftmp = FRN(ir);
  1579 			if( ftmp >= MAX_INTF )
  1580 			    FPULi = MAX_INT;
  1581 			else if( ftmp <= MIN_INTF )
  1582 			    FPULi = MIN_INT;
  1583 			else
  1584 			    FPULi = (int32_t)ftmp;
  1585 			break;
  1586 		    case 4: /* FNEG    FRn */
  1587 			FRN(ir) = -FRN(ir);
  1588 			break;
  1589 		    case 5: /* FABS    FRn */
  1590 			FRN(ir) = fabsf(FRN(ir));
  1591 			break;
  1592 		    case 6: /* FSQRT   FRn */
  1593 			FRN(ir) = sqrtf(FRN(ir));
  1594 			break;
  1595 		    case 7: /* FSRRA FRn */
  1596 			FRN(ir) = 1.0/sqrtf(FRN(ir));
  1597 			break;
  1598 		    case 8: /* FLDI0   FRn */
  1599 			FRN(ir) = 0.0;
  1600 			break;
  1601 		    case 9: /* FLDI1   FRn */
  1602 			FRN(ir) = 1.0;
  1603 			break;
  1604 		    case 10: /* FCNVSD FPUL, DRn */
  1605 			break;
  1606 		    case 11: /* FCNVDS DRn, FPUL */
  1607 			break;
  1608 		    case 14:/* FIPR    FVm, FVn */
  1609                             /* FIXME: This is not going to be entirely accurate
  1610                              * as the SH4 instruction is less precise. Also
  1611                              * need to check for 0s and infinities.
  1612                              */
  1614                             int tmp2 = FVN(ir);
  1615                             tmp = FVM(ir);
  1616                             FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  1617                                 FR(tmp+1)*FR(tmp2+1) +
  1618                                 FR(tmp+2)*FR(tmp2+2) +
  1619                                 FR(tmp+3)*FR(tmp2+3);
  1620                             break;
  1622 		    case 15:
  1623 			if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
  1624 			    tmp = FVN(ir);
  1625 			    float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
  1626 			    FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
  1627 				XF(8)*fv[2] + XF(12)*fv[3];
  1628 			    FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
  1629 				XF(9)*fv[2] + XF(13)*fv[3];
  1630 			    FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
  1631 				XF(10)*fv[2] + XF(14)*fv[3];
  1632 			    FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
  1633 				XF(11)*fv[2] + XF(15)*fv[3];
  1634 			    break;
  1636 			else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */
  1637 			    float angle = (((float)(short)(FPULi>>16)) +
  1638 					   (((float)(FPULi&0xFFFF))/65536.0)) *
  1639 				2 * M_PI;
  1640 			    int reg = FRNn(ir);
  1641 			    FR(reg) = sinf(angle);
  1642 			    FR(reg+1) = cosf(angle);
  1643 			    break;
  1645 			else if( ir == 0xFBFD ) {
  1646 			    /* FRCHG   */
  1647 			    sh4r.fpscr ^= FPSCR_FR;
  1648 			    break;
  1650 			else if( ir == 0xF3FD ) {
  1651 			    /* FSCHG   */
  1652 			    sh4r.fpscr ^= FPSCR_SZ;
  1653 			    break;
  1655 		    default: UNDEF(ir);
  1657                     break;
  1658                 case 14:/* FMAC    FR0, FRm, FRn */
  1659                     FRN(ir) += FRM(ir)*FR0;
  1660                     break;
  1661                 default: UNDEF(ir);
  1664 	    break;
  1666     sh4r.pc = sh4r.new_pc;
  1667     sh4r.new_pc += 2;
  1668     sh4r.in_delay_slot = 0;
  1669     return TRUE;
.