Search
lxdream.org :: lxdream/src/sh4/sh4mmio.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/sh4mmio.c
changeset 312:2c34bdc36cbd
prev166:8aa70cf503a2
next323:067583c1a704
author nkeynes
date Tue Jan 23 08:17:06 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Save/restore MMU state (specifically the OC cache ram) correctly
view annotate diff log raw
     1 /**
     2  * $Id: sh4mmio.c,v 1.10 2007-01-23 08:17:06 nkeynes Exp $
     3  * 
     4  * Miscellaneous and not-really-implemented SH4 peripheral modules. Also
     5  * responsible for including the IMPL side of the SH4 MMIO pages.
     6  * Most of these will eventually be split off into their own files.
     7  *
     8  * Copyright (c) 2005 Nathan Keynes.
     9  *
    10  * This program is free software; you can redistribute it and/or modify
    11  * it under the terms of the GNU General Public License as published by
    12  * the Free Software Foundation; either version 2 of the License, or
    13  * (at your option) any later version.
    14  *
    15  * This program is distributed in the hope that it will be useful,
    16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    18  * GNU General Public License for more details.
    19  */
    20 #define MODULE sh4_module
    22 #include "dream.h"
    23 #include "mem.h"
    24 #include "clock.h"
    25 #include "sh4core.h"
    26 #include "sh4mmio.h"
    27 #define MMIO_IMPL
    28 #include "sh4mmio.h"
    30 /********************************* MMU *************************************/
    32 MMIO_REGION_READ_DEFFN( MMU )
    34 #define OCRAM_START (0x1C000000>>PAGE_BITS)
    35 #define OCRAM_END   (0x20000000>>PAGE_BITS)
    37 static char *cache = NULL;
    39 void mmio_region_MMU_write( uint32_t reg, uint32_t val )
    40 {
    41     switch(reg) {
    42         case CCR:
    43             mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
    44             break;
    45         default:
    46             break;
    47     }
    48     MMIO_WRITE( MMU, reg, val );
    49 }
    52 void MMU_init() 
    53 {
    54     cache = mem_alloc_pages(2);
    55 }
    57 void MMU_reset()
    58 {
    59     mmio_region_MMU_write( CCR, 0 );
    60 }
    62 void MMU_save_state( FILE *f )
    63 {
    64     fwrite( cache, 4096, 2, f );
    65 }
    67 int MMU_load_state( FILE *f )
    68 {
    69     /* Setup the cache mode according to the saved register value
    70      * (mem_load runs before this point to load all MMIO data)
    71      */
    72     mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
    73     if( fread( cache, 4096, 2, f ) != 2 ) {
    74 	return 1;
    75     }
    76     return 0;
    77 }
    79 void mmu_set_cache_mode( int mode )
    80 {
    81     uint32_t i;
    82     switch( mode ) {
    83         case MEM_OC_INDEX0: /* OIX=0 */
    84             for( i=OCRAM_START; i<OCRAM_END; i++ )
    85                 page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));
    86             break;
    87         case MEM_OC_INDEX1: /* OIX=1 */
    88             for( i=OCRAM_START; i<OCRAM_END; i++ )
    89                 page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));
    90             break;
    91         default: /* disabled */
    92             for( i=OCRAM_START; i<OCRAM_END; i++ )
    93                 page_map[i] = NULL;
    94             break;
    95     }
    96 }
    99 /********************************* BSC *************************************/
   101 uint16_t bsc_output_mask_lo = 0, bsc_output_mask_hi = 0;
   102 uint16_t bsc_input_mask_lo = 0, bsc_input_mask_hi = 0;
   103 uint32_t bsc_output = 0, bsc_input = 0x0300;
   105 void bsc_out( int output, int mask )
   106 {
   107     /* Go figure... The BIOS won't start without this mess though */
   108     if( ((output | (~mask)) & 0x03) == 3 ) {
   109         bsc_output |= 0x03;
   110     } else {
   111         bsc_output &= ~0x03;
   112     }
   113 }
   115 void mmio_region_BSC_write( uint32_t reg, uint32_t val )
   116 {
   117     int i;
   118     switch( reg ) {
   119         case PCTRA:
   120             bsc_input_mask_lo = bsc_output_mask_lo = 0;
   121             for( i=0; i<16; i++ ) {
   122                 int bits = (val >> (i<<1)) & 0x03;
   123                 if( bits == 2 ) bsc_input_mask_lo |= (1<<i);
   124                 else if( bits != 0 ) bsc_output_mask_lo |= (1<<i);
   125             }
   126             bsc_output = (bsc_output&0x000F0000) |
   127                 (MMIO_READ( BSC, PDTRA ) & bsc_output_mask_lo);
   128             bsc_out( MMIO_READ( BSC, PDTRA ) | ((MMIO_READ(BSC,PDTRB)<<16)),
   129                      bsc_output_mask_lo | (bsc_output_mask_hi<<16) );
   130             break;
   131         case PCTRB:
   132             bsc_input_mask_hi = bsc_output_mask_hi = 0;
   133             for( i=0; i<4; i++ ) {
   134                 int bits = (val >> (i>>1)) & 0x03;
   135                 if( bits == 2 ) bsc_input_mask_hi |= (1<<i);
   136                 else if( bits != 0 ) bsc_output_mask_hi |= (1<<i);
   137             }
   138             bsc_output = (bsc_output&0xFFFF) |
   139                 ((MMIO_READ( BSC, PDTRA ) & bsc_output_mask_hi)<<16);
   140             break;
   141         case PDTRA:
   142             bsc_output = (bsc_output&0x000F0000) |
   143                 (val & bsc_output_mask_lo );
   144             bsc_out( val | ((MMIO_READ(BSC,PDTRB)<<16)),
   145                      bsc_output_mask_lo | (bsc_output_mask_hi<<16) );
   146             break;
   147         case PDTRB:
   148             bsc_output = (bsc_output&0xFFFF) |
   149                 ( (val & bsc_output_mask_hi)<<16 );
   150             break;
   151     }
   152     WARN( "Write to (mostly) unimplemented BSC (%03X <= %08X) [%s: %s]",
   153           reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );
   154     MMIO_WRITE( BSC, reg, val );
   155 }
   157 int32_t mmio_region_BSC_read( uint32_t reg )
   158 {
   159     int32_t val;
   160     switch( reg ) {
   161         case PDTRA:
   162             val = (bsc_input & bsc_input_mask_lo) | (bsc_output&0xFFFF);
   163             break;
   164         case PDTRB:
   165             val = ((bsc_input>>16) & bsc_input_mask_hi) | (bsc_output>>16);
   166             break;
   167         default:
   168             val = MMIO_READ( BSC, reg );
   169     }
   170     WARN( "Read from (mostly) unimplemented BSC (%03X => %08X) [%s: %s]",
   171           reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );
   172     return val;
   173 }
   175 /********************************* UBC *************************************/
   177 MMIO_REGION_STUBFNS( UBC )
   180 /********************************** SCI *************************************/
   182 MMIO_REGION_STUBFNS( SCI )
.