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lxdream.org :: lxdream/src/sh4/mmu.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/mmu.c
changeset 960:2f0819278fdb
prev955:e289b49c28f1
next963:1c3a0f67c603
author nkeynes
date Wed Jan 14 23:27:57 2009 +0000 (13 years ago)
permissions -rw-r--r--
last change Execute the mem_unprotect call only on 64-bit platforms (where it may be needed), since
it seems to break on OS X 10.4 32-bit, at least
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     1 /**
     2  * $Id$
     3  *
     4  * SH4 MMU implementation based on address space page maps. This module
     5  * is responsible for all address decoding functions. 
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    19 #define MODULE sh4_module
    21 #include <stdio.h>
    22 #include <assert.h>
    23 #include "sh4/sh4mmio.h"
    24 #include "sh4/sh4core.h"
    25 #include "sh4/sh4trans.h"
    26 #include "dreamcast.h"
    27 #include "mem.h"
    28 #include "mmu.h"
    30 #define RAISE_TLB_ERROR(code, vpn) sh4_raise_tlb_exception(code, vpn)
    31 #define RAISE_MEM_ERROR(code, vpn) \
    32     MMIO_WRITE(MMU, TEA, vpn); \
    33     MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
    34     sh4_raise_exception(code);
    35 #define RAISE_TLB_MULTIHIT_ERROR(vpn) sh4_raise_tlb_multihit(vpn)
    37 /* An entry is a 1K entry if it's one of the mmu_utlb_1k_pages entries */
    38 #define IS_1K_PAGE_ENTRY(ent)  ( ((uintptr_t)(((struct utlb_1k_entry *)ent) - &mmu_utlb_1k_pages[0])) < UTLB_ENTRY_COUNT )
    40 /* Primary address space (used directly by SH4 cores) */
    41 mem_region_fn_t *sh4_address_space;
    42 mem_region_fn_t *sh4_user_address_space;
    44 /* Accessed from the UTLB accessor methods */
    45 uint32_t mmu_urc;
    46 uint32_t mmu_urb;
    47 static gboolean mmu_urc_overflow; /* If true, urc was set >= urb */  
    49 /* Module globals */
    50 static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT];
    51 static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT];
    52 static struct utlb_page_entry mmu_utlb_pages[UTLB_ENTRY_COUNT];
    53 static uint32_t mmu_lrui;
    54 static uint32_t mmu_asid; // current asid
    55 static struct utlb_default_regions *mmu_user_storequeue_regions;
    57 /* Structures for 1K page handling */
    58 static struct utlb_1k_entry mmu_utlb_1k_pages[UTLB_ENTRY_COUNT];
    59 static int mmu_utlb_1k_free_list[UTLB_ENTRY_COUNT];
    60 static int mmu_utlb_1k_free_index;
    63 /* Function prototypes */
    64 static void mmu_invalidate_tlb();
    65 static void mmu_utlb_register_all();
    66 static void mmu_utlb_remove_entry(int);
    67 static void mmu_utlb_insert_entry(int);
    68 static void mmu_register_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn );
    69 static void mmu_register_user_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn );
    70 static void mmu_set_tlb_enabled( int tlb_on );
    71 static void mmu_set_tlb_asid( uint32_t asid );
    72 static void mmu_set_storequeue_protected( int protected, int tlb_on );
    73 static gboolean mmu_utlb_map_pages( mem_region_fn_t priv_page, mem_region_fn_t user_page, sh4addr_t start_addr, int npages );
    74 static void mmu_utlb_remap_pages( gboolean remap_priv, gboolean remap_user, int entryNo );
    75 static gboolean mmu_utlb_unmap_pages( gboolean unmap_priv, gboolean unmap_user, sh4addr_t start_addr, int npages );
    76 static gboolean mmu_ext_page_remapped( sh4addr_t page, mem_region_fn_t fn, void *user_data );
    77 static void mmu_utlb_1k_init();
    78 static struct utlb_1k_entry *mmu_utlb_1k_alloc();
    79 static void mmu_utlb_1k_free( struct utlb_1k_entry *entry );
    80 static int mmu_read_urc();
    82 static void FASTCALL tlb_miss_read( sh4addr_t addr, void *exc );
    83 static int32_t FASTCALL tlb_protected_read( sh4addr_t addr, void *exc );
    84 static void FASTCALL tlb_protected_write( sh4addr_t addr, uint32_t val, void *exc );
    85 static void FASTCALL tlb_initial_write( sh4addr_t addr, uint32_t val, void *exc );
    86 static uint32_t get_tlb_size_mask( uint32_t flags );
    87 static uint32_t get_tlb_size_pages( uint32_t flags );
    89 #define DEFAULT_REGIONS 0
    90 #define DEFAULT_STOREQUEUE_REGIONS 1
    91 #define DEFAULT_STOREQUEUE_SQMD_REGIONS 2
    93 static struct utlb_default_regions mmu_default_regions[3] = {
    94         { &mem_region_tlb_miss, &mem_region_tlb_protected, &mem_region_tlb_multihit },
    95         { &p4_region_storequeue_miss, &p4_region_storequeue_protected, &p4_region_storequeue_multihit },
    96         { &p4_region_storequeue_sqmd_miss, &p4_region_storequeue_sqmd_protected, &p4_region_storequeue_sqmd_multihit } };
    98 #define IS_STOREQUEUE_PROTECTED() (mmu_user_storequeue_regions == &mmu_default_regions[DEFAULT_STOREQUEUE_SQMD_REGIONS])
   100 /*********************** Module public functions ****************************/
   102 /**
   103  * Allocate memory for the address space maps, and initialize them according
   104  * to the default (reset) values. (TLB is disabled by default)
   105  */
   107 void MMU_init()
   108 {
   109     sh4_address_space = mem_alloc_pages( sizeof(mem_region_fn_t) * 256 );
   110     sh4_user_address_space = mem_alloc_pages( sizeof(mem_region_fn_t) * 256 );
   111     mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
   113     mmu_set_tlb_enabled(0);
   114     mmu_register_user_mem_region( 0x80000000, 0x00000000, &mem_region_address_error );
   115     mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );                                
   117     /* Setup P4 tlb/cache access regions */
   118     mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
   119     mmu_register_mem_region( 0xE4000000, 0xF0000000, &mem_region_unmapped );
   120     mmu_register_mem_region( 0xF0000000, 0xF1000000, &p4_region_icache_addr );
   121     mmu_register_mem_region( 0xF1000000, 0xF2000000, &p4_region_icache_data );
   122     mmu_register_mem_region( 0xF2000000, 0xF3000000, &p4_region_itlb_addr );
   123     mmu_register_mem_region( 0xF3000000, 0xF4000000, &p4_region_itlb_data );
   124     mmu_register_mem_region( 0xF4000000, 0xF5000000, &p4_region_ocache_addr );
   125     mmu_register_mem_region( 0xF5000000, 0xF6000000, &p4_region_ocache_data );
   126     mmu_register_mem_region( 0xF6000000, 0xF7000000, &p4_region_utlb_addr );
   127     mmu_register_mem_region( 0xF7000000, 0xF8000000, &p4_region_utlb_data );
   128     mmu_register_mem_region( 0xF8000000, 0x00000000, &mem_region_unmapped );
   130     /* Setup P4 control region */
   131     mmu_register_mem_region( 0xFF000000, 0xFF001000, &mmio_region_MMU.fn );
   132     mmu_register_mem_region( 0xFF100000, 0xFF101000, &mmio_region_PMM.fn );
   133     mmu_register_mem_region( 0xFF200000, 0xFF201000, &mmio_region_UBC.fn );
   134     mmu_register_mem_region( 0xFF800000, 0xFF801000, &mmio_region_BSC.fn );
   135     mmu_register_mem_region( 0xFF900000, 0xFFA00000, &mem_region_unmapped ); // SDMR2 + SDMR3
   136     mmu_register_mem_region( 0xFFA00000, 0xFFA01000, &mmio_region_DMAC.fn );
   137     mmu_register_mem_region( 0xFFC00000, 0xFFC01000, &mmio_region_CPG.fn );
   138     mmu_register_mem_region( 0xFFC80000, 0xFFC81000, &mmio_region_RTC.fn );
   139     mmu_register_mem_region( 0xFFD00000, 0xFFD01000, &mmio_region_INTC.fn );
   140     mmu_register_mem_region( 0xFFD80000, 0xFFD81000, &mmio_region_TMU.fn );
   141     mmu_register_mem_region( 0xFFE00000, 0xFFE01000, &mmio_region_SCI.fn );
   142     mmu_register_mem_region( 0xFFE80000, 0xFFE81000, &mmio_region_SCIF.fn );
   143     mmu_register_mem_region( 0xFFF00000, 0xFFF01000, &mem_region_unmapped ); // H-UDI
   145     register_mem_page_remapped_hook( mmu_ext_page_remapped, NULL );
   146     mmu_utlb_1k_init();
   148     /* Ensure the code regions are executable (64-bit only). Although it might
   149      * be more portable to mmap these at runtime rather than using static decls
   150      */
   151 #if SIZEOF_VOID_P == 8
   152     mem_unprotect( mmu_utlb_pages, sizeof(mmu_utlb_pages) );
   153     mem_unprotect( mmu_utlb_1k_pages, sizeof(mmu_utlb_1k_pages) );
   154 #endif
   155 }
   157 void MMU_reset()
   158 {
   159     mmio_region_MMU_write( CCR, 0 );
   160     mmio_region_MMU_write( MMUCR, 0 );
   161 }
   163 void MMU_save_state( FILE *f )
   164 {
   165     mmu_read_urc();   
   166     fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f );
   167     fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f );
   168     fwrite( &mmu_urc, sizeof(mmu_urc), 1, f );
   169     fwrite( &mmu_urb, sizeof(mmu_urb), 1, f );
   170     fwrite( &mmu_lrui, sizeof(mmu_lrui), 1, f );
   171     fwrite( &mmu_asid, sizeof(mmu_asid), 1, f );
   172 }
   174 int MMU_load_state( FILE *f )
   175 {
   176     if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) {
   177         return 1;
   178     }
   179     if( fread( &mmu_utlb, sizeof(mmu_utlb), 1, f ) != 1 ) {
   180         return 1;
   181     }
   182     if( fread( &mmu_urc, sizeof(mmu_urc), 1, f ) != 1 ) {
   183         return 1;
   184     }
   185     if( fread( &mmu_urc, sizeof(mmu_urb), 1, f ) != 1 ) {
   186         return 1;
   187     }
   188     if( fread( &mmu_lrui, sizeof(mmu_lrui), 1, f ) != 1 ) {
   189         return 1;
   190     }
   191     if( fread( &mmu_asid, sizeof(mmu_asid), 1, f ) != 1 ) {
   192         return 1;
   193     }
   195     uint32_t mmucr = MMIO_READ(MMU,MMUCR);
   196     mmu_urc_overflow = mmu_urc >= mmu_urb;
   197     mmu_set_tlb_enabled(mmucr&MMUCR_AT);
   198     mmu_set_storequeue_protected(mmucr&MMUCR_SQMD, mmucr&MMUCR_AT);
   199     return 0;
   200 }
   202 /**
   203  * LDTLB instruction implementation. Copies PTEH, PTEL and PTEA into the UTLB
   204  * entry identified by MMUCR.URC. Does not modify MMUCR or the ITLB.
   205  */
   206 void MMU_ldtlb()
   207 {
   208     int urc = mmu_read_urc();
   209     if( mmu_utlb[urc].flags & TLB_VALID )
   210         mmu_utlb_remove_entry( urc );
   211     mmu_utlb[urc].vpn = MMIO_READ(MMU, PTEH) & 0xFFFFFC00;
   212     mmu_utlb[urc].asid = MMIO_READ(MMU, PTEH) & 0x000000FF;
   213     mmu_utlb[urc].ppn = MMIO_READ(MMU, PTEL) & 0x1FFFFC00;
   214     mmu_utlb[urc].flags = MMIO_READ(MMU, PTEL) & 0x00001FF;
   215     mmu_utlb[urc].pcmcia = MMIO_READ(MMU, PTEA);
   216     mmu_utlb[urc].mask = get_tlb_size_mask(mmu_utlb[urc].flags);
   217     if( mmu_utlb[urc].flags & TLB_VALID )
   218         mmu_utlb_insert_entry( urc );
   219 }
   222 MMIO_REGION_READ_FN( MMU, reg )
   223 {
   224     reg &= 0xFFF;
   225     switch( reg ) {
   226     case MMUCR:
   227         return MMIO_READ( MMU, MMUCR) | (mmu_read_urc()<<10) | ((mmu_urb&0x3F)<<18) | (mmu_lrui<<26);
   228     default:
   229         return MMIO_READ( MMU, reg );
   230     }
   231 }
   233 MMIO_REGION_WRITE_FN( MMU, reg, val )
   234 {
   235     uint32_t tmp;
   236     reg &= 0xFFF;
   237     switch(reg) {
   238     case SH4VER:
   239         return;
   240     case PTEH:
   241         val &= 0xFFFFFCFF;
   242         if( (val & 0xFF) != mmu_asid ) {
   243             mmu_set_tlb_asid( val&0xFF );
   244             sh4_icache.page_vma = -1; // invalidate icache as asid has changed
   245         }
   246         break;
   247     case PTEL:
   248         val &= 0x1FFFFDFF;
   249         break;
   250     case PTEA:
   251         val &= 0x0000000F;
   252         break;
   253     case TRA:
   254         val &= 0x000003FC;
   255         break;
   256     case EXPEVT:
   257     case INTEVT:
   258         val &= 0x00000FFF;
   259         break;
   260     case MMUCR:
   261         if( val & MMUCR_TI ) {
   262             mmu_invalidate_tlb();
   263         }
   264         mmu_urc = (val >> 10) & 0x3F;
   265         mmu_urb = (val >> 18) & 0x3F;
   266         if( mmu_urb == 0 ) {
   267             mmu_urb = 0x40;
   268         } else if( mmu_urc >= mmu_urb ) {
   269             mmu_urc_overflow = TRUE;
   270         }
   271         mmu_lrui = (val >> 26) & 0x3F;
   272         val &= 0x00000301;
   273         tmp = MMIO_READ( MMU, MMUCR );
   274         if( (val ^ tmp) & (MMUCR_SQMD) ) {
   275             mmu_set_storequeue_protected( val & MMUCR_SQMD, val&MMUCR_AT );
   276         }
   277         if( (val ^ tmp) & (MMUCR_AT) ) {
   278             // AT flag has changed state - flush the xlt cache as all bets
   279             // are off now. We also need to force an immediate exit from the
   280             // current block
   281             mmu_set_tlb_enabled( val & MMUCR_AT );
   282             MMIO_WRITE( MMU, MMUCR, val );
   283             sh4_core_exit( CORE_EXIT_FLUSH_ICACHE );
   284             xlat_flush_cache(); // If we're not running, flush the cache anyway
   285         }
   286         break;
   287     case CCR:
   288         CCN_set_cache_control( val );
   289         val &= 0x81A7;
   290         break;
   291     case MMUUNK1:
   292         /* Note that if the high bit is set, this appears to reset the machine.
   293          * Not emulating this behaviour yet until we know why...
   294          */
   295         val &= 0x00010007;
   296         break;
   297     case QACR0:
   298     case QACR1:
   299         val &= 0x0000001C;
   300         break;
   301     case PMCR1:
   302         PMM_write_control(0, val);
   303         val &= 0x0000C13F;
   304         break;
   305     case PMCR2:
   306         PMM_write_control(1, val);
   307         val &= 0x0000C13F;
   308         break;
   309     default:
   310         break;
   311     }
   312     MMIO_WRITE( MMU, reg, val );
   313 }
   315 /********************** 1K Page handling ***********************/
   316 /* Since we use 4K pages as our native page size, 1K pages need a bit of extra
   317  * effort to manage - we justify this on the basis that most programs won't
   318  * actually use 1K pages, so we may as well optimize for the common case.
   319  * 
   320  * Implementation uses an intermediate page entry (the utlb_1k_entry) that
   321  * redirects requests to the 'real' page entry. These are allocated on an
   322  * as-needed basis, and returned to the pool when all subpages are empty.
   323  */ 
   324 static void mmu_utlb_1k_init()
   325 {
   326     int i;
   327     for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   328         mmu_utlb_1k_free_list[i] = i;
   329         mmu_utlb_1k_init_vtable( &mmu_utlb_1k_pages[i] );
   330     }
   331     mmu_utlb_1k_free_index = 0;
   332 }
   334 static struct utlb_1k_entry *mmu_utlb_1k_alloc()
   335 {
   336     assert( mmu_utlb_1k_free_index < UTLB_ENTRY_COUNT );
   337     struct utlb_1k_entry *entry = &mmu_utlb_1k_pages[mmu_utlb_1k_free_index++];
   338     return entry;
   339 }    
   341 static void mmu_utlb_1k_free( struct utlb_1k_entry *ent )
   342 {
   343     unsigned int entryNo = ent - &mmu_utlb_1k_pages[0];
   344     assert( entryNo < UTLB_ENTRY_COUNT );
   345     assert( mmu_utlb_1k_free_index > 0 );
   346     mmu_utlb_1k_free_list[--mmu_utlb_1k_free_index] = entryNo;
   347 }
   350 /********************** Address space maintenance *************************/
   352 /**
   353  * MMU accessor functions just increment URC - fixup here if necessary
   354  */
   355 static int mmu_read_urc()
   356 {
   357     if( mmu_urc_overflow ) {
   358         if( mmu_urc >= 0x40 ) {
   359             mmu_urc_overflow = FALSE;
   360             mmu_urc -= 0x40;
   361             mmu_urc %= mmu_urb;
   362         }
   363     } else {
   364         mmu_urc %= mmu_urb;
   365     }
   366     return mmu_urc;
   367 }
   369 static void mmu_register_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn )
   370 {
   371     int count = (end - start) >> 12;
   372     mem_region_fn_t *ptr = &sh4_address_space[start>>12];
   373     while( count-- > 0 ) {
   374         *ptr++ = fn;
   375     }
   376 }
   377 static void mmu_register_user_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn )
   378 {
   379     int count = (end - start) >> 12;
   380     mem_region_fn_t *ptr = &sh4_user_address_space[start>>12];
   381     while( count-- > 0 ) {
   382         *ptr++ = fn;
   383     }
   384 }
   386 static gboolean mmu_ext_page_remapped( sh4addr_t page, mem_region_fn_t fn, void *user_data )
   387 {
   388     int i;
   389     if( (MMIO_READ(MMU,MMUCR)) & MMUCR_AT ) {
   390         /* TLB on */
   391         sh4_address_space[(page|0x80000000)>>12] = fn; /* Direct map to P1 and P2 */
   392         sh4_address_space[(page|0xA0000000)>>12] = fn;
   393         /* Scan UTLB and update any direct-referencing entries */
   394     } else {
   395         /* Direct map to U0, P0, P1, P2, P3 */
   396         for( i=0; i<= 0xC0000000; i+= 0x20000000 ) {
   397             sh4_address_space[(page|i)>>12] = fn;
   398         }
   399         for( i=0; i < 0x80000000; i+= 0x20000000 ) {
   400             sh4_user_address_space[(page|i)>>12] = fn;
   401         }
   402     }
   403 }
   405 static void mmu_set_tlb_enabled( int tlb_on )
   406 {
   407     mem_region_fn_t *ptr, *uptr;
   408     int i;
   410     /* Reset the storequeue area */
   412     if( tlb_on ) {
   413         mmu_register_mem_region(0x00000000, 0x80000000, &mem_region_tlb_miss );
   414         mmu_register_mem_region(0xC0000000, 0xE0000000, &mem_region_tlb_miss );
   415         mmu_register_user_mem_region(0x00000000, 0x80000000, &mem_region_tlb_miss );
   417         /* Default SQ prefetch goes to TLB miss (?) */
   418         mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue_miss );
   419         mmu_register_user_mem_region( 0xE0000000, 0xE4000000, mmu_user_storequeue_regions->tlb_miss );
   420         mmu_utlb_register_all();
   421     } else {
   422         for( i=0, ptr = sh4_address_space; i<7; i++, ptr += LXDREAM_PAGE_TABLE_ENTRIES ) {
   423             memcpy( ptr, ext_address_space, sizeof(mem_region_fn_t) * LXDREAM_PAGE_TABLE_ENTRIES );
   424         }
   425         for( i=0, ptr = sh4_user_address_space; i<4; i++, ptr += LXDREAM_PAGE_TABLE_ENTRIES ) {
   426             memcpy( ptr, ext_address_space, sizeof(mem_region_fn_t) * LXDREAM_PAGE_TABLE_ENTRIES );
   427         }
   429         mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
   430         if( IS_STOREQUEUE_PROTECTED() ) {
   431             mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue_sqmd );
   432         } else {
   433             mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
   434         }
   435     }
   437 }
   439 /**
   440  * Flip the SQMD switch - this is rather expensive, so will need to be changed if
   441  * anything expects to do this frequently.
   442  */
   443 static void mmu_set_storequeue_protected( int protected, int tlb_on ) 
   444 {
   445     mem_region_fn_t nontlb_region;
   446     int i;
   448     if( protected ) {
   449         mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_SQMD_REGIONS];
   450         nontlb_region = &p4_region_storequeue_sqmd;
   451     } else {
   452         mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
   453         nontlb_region = &p4_region_storequeue; 
   454     }
   456     if( tlb_on ) {
   457         mmu_register_user_mem_region( 0xE0000000, 0xE4000000, mmu_user_storequeue_regions->tlb_miss );
   458         for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   459             if( (mmu_utlb[i].vpn & 0xFC000000) == 0xE0000000 ) {
   460                 mmu_utlb_insert_entry(i);
   461             }
   462         }
   463     } else {
   464         mmu_register_user_mem_region( 0xE0000000, 0xE4000000, nontlb_region ); 
   465     }
   467 }
   469 static void mmu_set_tlb_asid( uint32_t asid )
   470 {
   471     /* Scan for pages that need to be remapped */
   472     int i;
   473     if( IS_SV_ENABLED() ) {
   474         for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   475             if( mmu_utlb[i].flags & TLB_VALID ) {
   476                 if( (mmu_utlb[i].flags & TLB_SHARE) == 0 ) {
   477                     if( mmu_utlb[i].asid == mmu_asid ) { // Matches old ASID - unmap out
   478                         if( !mmu_utlb_unmap_pages( FALSE, TRUE, mmu_utlb[i].vpn&mmu_utlb[i].mask,
   479                                 get_tlb_size_pages(mmu_utlb[i].flags) ) )
   480                             mmu_utlb_remap_pages( FALSE, TRUE, i );
   481                     } else if( mmu_utlb[i].asid == asid ) { // Matches new ASID - map in
   482                         mmu_utlb_map_pages( NULL, mmu_utlb_pages[i].user_fn, 
   483                                 mmu_utlb[i].vpn&mmu_utlb[i].mask, 
   484                                 get_tlb_size_pages(mmu_utlb[i].flags) );  
   485                     }
   486                 }
   487             }
   488         }
   489     } else {
   490         // Remap both Priv+user pages
   491         for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   492             if( mmu_utlb[i].flags & TLB_VALID ) {
   493                 if( (mmu_utlb[i].flags & TLB_SHARE) == 0 ) {
   494                     if( mmu_utlb[i].asid == mmu_asid ) { // Matches old ASID - unmap out
   495                         if( !mmu_utlb_unmap_pages( TRUE, TRUE, mmu_utlb[i].vpn&mmu_utlb[i].mask,
   496                                 get_tlb_size_pages(mmu_utlb[i].flags) ) )
   497                             mmu_utlb_remap_pages( TRUE, TRUE, i );
   498                     } else if( mmu_utlb[i].asid == asid ) { // Matches new ASID - map in
   499                         mmu_utlb_map_pages( &mmu_utlb_pages[i].fn, mmu_utlb_pages[i].user_fn, 
   500                                 mmu_utlb[i].vpn&mmu_utlb[i].mask, 
   501                                 get_tlb_size_pages(mmu_utlb[i].flags) );  
   502                     }
   503                 }
   504             }
   505         }
   506     }
   508     mmu_asid = asid;
   509 }
   511 static uint32_t get_tlb_size_mask( uint32_t flags )
   512 {
   513     switch( flags & TLB_SIZE_MASK ) {
   514     case TLB_SIZE_1K: return MASK_1K;
   515     case TLB_SIZE_4K: return MASK_4K;
   516     case TLB_SIZE_64K: return MASK_64K;
   517     case TLB_SIZE_1M: return MASK_1M;
   518     default: return 0; /* Unreachable */
   519     }
   520 }
   521 static uint32_t get_tlb_size_pages( uint32_t flags )
   522 {
   523     switch( flags & TLB_SIZE_MASK ) {
   524     case TLB_SIZE_1K: return 0;
   525     case TLB_SIZE_4K: return 1;
   526     case TLB_SIZE_64K: return 16;
   527     case TLB_SIZE_1M: return 256;
   528     default: return 0; /* Unreachable */
   529     }
   530 }
   532 /**
   533  * Add a new TLB entry mapping to the address space table. If any of the pages
   534  * are already mapped, they are mapped to the TLB multi-hit page instead.
   535  * @return FALSE if a TLB multihit situation was detected, otherwise TRUE.
   536  */ 
   537 static gboolean mmu_utlb_map_pages( mem_region_fn_t priv_page, mem_region_fn_t user_page, sh4addr_t start_addr, int npages )
   538 {
   539     mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
   540     mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
   541     struct utlb_default_regions *privdefs = &mmu_default_regions[DEFAULT_REGIONS];
   542     struct utlb_default_regions *userdefs = privdefs;    
   544     gboolean mapping_ok = TRUE;
   545     int i;
   547     if( (start_addr & 0xFC000000) == 0xE0000000 ) {
   548         /* Storequeue mapping */
   549         privdefs = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
   550         userdefs = mmu_user_storequeue_regions;
   551     } else if( (start_addr & 0xE0000000) == 0xC0000000 ) {
   552         user_page = NULL; /* No user access to P3 region */
   553     } else if( start_addr >= 0x80000000 ) {
   554         return TRUE; // No mapping - legal but meaningless
   555     }
   557     if( npages == 0 ) {
   558         struct utlb_1k_entry *ent;
   559         int i, idx = (start_addr >> 10) & 0x03;
   560         if( IS_1K_PAGE_ENTRY(*ptr) ) {
   561             ent = (struct utlb_1k_entry *)*ptr;
   562         } else {
   563             ent = mmu_utlb_1k_alloc();
   564             /* New 1K struct - init to previous contents of region */
   565             for( i=0; i<4; i++ ) {
   566                 ent->subpages[i] = *ptr;
   567                 ent->user_subpages[i] = *uptr;
   568             }
   569             *ptr = &ent->fn;
   570             *uptr = &ent->user_fn;
   571         }
   573         if( priv_page != NULL ) {
   574             if( ent->subpages[idx] == privdefs->tlb_miss ) {
   575                 ent->subpages[idx] = priv_page;
   576             } else {
   577                 mapping_ok = FALSE;
   578                 ent->subpages[idx] = privdefs->tlb_multihit;
   579             }
   580         }
   581         if( user_page != NULL ) {
   582             if( ent->user_subpages[idx] == userdefs->tlb_miss ) {
   583                 ent->user_subpages[idx] = user_page;
   584             } else {
   585                 mapping_ok = FALSE;
   586                 ent->user_subpages[idx] = userdefs->tlb_multihit;
   587             }
   588         }
   590     } else {
   591         if( priv_page != NULL ) {
   592             /* Privileged mapping only */
   593             for( i=0; i<npages; i++ ) {
   594                 if( *ptr == privdefs->tlb_miss ) {
   595                     *ptr++ = priv_page;
   596                 } else {
   597                     mapping_ok = FALSE;
   598                     *ptr++ = privdefs->tlb_multihit;
   599                 }
   600             }
   601         }
   602         if( user_page != NULL ) {
   603             /* User mapping only (eg ASID change remap w/ SV=1) */
   604             for( i=0; i<npages; i++ ) {
   605                 if( *uptr == userdefs->tlb_miss ) {
   606                     *uptr++ = user_page;
   607                 } else {
   608                     mapping_ok = FALSE;
   609                     *uptr++ = userdefs->tlb_multihit;
   610                 }
   611             }        
   612         }
   613     }
   615     return mapping_ok;
   616 }
   618 /**
   619  * Remap any pages within the region covered by entryNo, but not including 
   620  * entryNo itself. This is used to reestablish pages that were previously
   621  * covered by a multi-hit exception region when one of the pages is removed.
   622  */
   623 static void mmu_utlb_remap_pages( gboolean remap_priv, gboolean remap_user, int entryNo )
   624 {
   625     int mask = mmu_utlb[entryNo].mask;
   626     uint32_t remap_addr = mmu_utlb[entryNo].vpn & mask;
   627     int i;
   629     for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   630         if( i != entryNo && (mmu_utlb[i].vpn & mask) == remap_addr && (mmu_utlb[i].flags & TLB_VALID) ) {
   631             /* Overlapping region */
   632             mem_region_fn_t priv_page = (remap_priv ? &mmu_utlb_pages[i].fn : NULL);
   633             mem_region_fn_t user_page = (remap_priv ? mmu_utlb_pages[i].user_fn : NULL);
   634             uint32_t start_addr;
   635             int npages;
   637             if( mmu_utlb[i].mask >= mask ) {
   638                 /* entry is no larger than the area we're replacing - map completely */
   639                 start_addr = mmu_utlb[i].vpn & mmu_utlb[i].mask;
   640                 npages = get_tlb_size_pages( mmu_utlb[i].flags );
   641             } else {
   642                 /* Otherwise map subset - region covered by removed page */
   643                 start_addr = remap_addr;
   644                 npages = get_tlb_size_pages( mmu_utlb[entryNo].flags );
   645             }
   647             if( (mmu_utlb[i].flags & TLB_SHARE) || mmu_utlb[i].asid == mmu_asid ) { 
   648                 mmu_utlb_map_pages( priv_page, user_page, start_addr, npages );
   649             } else if( IS_SV_ENABLED() ) {
   650                 mmu_utlb_map_pages( priv_page, NULL, start_addr, npages );
   651             }
   653         }
   654     }
   655 }
   657 /**
   658  * Remove a previous TLB mapping (replacing them with the TLB miss region).
   659  * @return FALSE if any pages were previously mapped to the TLB multihit page, 
   660  * otherwise TRUE. In either case, all pages in the region are cleared to TLB miss.
   661  */
   662 static gboolean mmu_utlb_unmap_pages( gboolean unmap_priv, gboolean unmap_user, sh4addr_t start_addr, int npages )
   663 {
   664     mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
   665     mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
   666     struct utlb_default_regions *privdefs = &mmu_default_regions[DEFAULT_REGIONS];
   667     struct utlb_default_regions *userdefs = privdefs;
   669     gboolean unmapping_ok = TRUE;
   670     int i;
   672     if( (start_addr & 0xFC000000) == 0xE0000000 ) {
   673         /* Storequeue mapping */
   674         privdefs = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
   675         userdefs = mmu_user_storequeue_regions;
   676     } else if( (start_addr & 0xE0000000) == 0xC0000000 ) {
   677         unmap_user = FALSE;
   678     } else if( start_addr >= 0x80000000 ) {
   679         return TRUE; // No mapping - legal but meaningless
   680     }
   682     if( npages == 0 ) { // 1K page
   683         assert( IS_1K_PAGE_ENTRY( *ptr ) );
   684         struct utlb_1k_entry *ent = (struct utlb_1k_entry *)*ptr;
   685         int i, idx = (start_addr >> 10) & 0x03, mergeable=1;
   686         if( ent->subpages[idx] == privdefs->tlb_multihit ) {
   687             unmapping_ok = FALSE;
   688         }
   689         if( unmap_priv )
   690             ent->subpages[idx] = privdefs->tlb_miss;
   691         if( unmap_user )
   692             ent->user_subpages[idx] = userdefs->tlb_miss;
   694         /* If all 4 subpages have the same content, merge them together and
   695          * release the 1K entry
   696          */
   697         mem_region_fn_t priv_page = ent->subpages[0];
   698         mem_region_fn_t user_page = ent->user_subpages[0];
   699         for( i=1; i<4; i++ ) {
   700             if( priv_page != ent->subpages[i] || user_page != ent->user_subpages[i] ) {
   701                 mergeable = 0;
   702                 break;
   703             }
   704         }
   705         if( mergeable ) {
   706             mmu_utlb_1k_free(ent);
   707             *ptr = priv_page;
   708             *uptr = user_page;
   709         }
   710     } else {
   711         if( unmap_priv ) {
   712             /* Privileged (un)mapping */
   713             for( i=0; i<npages; i++ ) {
   714                 if( *ptr == privdefs->tlb_multihit ) {
   715                     unmapping_ok = FALSE;
   716                 }
   717                 *ptr++ = privdefs->tlb_miss;
   718             }
   719         }
   720         if( unmap_user ) {
   721             /* User (un)mapping */
   722             for( i=0; i<npages; i++ ) {
   723                 if( *uptr == userdefs->tlb_multihit ) {
   724                     unmapping_ok = FALSE;
   725                 }
   726                 *uptr++ = userdefs->tlb_miss;
   727             }            
   728         }
   729     }
   731     return unmapping_ok;
   732 }
   734 static void mmu_utlb_insert_entry( int entry )
   735 {
   736     struct utlb_entry *ent = &mmu_utlb[entry];
   737     mem_region_fn_t page = &mmu_utlb_pages[entry].fn;
   738     mem_region_fn_t upage;
   739     sh4addr_t start_addr = ent->vpn & ent->mask;
   740     int npages = get_tlb_size_pages(ent->flags);
   742     if( (start_addr & 0xFC000000) == 0xE0000000 ) {
   743         /* Store queue mappings are a bit different - normal access is fixed to
   744          * the store queue register block, and we only map prefetches through
   745          * the TLB 
   746          */
   747         mmu_utlb_init_storequeue_vtable( ent, &mmu_utlb_pages[entry] );
   749         if( (ent->flags & TLB_USERMODE) == 0 ) {
   750             upage = mmu_user_storequeue_regions->tlb_prot;
   751         } else if( IS_STOREQUEUE_PROTECTED() ) {
   752             upage = &p4_region_storequeue_sqmd;
   753         } else {
   754             upage = page;
   755         }
   757     }  else {
   759         if( (ent->flags & TLB_USERMODE) == 0 ) {
   760             upage = &mem_region_tlb_protected;
   761         } else {        
   762             upage = page;
   763         }
   765         if( (ent->flags & TLB_WRITABLE) == 0 ) {
   766             page->write_long = (mem_write_fn_t)tlb_protected_write;
   767             page->write_word = (mem_write_fn_t)tlb_protected_write;
   768             page->write_byte = (mem_write_fn_t)tlb_protected_write;
   769             page->write_burst = (mem_write_burst_fn_t)tlb_protected_write;
   770             mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], FALSE );
   771         } else if( (ent->flags & TLB_DIRTY) == 0 ) {
   772             page->write_long = (mem_write_fn_t)tlb_initial_write;
   773             page->write_word = (mem_write_fn_t)tlb_initial_write;
   774             page->write_byte = (mem_write_fn_t)tlb_initial_write;
   775             page->write_burst = (mem_write_burst_fn_t)tlb_initial_write;
   776             mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], FALSE );
   777         } else {
   778             mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], TRUE );
   779         }
   780     }
   782     mmu_utlb_pages[entry].user_fn = upage;
   784     /* Is page visible? */
   785     if( (ent->flags & TLB_SHARE) || ent->asid == mmu_asid ) { 
   786         mmu_utlb_map_pages( page, upage, start_addr, npages );
   787     } else if( IS_SV_ENABLED() ) {
   788         mmu_utlb_map_pages( page, NULL, start_addr, npages );
   789     }
   790 }
   792 static void mmu_utlb_remove_entry( int entry )
   793 {
   794     int i, j;
   795     struct utlb_entry *ent = &mmu_utlb[entry];
   796     sh4addr_t start_addr = ent->vpn&ent->mask;
   797     mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
   798     mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
   799     gboolean unmap_user;
   800     int npages = get_tlb_size_pages(ent->flags);
   802     if( (ent->flags & TLB_SHARE) || ent->asid == mmu_asid ) {
   803         unmap_user = TRUE;
   804     } else if( IS_SV_ENABLED() ) {
   805         unmap_user = FALSE;
   806     } else {
   807         return; // Not mapped
   808     }
   810     gboolean clean_unmap = mmu_utlb_unmap_pages( TRUE, unmap_user, start_addr, npages );
   812     if( !clean_unmap ) {
   813         mmu_utlb_remap_pages( TRUE, unmap_user, entry );
   814     }
   815 }
   817 static void mmu_utlb_register_all()
   818 {
   819     int i;
   820     for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   821         if( mmu_utlb[i].flags & TLB_VALID ) 
   822             mmu_utlb_insert_entry( i );
   823     }
   824 }
   826 static void mmu_invalidate_tlb()
   827 {
   828     int i;
   829     for( i=0; i<ITLB_ENTRY_COUNT; i++ ) {
   830         mmu_itlb[i].flags &= (~TLB_VALID);
   831     }
   832     if( IS_TLB_ENABLED() ) {
   833         for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   834             if( mmu_utlb[i].flags & TLB_VALID ) {
   835                 mmu_utlb_remove_entry( i );
   836             }
   837         }
   838     }
   839     for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   840         mmu_utlb[i].flags &= (~TLB_VALID);
   841     }
   842 }
   844 /******************************************************************************/
   845 /*                        MMU TLB address translation                         */
   846 /******************************************************************************/
   848 /**
   849  * Translate a 32-bit address into a UTLB entry number. Does not check for
   850  * page protection etc.
   851  * @return the entryNo if found, -1 if not found, and -2 for a multi-hit.
   852  */
   853 int mmu_utlb_entry_for_vpn( uint32_t vpn )
   854 {
   855     mem_region_fn_t fn = sh4_address_space[vpn>>12];
   856     if( fn >= &mmu_utlb_pages[0].fn && fn < &mmu_utlb_pages[UTLB_ENTRY_COUNT].fn ) {
   857         return ((struct utlb_page_entry *)fn) - &mmu_utlb_pages[0];
   858     } else if( fn == &mem_region_tlb_multihit ) {
   859         return -2;
   860     } else {
   861         return -1;
   862     }
   863 }
   866 /**
   867  * Perform the actual utlb lookup w/ asid matching.
   868  * Possible utcomes are:
   869  *   0..63 Single match - good, return entry found
   870  *   -1 No match - raise a tlb data miss exception
   871  *   -2 Multiple matches - raise a multi-hit exception (reset)
   872  * @param vpn virtual address to resolve
   873  * @return the resultant UTLB entry, or an error.
   874  */
   875 static inline int mmu_utlb_lookup_vpn_asid( uint32_t vpn )
   876 {
   877     int result = -1;
   878     unsigned int i;
   880     mmu_urc++;
   881     if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
   882         mmu_urc = 0;
   883     }
   885     for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
   886         if( (mmu_utlb[i].flags & TLB_VALID) &&
   887                 ((mmu_utlb[i].flags & TLB_SHARE) || mmu_asid == mmu_utlb[i].asid) &&
   888                 ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
   889             if( result != -1 ) {
   890                 return -2;
   891             }
   892             result = i;
   893         }
   894     }
   895     return result;
   896 }
   898 /**
   899  * Perform the actual utlb lookup matching on vpn only
   900  * Possible utcomes are:
   901  *   0..63 Single match - good, return entry found
   902  *   -1 No match - raise a tlb data miss exception
   903  *   -2 Multiple matches - raise a multi-hit exception (reset)
   904  * @param vpn virtual address to resolve
   905  * @return the resultant UTLB entry, or an error.
   906  */
   907 static inline int mmu_utlb_lookup_vpn( uint32_t vpn )
   908 {
   909     int result = -1;
   910     unsigned int i;
   912     mmu_urc++;
   913     if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
   914         mmu_urc = 0;
   915     }
   917     for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
   918         if( (mmu_utlb[i].flags & TLB_VALID) &&
   919                 ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
   920             if( result != -1 ) {
   921                 return -2;
   922             }
   923             result = i;
   924         }
   925     }
   927     return result;
   928 }
   930 /**
   931  * Update the ITLB by replacing the LRU entry with the specified UTLB entry.
   932  * @return the number (0-3) of the replaced entry.
   933  */
   934 static int inline mmu_itlb_update_from_utlb( int entryNo )
   935 {
   936     int replace;
   937     /* Determine entry to replace based on lrui */
   938     if( (mmu_lrui & 0x38) == 0x38 ) {
   939         replace = 0;
   940         mmu_lrui = mmu_lrui & 0x07;
   941     } else if( (mmu_lrui & 0x26) == 0x06 ) {
   942         replace = 1;
   943         mmu_lrui = (mmu_lrui & 0x19) | 0x20;
   944     } else if( (mmu_lrui & 0x15) == 0x01 ) {
   945         replace = 2;
   946         mmu_lrui = (mmu_lrui & 0x3E) | 0x14;
   947     } else { // Note - gets invalid entries too
   948         replace = 3;
   949         mmu_lrui = (mmu_lrui | 0x0B);
   950     }
   952     mmu_itlb[replace].vpn = mmu_utlb[entryNo].vpn;
   953     mmu_itlb[replace].mask = mmu_utlb[entryNo].mask;
   954     mmu_itlb[replace].ppn = mmu_utlb[entryNo].ppn;
   955     mmu_itlb[replace].asid = mmu_utlb[entryNo].asid;
   956     mmu_itlb[replace].flags = mmu_utlb[entryNo].flags & 0x01DA;
   957     return replace;
   958 }
   960 /**
   961  * Perform the actual itlb lookup w/ asid protection
   962  * Possible utcomes are:
   963  *   0..63 Single match - good, return entry found
   964  *   -1 No match - raise a tlb data miss exception
   965  *   -2 Multiple matches - raise a multi-hit exception (reset)
   966  * @param vpn virtual address to resolve
   967  * @return the resultant ITLB entry, or an error.
   968  */
   969 static inline int mmu_itlb_lookup_vpn_asid( uint32_t vpn )
   970 {
   971     int result = -1;
   972     unsigned int i;
   974     for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
   975         if( (mmu_itlb[i].flags & TLB_VALID) &&
   976                 ((mmu_itlb[i].flags & TLB_SHARE) || mmu_asid == mmu_itlb[i].asid) &&
   977                 ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
   978             if( result != -1 ) {
   979                 return -2;
   980             }
   981             result = i;
   982         }
   983     }
   985     if( result == -1 ) {
   986         int utlbEntry = mmu_utlb_entry_for_vpn( vpn );
   987         if( utlbEntry < 0 ) {
   988             return utlbEntry;
   989         } else {
   990             return mmu_itlb_update_from_utlb( utlbEntry );
   991         }
   992     }
   994     switch( result ) {
   995     case 0: mmu_lrui = (mmu_lrui & 0x07); break;
   996     case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
   997     case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
   998     case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
   999     }
  1001     return result;
  1004 /**
  1005  * Perform the actual itlb lookup on vpn only
  1006  * Possible utcomes are:
  1007  *   0..63 Single match - good, return entry found
  1008  *   -1 No match - raise a tlb data miss exception
  1009  *   -2 Multiple matches - raise a multi-hit exception (reset)
  1010  * @param vpn virtual address to resolve
  1011  * @return the resultant ITLB entry, or an error.
  1012  */
  1013 static inline int mmu_itlb_lookup_vpn( uint32_t vpn )
  1015     int result = -1;
  1016     unsigned int i;
  1018     for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
  1019         if( (mmu_itlb[i].flags & TLB_VALID) &&
  1020                 ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
  1021             if( result != -1 ) {
  1022                 return -2;
  1024             result = i;
  1028     if( result == -1 ) {
  1029         int utlbEntry = mmu_utlb_lookup_vpn( vpn );
  1030         if( utlbEntry < 0 ) {
  1031             return utlbEntry;
  1032         } else {
  1033             return mmu_itlb_update_from_utlb( utlbEntry );
  1037     switch( result ) {
  1038     case 0: mmu_lrui = (mmu_lrui & 0x07); break;
  1039     case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
  1040     case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
  1041     case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
  1044     return result;
  1047 /**
  1048  * Update the icache for an untranslated address
  1049  */
  1050 static inline void mmu_update_icache_phys( sh4addr_t addr )
  1052     if( (addr & 0x1C000000) == 0x0C000000 ) {
  1053         /* Main ram */
  1054         sh4_icache.page_vma = addr & 0xFF000000;
  1055         sh4_icache.page_ppa = 0x0C000000;
  1056         sh4_icache.mask = 0xFF000000;
  1057         sh4_icache.page = dc_main_ram;
  1058     } else if( (addr & 0x1FE00000) == 0 ) {
  1059         /* BIOS ROM */
  1060         sh4_icache.page_vma = addr & 0xFFE00000;
  1061         sh4_icache.page_ppa = 0;
  1062         sh4_icache.mask = 0xFFE00000;
  1063         sh4_icache.page = dc_boot_rom;
  1064     } else {
  1065         /* not supported */
  1066         sh4_icache.page_vma = -1;
  1070 /**
  1071  * Update the sh4_icache structure to describe the page(s) containing the
  1072  * given vma. If the address does not reference a RAM/ROM region, the icache
  1073  * will be invalidated instead.
  1074  * If AT is on, this method will raise TLB exceptions normally
  1075  * (hence this method should only be used immediately prior to execution of
  1076  * code), and otherwise will set the icache according to the matching TLB entry.
  1077  * If AT is off, this method will set the entire referenced RAM/ROM region in
  1078  * the icache.
  1079  * @return TRUE if the update completed (successfully or otherwise), FALSE
  1080  * if an exception was raised.
  1081  */
  1082 gboolean FASTCALL mmu_update_icache( sh4vma_t addr )
  1084     int entryNo;
  1085     if( IS_SH4_PRIVMODE()  ) {
  1086         if( addr & 0x80000000 ) {
  1087             if( addr < 0xC0000000 ) {
  1088                 /* P1, P2 and P4 regions are pass-through (no translation) */
  1089                 mmu_update_icache_phys(addr);
  1090                 return TRUE;
  1091             } else if( addr >= 0xE0000000 && addr < 0xFFFFFF00 ) {
  1092                 RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
  1093                 return FALSE;
  1097         uint32_t mmucr = MMIO_READ(MMU,MMUCR);
  1098         if( (mmucr & MMUCR_AT) == 0 ) {
  1099             mmu_update_icache_phys(addr);
  1100             return TRUE;
  1103         if( (mmucr & MMUCR_SV) == 0 )
  1104         	entryNo = mmu_itlb_lookup_vpn_asid( addr );
  1105         else
  1106         	entryNo = mmu_itlb_lookup_vpn( addr );
  1107     } else {
  1108         if( addr & 0x80000000 ) {
  1109             RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
  1110             return FALSE;
  1113         uint32_t mmucr = MMIO_READ(MMU,MMUCR);
  1114         if( (mmucr & MMUCR_AT) == 0 ) {
  1115             mmu_update_icache_phys(addr);
  1116             return TRUE;
  1119         entryNo = mmu_itlb_lookup_vpn_asid( addr );
  1121         if( entryNo != -1 && (mmu_itlb[entryNo].flags & TLB_USERMODE) == 0 ) {
  1122             RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
  1123             return FALSE;
  1127     switch(entryNo) {
  1128     case -1:
  1129     RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
  1130     return FALSE;
  1131     case -2:
  1132     RAISE_TLB_MULTIHIT_ERROR(addr);
  1133     return FALSE;
  1134     default:
  1135         sh4_icache.page_ppa = mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask;
  1136         sh4_icache.page = mem_get_region( sh4_icache.page_ppa );
  1137         if( sh4_icache.page == NULL ) {
  1138             sh4_icache.page_vma = -1;
  1139         } else {
  1140             sh4_icache.page_vma = mmu_itlb[entryNo].vpn & mmu_itlb[entryNo].mask;
  1141             sh4_icache.mask = mmu_itlb[entryNo].mask;
  1143         return TRUE;
  1147 /**
  1148  * Translate address for disassembly purposes (ie performs an instruction
  1149  * lookup) - does not raise exceptions or modify any state, and ignores
  1150  * protection bits. Returns the translated address, or MMU_VMA_ERROR
  1151  * on translation failure.
  1152  */
  1153 sh4addr_t FASTCALL mmu_vma_to_phys_disasm( sh4vma_t vma )
  1155     if( vma & 0x80000000 ) {
  1156         if( vma < 0xC0000000 ) {
  1157             /* P1, P2 and P4 regions are pass-through (no translation) */
  1158             return VMA_TO_EXT_ADDR(vma);
  1159         } else if( vma >= 0xE0000000 && vma < 0xFFFFFF00 ) {
  1160             /* Not translatable */
  1161             return MMU_VMA_ERROR;
  1165     uint32_t mmucr = MMIO_READ(MMU,MMUCR);
  1166     if( (mmucr & MMUCR_AT) == 0 ) {
  1167         return VMA_TO_EXT_ADDR(vma);
  1170     int entryNo = mmu_itlb_lookup_vpn( vma );
  1171     if( entryNo == -2 ) {
  1172         entryNo = mmu_itlb_lookup_vpn_asid( vma );
  1174     if( entryNo < 0 ) {
  1175         return MMU_VMA_ERROR;
  1176     } else {
  1177         return (mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask) |
  1178         (vma & (~mmu_itlb[entryNo].mask));
  1182 /********************** TLB Direct-Access Regions ***************************/
  1183 #ifdef HAVE_FRAME_ADDRESS
  1184 #define EXCEPTION_EXIT() do{ *(((void **)__builtin_frame_address(0))+1) = exc; return; } while(0)
  1185 #else
  1186 #define EXCEPTION_EXIT() sh4_core_exit(CORE_EXIT_EXCEPTION)
  1187 #endif
  1190 #define ITLB_ENTRY(addr) ((addr>>7)&0x03)
  1192 int32_t FASTCALL mmu_itlb_addr_read( sh4addr_t addr )
  1194     struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
  1195     return ent->vpn | ent->asid | (ent->flags & TLB_VALID);
  1198 void FASTCALL mmu_itlb_addr_write( sh4addr_t addr, uint32_t val )
  1200     struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
  1201     ent->vpn = val & 0xFFFFFC00;
  1202     ent->asid = val & 0x000000FF;
  1203     ent->flags = (ent->flags & ~(TLB_VALID)) | (val&TLB_VALID);
  1206 int32_t FASTCALL mmu_itlb_data_read( sh4addr_t addr )
  1208     struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
  1209     return (ent->ppn & 0x1FFFFC00) | ent->flags;
  1212 void FASTCALL mmu_itlb_data_write( sh4addr_t addr, uint32_t val )
  1214     struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
  1215     ent->ppn = val & 0x1FFFFC00;
  1216     ent->flags = val & 0x00001DA;
  1217     ent->mask = get_tlb_size_mask(val);
  1218     if( ent->ppn >= 0x1C000000 )
  1219         ent->ppn |= 0xE0000000;
  1222 #define UTLB_ENTRY(addr) ((addr>>8)&0x3F)
  1223 #define UTLB_ASSOC(addr) (addr&0x80)
  1224 #define UTLB_DATA2(addr) (addr&0x00800000)
  1226 int32_t FASTCALL mmu_utlb_addr_read( sh4addr_t addr )
  1228     struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
  1229     return ent->vpn | ent->asid | (ent->flags & TLB_VALID) |
  1230     ((ent->flags & TLB_DIRTY)<<7);
  1232 int32_t FASTCALL mmu_utlb_data_read( sh4addr_t addr )
  1234     struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
  1235     if( UTLB_DATA2(addr) ) {
  1236         return ent->pcmcia;
  1237     } else {
  1238         return (ent->ppn&0x1FFFFC00) | ent->flags;
  1242 /**
  1243  * Find a UTLB entry for the associative TLB write - same as the normal
  1244  * lookup but ignores the valid bit.
  1245  */
  1246 static inline int mmu_utlb_lookup_assoc( uint32_t vpn, uint32_t asid )
  1248     int result = -1;
  1249     unsigned int i;
  1250     for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
  1251         if( (mmu_utlb[i].flags & TLB_VALID) &&
  1252                 ((mmu_utlb[i].flags & TLB_SHARE) || asid == mmu_utlb[i].asid) &&
  1253                 ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
  1254             if( result != -1 ) {
  1255                 fprintf( stderr, "TLB Multi hit: %d %d\n", result, i );
  1256                 return -2;
  1258             result = i;
  1261     return result;
  1264 /**
  1265  * Find a ITLB entry for the associative TLB write - same as the normal
  1266  * lookup but ignores the valid bit.
  1267  */
  1268 static inline int mmu_itlb_lookup_assoc( uint32_t vpn, uint32_t asid )
  1270     int result = -1;
  1271     unsigned int i;
  1272     for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
  1273         if( (mmu_itlb[i].flags & TLB_VALID) &&
  1274                 ((mmu_itlb[i].flags & TLB_SHARE) || asid == mmu_itlb[i].asid) &&
  1275                 ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
  1276             if( result != -1 ) {
  1277                 return -2;
  1279             result = i;
  1282     return result;
  1285 void FASTCALL mmu_utlb_addr_write( sh4addr_t addr, uint32_t val, void *exc )
  1287     if( UTLB_ASSOC(addr) ) {
  1288         int utlb = mmu_utlb_lookup_assoc( val, mmu_asid );
  1289         if( utlb >= 0 ) {
  1290             struct utlb_entry *ent = &mmu_utlb[utlb];
  1291             uint32_t old_flags = ent->flags;
  1292             ent->flags = ent->flags & ~(TLB_DIRTY|TLB_VALID);
  1293             ent->flags |= (val & TLB_VALID);
  1294             ent->flags |= ((val & 0x200)>>7);
  1295             if( ((old_flags^ent->flags) & (TLB_VALID|TLB_DIRTY)) != 0 ) {
  1296                 if( old_flags & TLB_VALID )
  1297                     mmu_utlb_remove_entry( utlb );
  1298                 if( ent->flags & TLB_VALID )
  1299                     mmu_utlb_insert_entry( utlb );
  1303         int itlb = mmu_itlb_lookup_assoc( val, mmu_asid );
  1304         if( itlb >= 0 ) {
  1305             struct itlb_entry *ent = &mmu_itlb[itlb];
  1306             ent->flags = (ent->flags & (~TLB_VALID)) | (val & TLB_VALID);
  1309         if( itlb == -2 || utlb == -2 ) {
  1310             RAISE_TLB_MULTIHIT_ERROR(addr);
  1311             EXCEPTION_EXIT();
  1312             return;
  1314     } else {
  1315         struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
  1316         if( ent->flags & TLB_VALID ) 
  1317             mmu_utlb_remove_entry( UTLB_ENTRY(addr) );
  1318         ent->vpn = (val & 0xFFFFFC00);
  1319         ent->asid = (val & 0xFF);
  1320         ent->flags = (ent->flags & ~(TLB_DIRTY|TLB_VALID));
  1321         ent->flags |= (val & TLB_VALID);
  1322         ent->flags |= ((val & 0x200)>>7);
  1323         if( ent->flags & TLB_VALID ) 
  1324             mmu_utlb_insert_entry( UTLB_ENTRY(addr) );
  1328 void FASTCALL mmu_utlb_data_write( sh4addr_t addr, uint32_t val )
  1330     struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
  1331     if( UTLB_DATA2(addr) ) {
  1332         ent->pcmcia = val & 0x0000000F;
  1333     } else {
  1334         if( ent->flags & TLB_VALID ) 
  1335             mmu_utlb_remove_entry( UTLB_ENTRY(addr) );
  1336         ent->ppn = (val & 0x1FFFFC00);
  1337         ent->flags = (val & 0x000001FF);
  1338         ent->mask = get_tlb_size_mask(val);
  1339         if( ent->flags & TLB_VALID ) 
  1340             mmu_utlb_insert_entry( UTLB_ENTRY(addr) );
  1344 struct mem_region_fn p4_region_itlb_addr = {
  1345         mmu_itlb_addr_read, mmu_itlb_addr_write,
  1346         mmu_itlb_addr_read, mmu_itlb_addr_write,
  1347         mmu_itlb_addr_read, mmu_itlb_addr_write,
  1348         unmapped_read_burst, unmapped_write_burst,
  1349         unmapped_prefetch };
  1350 struct mem_region_fn p4_region_itlb_data = {
  1351         mmu_itlb_data_read, mmu_itlb_data_write,
  1352         mmu_itlb_data_read, mmu_itlb_data_write,
  1353         mmu_itlb_data_read, mmu_itlb_data_write,
  1354         unmapped_read_burst, unmapped_write_burst,
  1355         unmapped_prefetch };
  1356 struct mem_region_fn p4_region_utlb_addr = {
  1357         mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
  1358         mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
  1359         mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
  1360         unmapped_read_burst, unmapped_write_burst,
  1361         unmapped_prefetch };
  1362 struct mem_region_fn p4_region_utlb_data = {
  1363         mmu_utlb_data_read, mmu_utlb_data_write,
  1364         mmu_utlb_data_read, mmu_utlb_data_write,
  1365         mmu_utlb_data_read, mmu_utlb_data_write,
  1366         unmapped_read_burst, unmapped_write_burst,
  1367         unmapped_prefetch };
  1369 /********************** Error regions **************************/
  1371 static void FASTCALL address_error_read( sh4addr_t addr, void *exc ) 
  1373     RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
  1374     EXCEPTION_EXIT();
  1377 static void FASTCALL address_error_read_burst( unsigned char *dest, sh4addr_t addr, void *exc ) 
  1379     RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
  1380     EXCEPTION_EXIT();
  1383 static void FASTCALL address_error_write( sh4addr_t addr, uint32_t val, void *exc )
  1385     RAISE_MEM_ERROR(EXC_DATA_ADDR_WRITE, addr);
  1386     EXCEPTION_EXIT();
  1389 static void FASTCALL tlb_miss_read( sh4addr_t addr, void *exc )
  1391     RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
  1392     EXCEPTION_EXIT();
  1395 static void FASTCALL tlb_miss_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
  1397     RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
  1398     EXCEPTION_EXIT();
  1401 static void FASTCALL tlb_miss_write( sh4addr_t addr, uint32_t val, void *exc )
  1403     RAISE_TLB_ERROR(EXC_TLB_MISS_WRITE, addr);
  1404     EXCEPTION_EXIT();
  1407 static int32_t FASTCALL tlb_protected_read( sh4addr_t addr, void *exc )
  1409     RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
  1410     EXCEPTION_EXIT();
  1413 static int32_t FASTCALL tlb_protected_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
  1415     RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
  1416     EXCEPTION_EXIT();
  1419 static void FASTCALL tlb_protected_write( sh4addr_t addr, uint32_t val, void *exc )
  1421     RAISE_MEM_ERROR(EXC_TLB_PROT_WRITE, addr);
  1422     EXCEPTION_EXIT();
  1425 static void FASTCALL tlb_initial_write( sh4addr_t addr, uint32_t val, void *exc )
  1427     RAISE_MEM_ERROR(EXC_INIT_PAGE_WRITE, addr);
  1428     EXCEPTION_EXIT();
  1431 static int32_t FASTCALL tlb_multi_hit_read( sh4addr_t addr, void *exc )
  1433     sh4_raise_tlb_multihit(addr);
  1434     EXCEPTION_EXIT();
  1437 static int32_t FASTCALL tlb_multi_hit_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
  1439     sh4_raise_tlb_multihit(addr);
  1440     EXCEPTION_EXIT();
  1442 static void FASTCALL tlb_multi_hit_write( sh4addr_t addr, uint32_t val, void *exc )
  1444     sh4_raise_tlb_multihit(addr);
  1445     EXCEPTION_EXIT();
  1448 /**
  1449  * Note: Per sec 4.6.4 of the SH7750 manual, SQ 
  1450  */
  1451 struct mem_region_fn mem_region_address_error = {
  1452         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1453         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1454         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1455         (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
  1456         unmapped_prefetch };
  1458 struct mem_region_fn mem_region_tlb_miss = {
  1459         (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
  1460         (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
  1461         (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
  1462         (mem_read_burst_fn_t)tlb_miss_read_burst, (mem_write_burst_fn_t)tlb_miss_write,
  1463         unmapped_prefetch };
  1465 struct mem_region_fn mem_region_tlb_protected = {
  1466         (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
  1467         (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
  1468         (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
  1469         (mem_read_burst_fn_t)tlb_protected_read_burst, (mem_write_burst_fn_t)tlb_protected_write,
  1470         unmapped_prefetch };
  1472 struct mem_region_fn mem_region_tlb_multihit = {
  1473         (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
  1474         (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
  1475         (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
  1476         (mem_read_burst_fn_t)tlb_multi_hit_read_burst, (mem_write_burst_fn_t)tlb_multi_hit_write,
  1477         (mem_prefetch_fn_t)tlb_multi_hit_read };
  1480 /* Store-queue regions */
  1481 /* These are a bit of a pain - the first 8 fields are controlled by SQMD, while 
  1482  * the final (prefetch) is controlled by the actual TLB settings (plus SQMD in
  1483  * some cases), in contrast to the ordinary fields above.
  1485  * There is probably a simpler way to do this.
  1486  */
  1488 struct mem_region_fn p4_region_storequeue = { 
  1489         ccn_storequeue_read_long, ccn_storequeue_write_long,
  1490         unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
  1491         unmapped_read_long, unmapped_write_long,
  1492         unmapped_read_burst, unmapped_write_burst,
  1493         ccn_storequeue_prefetch }; 
  1495 struct mem_region_fn p4_region_storequeue_miss = { 
  1496         ccn_storequeue_read_long, ccn_storequeue_write_long,
  1497         unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
  1498         unmapped_read_long, unmapped_write_long,
  1499         unmapped_read_burst, unmapped_write_burst,
  1500         (mem_prefetch_fn_t)tlb_miss_read }; 
  1502 struct mem_region_fn p4_region_storequeue_multihit = { 
  1503         ccn_storequeue_read_long, ccn_storequeue_write_long,
  1504         unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
  1505         unmapped_read_long, unmapped_write_long,
  1506         unmapped_read_burst, unmapped_write_burst,
  1507         (mem_prefetch_fn_t)tlb_multi_hit_read }; 
  1509 struct mem_region_fn p4_region_storequeue_protected = {
  1510         ccn_storequeue_read_long, ccn_storequeue_write_long,
  1511         unmapped_read_long, unmapped_write_long,
  1512         unmapped_read_long, unmapped_write_long,
  1513         unmapped_read_burst, unmapped_write_burst,
  1514         (mem_prefetch_fn_t)tlb_protected_read };
  1516 struct mem_region_fn p4_region_storequeue_sqmd = {
  1517         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1518         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1519         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1520         (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
  1521         (mem_prefetch_fn_t)address_error_read };        
  1523 struct mem_region_fn p4_region_storequeue_sqmd_miss = { 
  1524         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1525         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1526         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1527         (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
  1528         (mem_prefetch_fn_t)tlb_miss_read }; 
  1530 struct mem_region_fn p4_region_storequeue_sqmd_multihit = {
  1531         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1532         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1533         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1534         (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
  1535         (mem_prefetch_fn_t)tlb_multi_hit_read };        
  1537 struct mem_region_fn p4_region_storequeue_sqmd_protected = {
  1538         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1539         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1540         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1541         (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
  1542         (mem_prefetch_fn_t)tlb_protected_read };
.